Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2016 Allwinnertech Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2017-2018 Bootlin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/phy/phy-mipi-dphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SUN6I_DPHY_GCTL_REG		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SUN6I_DPHY_GCTL_LANE_NUM(n)		((((n) - 1) & 3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SUN6I_DPHY_GCTL_EN			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SUN6I_DPHY_TX_CTL_REG		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT	BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SUN6I_DPHY_TX_TIME0_REG		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n)		(((n) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n)	(((n) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n)	((n) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SUN6I_DPHY_TX_TIME1_REG		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SUN6I_DPHY_TX_TIME1_CLK_POST(n)		(((n) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SUN6I_DPHY_TX_TIME1_CLK_PRE(n)		(((n) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SUN6I_DPHY_TX_TIME1_CLK_ZERO(n)		(((n) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n)	((n) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SUN6I_DPHY_TX_TIME2_REG		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n)	((n) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SUN6I_DPHY_TX_TIME3_REG		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SUN6I_DPHY_TX_TIME4_REG		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n)	(((n) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n)	((n) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SUN6I_DPHY_ANA0_REG		0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SUN6I_DPHY_ANA0_REG_PWS			BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SUN6I_DPHY_ANA0_REG_DMPC		BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SUN6I_DPHY_ANA0_REG_DMPD(n)		(((n) & 0xf) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SUN6I_DPHY_ANA0_REG_SLV(n)		(((n) & 7) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SUN6I_DPHY_ANA0_REG_DEN(n)		(((n) & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SUN6I_DPHY_ANA1_REG		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SUN6I_DPHY_ANA1_REG_VTTMODE		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SUN6I_DPHY_ANA1_REG_CSMPS(n)		(((n) & 3) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SUN6I_DPHY_ANA1_REG_SVTT(n)		(((n) & 0xf) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SUN6I_DPHY_ANA2_REG		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SUN6I_DPHY_ANA2_EN_P2S_CPU(n)		(((n) & 0xf) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK		GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SUN6I_DPHY_ANA2_EN_CK_CPU		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SUN6I_DPHY_ANA2_REG_ENIB		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SUN6I_DPHY_ANA3_REG		0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SUN6I_DPHY_ANA3_EN_VTTD(n)		(((n) & 0xf) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SUN6I_DPHY_ANA3_EN_VTTD_MASK		GENMASK(31, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SUN6I_DPHY_ANA3_EN_VTTC			BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SUN6I_DPHY_ANA3_EN_DIV			BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SUN6I_DPHY_ANA3_EN_LDOC			BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SUN6I_DPHY_ANA3_EN_LDOD			BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SUN6I_DPHY_ANA3_EN_LDOR			BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SUN6I_DPHY_ANA4_REG		0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SUN6I_DPHY_ANA4_REG_DMPLVC		BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define SUN6I_DPHY_ANA4_REG_DMPLVD(n)		(((n) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SUN6I_DPHY_ANA4_REG_CKDV(n)		(((n) & 0x1f) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SUN6I_DPHY_ANA4_REG_TMSC(n)		(((n) & 3) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SUN6I_DPHY_ANA4_REG_TMSD(n)		(((n) & 3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define SUN6I_DPHY_ANA4_REG_TXDNSC(n)		(((n) & 3) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SUN6I_DPHY_ANA4_REG_TXDNSD(n)		(((n) & 3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define SUN6I_DPHY_ANA4_REG_TXPUSC(n)		(((n) & 3) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SUN6I_DPHY_ANA4_REG_TXPUSD(n)		((n) & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SUN6I_DPHY_DBG5_REG		0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) struct sun6i_dphy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct clk				*bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct clk				*mod_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct regmap				*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct reset_control			*reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct phy				*phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct phy_configure_opts_mipi_dphy	config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int sun6i_dphy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct sun6i_dphy *dphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	reset_control_deassert(dphy->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	clk_prepare_enable(dphy->mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	clk_set_rate_exclusive(dphy->mod_clk, 150000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct sun6i_dphy *dphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	memcpy(&dphy->config, opts, sizeof(dphy->config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int sun6i_dphy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct sun6i_dphy *dphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		     SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		     SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		     SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		     SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		     SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		     SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		     SUN6I_DPHY_TX_TIME1_CLK_POST(10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		     SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		     SUN6I_DPHY_GCTL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		     SUN6I_DPHY_ANA0_REG_PWS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		     SUN6I_DPHY_ANA0_REG_DMPC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		     SUN6I_DPHY_ANA0_REG_SLV(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		     SUN6I_DPHY_ANA0_REG_DMPD(lanes_mask) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		     SUN6I_DPHY_ANA0_REG_DEN(lanes_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		     SUN6I_DPHY_ANA1_REG_CSMPS(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		     SUN6I_DPHY_ANA1_REG_SVTT(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		     SUN6I_DPHY_ANA4_REG_CKDV(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		     SUN6I_DPHY_ANA4_REG_TMSC(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		     SUN6I_DPHY_ANA4_REG_TMSD(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		     SUN6I_DPHY_ANA4_REG_TXDNSC(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		     SUN6I_DPHY_ANA4_REG_TXDNSD(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		     SUN6I_DPHY_ANA4_REG_TXPUSC(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		     SUN6I_DPHY_ANA4_REG_TXPUSD(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		     SUN6I_DPHY_ANA4_REG_DMPLVC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		     SUN6I_DPHY_ANA4_REG_DMPLVD(lanes_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		     SUN6I_DPHY_ANA2_REG_ENIB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		     SUN6I_DPHY_ANA3_EN_LDOR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		     SUN6I_DPHY_ANA3_EN_LDOC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		     SUN6I_DPHY_ANA3_EN_LDOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			   SUN6I_DPHY_ANA3_EN_VTTC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			   SUN6I_DPHY_ANA3_EN_VTTD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			   SUN6I_DPHY_ANA3_EN_VTTC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			   SUN6I_DPHY_ANA3_EN_VTTD(lanes_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			   SUN6I_DPHY_ANA3_EN_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			   SUN6I_DPHY_ANA3_EN_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			   SUN6I_DPHY_ANA2_EN_CK_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			   SUN6I_DPHY_ANA2_EN_CK_CPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			   SUN6I_DPHY_ANA1_REG_VTTMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			   SUN6I_DPHY_ANA1_REG_VTTMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int sun6i_dphy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct sun6i_dphy *dphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			   SUN6I_DPHY_ANA1_REG_VTTMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int sun6i_dphy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct sun6i_dphy *dphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	clk_rate_exclusive_put(dphy->mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	clk_disable_unprepare(dphy->mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	reset_control_assert(dphy->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct phy_ops sun6i_dphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.configure	= sun6i_dphy_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.power_on	= sun6i_dphy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.power_off	= sun6i_dphy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.init		= sun6i_dphy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.exit		= sun6i_dphy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const struct regmap_config sun6i_dphy_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.reg_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.val_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.reg_stride	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.max_register	= SUN6I_DPHY_DBG5_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.name		= "mipi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int sun6i_dphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct sun6i_dphy *dphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (!dphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (IS_ERR(regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	dphy->regs = devm_regmap_init_mmio_clk(&pdev->dev, "bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 					       regs, &sun6i_dphy_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (IS_ERR(dphy->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		dev_err(&pdev->dev, "Couldn't create the DPHY encoder regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return PTR_ERR(dphy->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	dphy->reset = devm_reset_control_get_shared(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (IS_ERR(dphy->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		dev_err(&pdev->dev, "Couldn't get our reset line\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return PTR_ERR(dphy->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	dphy->mod_clk = devm_clk_get(&pdev->dev, "mod");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (IS_ERR(dphy->mod_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		dev_err(&pdev->dev, "Couldn't get the DPHY mod clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return PTR_ERR(dphy->mod_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	dphy->phy = devm_phy_create(&pdev->dev, NULL, &sun6i_dphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (IS_ERR(dphy->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		dev_err(&pdev->dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		return PTR_ERR(dphy->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	phy_set_drvdata(dphy->phy, dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct of_device_id sun6i_dphy_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	{ .compatible = "allwinner,sun6i-a31-mipi-dphy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct platform_driver sun6i_dphy_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.probe		= sun6i_dphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.name		= "sun6i-mipi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.of_match_table	= sun6i_dphy_of_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) module_platform_driver(sun6i_dphy_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_AUTHOR("Maxime Ripard <maxime.ripard@bootlin>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DESCRIPTION("Allwinner A31 MIPI D-PHY Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MODULE_LICENSE("GPL");