^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Allwinner sun50i(H6) USB 3.0 phy driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on phy-sun9i-usb.c, which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Based on code from Allwinner BSP, which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Interface Status and Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SUNXI_ISCR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SUNXI_PIPE_CLOCK_CONTROL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SUNXI_PHY_TUNE_LOW 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SUNXI_PHY_TUNE_HIGH 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SUNXI_PHY_EXTERNAL_CONTROL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* USB2.0 Interface Status and Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUNXI_ISCR_FORCE_VBUS (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* PIPE Clock Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* PHY External Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SUNXI_PEC_EXTERN_VBUS (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUNXI_PEC_SSC_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUNXI_PEC_REF_SSP_EN (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* PHY Tune High Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUNXI_TX_SWING_FULL(n) ((n) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SUNXI_LOS_BIAS(n) ((n) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SUNXI_LOS_BIAS_MASK GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SUNXI_TXVBOOSTLVL(n) ((n) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SUNXI_TXVBOOSTLVL_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct sun50i_usb3_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) val |= SUNXI_PEC_EXTERN_VBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) val |= SUNXI_PCC_PIPE_CLK_OPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) val = readl(phy->regs + SUNXI_ISCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) val |= SUNXI_ISCR_FORCE_VBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) writel(val, phy->regs + SUNXI_ISCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * All the magic numbers written to the PHY_TUNE_{LOW_HIGH}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * registers are directly taken from the BSP USB3 driver from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Allwiner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SUNXI_TX_DEEMPH_3P5DB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) val |= SUNXI_TXVBOOSTLVL(0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) val |= SUNXI_LOS_BIAS(0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) val |= SUNXI_TX_SWING_FULL(0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val |= SUNXI_TX_DEEMPH_6DB(0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val |= SUNXI_TX_DEEMPH_3P5DB(0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int sun50i_usb3_phy_init(struct phy *_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = clk_prepare_enable(phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = reset_control_deassert(phy->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clk_disable_unprepare(phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) sun50i_usb3_phy_open(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int sun50i_usb3_phy_exit(struct phy *_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) reset_control_assert(phy->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clk_disable_unprepare(phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct phy_ops sun50i_usb3_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .init = sun50i_usb3_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .exit = sun50i_usb3_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int sun50i_usb3_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct sun50i_usb3_phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) phy->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (IS_ERR(phy->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (PTR_ERR(phy->clk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(dev, "failed to get phy clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return PTR_ERR(phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) phy->reset = devm_reset_control_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (IS_ERR(phy->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_err(dev, "failed to get reset control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return PTR_ERR(phy->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) phy->regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (IS_ERR(phy->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return PTR_ERR(phy->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (IS_ERR(phy->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return PTR_ERR(phy->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) phy_set_drvdata(phy->phy, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct of_device_id sun50i_usb3_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { .compatible = "allwinner,sun50i-h6-usb3-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct platform_driver sun50i_usb3_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .probe = sun50i_usb3_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .of_match_table = sun50i_usb3_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .name = "sun50i-usb3-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) module_platform_driver(sun50i_usb3_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MODULE_DESCRIPTION("Allwinner H6 USB 3.0 phy driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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