^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the L3 cache PMUs in Qualcomm Technologies chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * The driver supports a distributed cache architecture where the overall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * cache for a socket is comprised of multiple slices each with its own PMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Access to each individual PMU is provided even though all CPUs share all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the slices. User space needs to aggregate to individual counts to provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * a global picture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * See Documentation/admin-guide/perf/qcom_l3_pmu.rst for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * General constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Number of counters on each PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define L3_NUM_COUNTERS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Mask for the event type field within perf_event_attr.config and EVTYPE reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define L3_EVTYPE_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Bit position of the 'long counter' flag within perf_event_attr.config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Reserve some space between the event type and this flag to allow expansion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * in the event type field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define L3_EVENT_LC_BIT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Perfmon registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define L3_HML3_PM_CR 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define L3_HML3_PM_EVCNTR(__cntr) (0x420 + ((__cntr) & 0x7) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define L3_HML3_PM_CNTCTL(__cntr) (0x120 + ((__cntr) & 0x7) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define L3_HML3_PM_EVTYPE(__cntr) (0x220 + ((__cntr) & 0x7) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define L3_HML3_PM_FILTRA 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define L3_HML3_PM_FILTRB 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define L3_HML3_PM_FILTRC 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define L3_HML3_PM_FILTRAM 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define L3_HML3_PM_FILTRBM 0x30C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define L3_HML3_PM_FILTRCM 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Basic counter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define L3_M_BC_CR 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define L3_M_BC_SATROLL_CR 0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define L3_M_BC_CNTENSET 0x508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define L3_M_BC_CNTENCLR 0x50C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define L3_M_BC_INTENSET 0x510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define L3_M_BC_INTENCLR 0x514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define L3_M_BC_GANG 0x718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define L3_M_BC_OVSR 0x740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define L3_M_BC_IRQCTL 0x96C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Bit field definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* L3_HML3_PM_CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PM_CR_RESET (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* L3_HML3_PM_XCNTCTL/L3_HML3_PM_CNTCTLx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PMCNT_RESET (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* L3_HML3_PM_EVTYPEx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EVSEL(__val) ((__val) & L3_EVTYPE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Reset value for all the filter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PM_FLTR_RESET (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* L3_M_BC_CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BC_RESET (1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BC_ENABLE (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* L3_M_BC_SATROLL_CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BC_SATROLL_CR_RESET (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* L3_M_BC_CNTENSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PMCNTENSET(__cntr) (1UL << ((__cntr) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* L3_M_BC_CNTENCLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PMCNTENCLR(__cntr) (1UL << ((__cntr) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BC_CNTENCLR_RESET (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* L3_M_BC_INTENSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PMINTENSET(__cntr) (1UL << ((__cntr) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* L3_M_BC_INTENCLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PMINTENCLR(__cntr) (1UL << ((__cntr) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BC_INTENCLR_RESET (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* L3_M_BC_GANG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GANG_EN(__cntr) (1UL << ((__cntr) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BC_GANG_RESET (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* L3_M_BC_OVSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PMOVSRCLR(__cntr) (1UL << ((__cntr) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PMOVSRCLR_RESET (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* L3_M_BC_IRQCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PMIRQONMSBEN(__cntr) (1UL << ((__cntr) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BC_IRQCTL_RESET (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define L3_EVENT_CYCLES 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define L3_EVENT_READ_HIT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define L3_EVENT_READ_MISS 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define L3_EVENT_READ_HIT_D 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define L3_EVENT_READ_MISS_D 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define L3_EVENT_WRITE_HIT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define L3_EVENT_WRITE_MISS 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Decoding of settings from perf_event_attr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * The config format for perf events is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * - config: bits 0-7: event type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * bit 32: HW counter size requested, 0: 32 bits, 1: 64 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline u32 get_event_type(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return (event->attr.config) & L3_EVTYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline bool event_uses_long_counter(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return !!(event->attr.config & BIT_ULL(L3_EVENT_LC_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline int event_num_counters(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return event_uses_long_counter(event) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Main PMU, inherits from the core perf PMU type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct l3cache_pmu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pmu pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct hlist_node node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct perf_event *events[L3_NUM_COUNTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long used_mask[BITS_TO_LONGS(L3_NUM_COUNTERS)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) cpumask_t cpumask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define to_l3cache_pmu(p) (container_of(p, struct l3cache_pmu, pmu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Type used to group hardware counter operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * Used to implement two types of hardware counters, standard (32bits) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * long (64bits). The hardware supports counter chaining which we use to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * implement long counters. This support is exposed via the 'lc' flag field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * in perf_event_attr.config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct l3cache_event_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Called to start event monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void (*start)(struct perf_event *event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Called to stop event monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void (*stop)(struct perf_event *event, int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Called to update the perf_event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void (*update)(struct perf_event *event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Implementation of long counter operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * 64bit counters are implemented by chaining two of the 32bit physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * counters. The PMU only supports chaining of adjacent even/odd pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * and for simplicity the driver always configures the odd counter to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * count the overflows of the lower-numbered even counter. Note that since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * the resulting hardware counter is 64bits no IRQs are required to maintain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * the software counter which is also 64bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void qcom_l3_cache__64bit_counter_start(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int idx = event->hw.idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 evsel = get_event_type(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 gang;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Set the odd counter to count the overflows of the even counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) gang = readl_relaxed(l3pmu->regs + L3_M_BC_GANG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) gang |= GANG_EN(idx + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) writel_relaxed(gang, l3pmu->regs + L3_M_BC_GANG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Initialize the hardware counters and reset prev_count*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) local64_set(&event->hw.prev_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * Set the event types, the upper half must use zero and the lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * half the actual event type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) writel_relaxed(EVSEL(0), l3pmu->regs + L3_HML3_PM_EVTYPE(idx + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) writel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Finally, enable the counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel_relaxed(PMCNTENSET(idx + 1), l3pmu->regs + L3_M_BC_CNTENSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void qcom_l3_cache__64bit_counter_stop(struct perf_event *event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int idx = event->hw.idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 gang = readl_relaxed(l3pmu->regs + L3_M_BC_GANG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Disable the counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writel_relaxed(PMCNTENCLR(idx), l3pmu->regs + L3_M_BC_CNTENCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) writel_relaxed(PMCNTENCLR(idx + 1), l3pmu->regs + L3_M_BC_CNTENCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Disable chaining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) writel_relaxed(gang & ~GANG_EN(idx + 1), l3pmu->regs + L3_M_BC_GANG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void qcom_l3_cache__64bit_counter_update(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int idx = event->hw.idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 hi, lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u64 prev, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) prev = local64_read(&event->hw.prev_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) hi = readl_relaxed(l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) lo = readl_relaxed(l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } while (hi != readl_relaxed(l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) new = ((u64)hi << 32) | lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) local64_add(new - prev, &event->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const struct l3cache_event_ops event_ops_long = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .start = qcom_l3_cache__64bit_counter_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .stop = qcom_l3_cache__64bit_counter_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .update = qcom_l3_cache__64bit_counter_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Implementation of standard counter operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * 32bit counters use a single physical counter and a hardware feature that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * asserts the overflow IRQ on the toggling of the most significant bit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * the counter. This feature allows the counters to be left free-running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * without needing the usual reprogramming required to properly handle races
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * during concurrent calls to update.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void qcom_l3_cache__32bit_counter_start(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int idx = event->hw.idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 evsel = get_event_type(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 irqctl = readl_relaxed(l3pmu->regs + L3_M_BC_IRQCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Set the counter to assert the overflow IRQ on MSB toggling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writel_relaxed(irqctl | PMIRQONMSBEN(idx), l3pmu->regs + L3_M_BC_IRQCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Initialize the hardware counter and reset prev_count*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) local64_set(&event->hw.prev_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Set the event type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) writel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Enable interrupt generation by this counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writel_relaxed(PMINTENSET(idx), l3pmu->regs + L3_M_BC_INTENSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Finally, enable the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void qcom_l3_cache__32bit_counter_stop(struct perf_event *event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int idx = event->hw.idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 irqctl = readl_relaxed(l3pmu->regs + L3_M_BC_IRQCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Disable the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) writel_relaxed(PMCNTENCLR(idx), l3pmu->regs + L3_M_BC_CNTENCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Disable interrupt generation by this counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) writel_relaxed(PMINTENCLR(idx), l3pmu->regs + L3_M_BC_INTENCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Set the counter to not assert the overflow IRQ on MSB toggling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) writel_relaxed(irqctl & ~PMIRQONMSBEN(idx), l3pmu->regs + L3_M_BC_IRQCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static void qcom_l3_cache__32bit_counter_update(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int idx = event->hw.idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 prev, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) prev = local64_read(&event->hw.prev_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) new = readl_relaxed(l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) local64_add(new - prev, &event->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct l3cache_event_ops event_ops_std = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .start = qcom_l3_cache__32bit_counter_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .stop = qcom_l3_cache__32bit_counter_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .update = qcom_l3_cache__32bit_counter_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Retrieve the appropriate operations for the given event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) const struct l3cache_event_ops *l3cache_event_get_ops(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (event_uses_long_counter(event))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return &event_ops_long;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return &event_ops_std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Top level PMU functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static inline void qcom_l3_cache__init(struct l3cache_pmu *l3pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) writel_relaxed(BC_RESET, l3pmu->regs + L3_M_BC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Use writel for the first programming command to ensure the basic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * counter unit is stopped before proceeding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writel(BC_SATROLL_CR_RESET, l3pmu->regs + L3_M_BC_SATROLL_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) writel_relaxed(BC_CNTENCLR_RESET, l3pmu->regs + L3_M_BC_CNTENCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writel_relaxed(BC_INTENCLR_RESET, l3pmu->regs + L3_M_BC_INTENCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) writel_relaxed(PMOVSRCLR_RESET, l3pmu->regs + L3_M_BC_OVSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) writel_relaxed(BC_GANG_RESET, l3pmu->regs + L3_M_BC_GANG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writel_relaxed(BC_IRQCTL_RESET, l3pmu->regs + L3_M_BC_IRQCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) writel_relaxed(PM_CR_RESET, l3pmu->regs + L3_HML3_PM_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) for (i = 0; i < L3_NUM_COUNTERS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) writel_relaxed(EVSEL(0), l3pmu->regs + L3_HML3_PM_EVTYPE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRBM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) writel_relaxed(PM_FLTR_RESET, l3pmu->regs + L3_HML3_PM_FILTRCM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * Use writel here to ensure all programming commands are done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * before proceeding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) writel(BC_ENABLE, l3pmu->regs + L3_M_BC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static irqreturn_t qcom_l3_cache__handle_irq(int irq_num, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct l3cache_pmu *l3pmu = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Read the overflow status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) long status = readl_relaxed(l3pmu->regs + L3_M_BC_OVSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Clear the bits we read on the overflow status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) writel_relaxed(status, l3pmu->regs + L3_M_BC_OVSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) for_each_set_bit(idx, &status, L3_NUM_COUNTERS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct perf_event *event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) const struct l3cache_event_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) event = l3pmu->events[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Since the IRQ is not enabled for events using long counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * we should never see one of those here, however, be consistent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * and use the ops indirections like in the other operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ops = l3cache_event_get_ops(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ops->update(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * Implementation of abstract pmu functionality required by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * the core perf events code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void qcom_l3_cache__pmu_enable(struct pmu *pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct l3cache_pmu *l3pmu = to_l3cache_pmu(pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Ensure the other programming commands are observed before enabling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) writel_relaxed(BC_ENABLE, l3pmu->regs + L3_M_BC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static void qcom_l3_cache__pmu_disable(struct pmu *pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct l3cache_pmu *l3pmu = to_l3cache_pmu(pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) writel_relaxed(0, l3pmu->regs + L3_M_BC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Ensure the basic counter unit is stopped before proceeding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * We must NOT create groups containing events from multiple hardware PMUs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * although mixing different software and hardware PMUs is allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static bool qcom_l3_cache__validate_event_group(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct perf_event *leader = event->group_leader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct perf_event *sibling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int counters = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (leader->pmu != event->pmu && !is_software_event(leader))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) counters = event_num_counters(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) counters += event_num_counters(leader);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) for_each_sibling_event(sibling, leader) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (is_software_event(sibling))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (sibling->pmu != event->pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) counters += event_num_counters(sibling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * If the group requires more counters than the HW has, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * cannot ever be scheduled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return counters <= L3_NUM_COUNTERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int qcom_l3_cache__event_init(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * Is the event for this PMU?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (event->attr.type != event->pmu->type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * Sampling not supported since these events are not core-attributable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (hwc->sample_period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * Task mode not available, we run the counters as socket counters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * not attributable to any CPU and therefore cannot attribute per-task.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (event->cpu < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Validate the group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (!qcom_l3_cache__validate_event_group(event))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) hwc->idx = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * Many perf core operations (eg. events rotation) operate on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * single CPU context. This is obvious for CPU PMUs, where one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * expects the same sets of events being observed on all CPUs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * but can lead to issues for off-core PMUs, like this one, where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * each event could be theoretically assigned to a different CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * To mitigate this, we enforce CPU assignment to one designated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * processor (the one described in the "cpumask" attribute exported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * by the PMU device). perf user space tools honor this and avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * opening more than one copy of the events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) event->cpu = cpumask_first(&l3pmu->cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static void qcom_l3_cache__event_start(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) const struct l3cache_event_ops *ops = l3cache_event_get_ops(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hwc->state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ops->start(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static void qcom_l3_cache__event_stop(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) const struct l3cache_event_ops *ops = l3cache_event_get_ops(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (hwc->state & PERF_HES_STOPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ops->stop(event, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (flags & PERF_EF_UPDATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ops->update(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int qcom_l3_cache__event_add(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int order = event_uses_long_counter(event) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * Try to allocate a counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) idx = bitmap_find_free_region(l3pmu->used_mask, L3_NUM_COUNTERS, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (idx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* The counters are all in use. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) hwc->idx = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) l3pmu->events[idx] = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (flags & PERF_EF_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) qcom_l3_cache__event_start(event, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Propagate changes to the userspace mapping. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) perf_event_update_userpage(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static void qcom_l3_cache__event_del(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct l3cache_pmu *l3pmu = to_l3cache_pmu(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int order = event_uses_long_counter(event) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Stop and clean up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) qcom_l3_cache__event_stop(event, flags | PERF_EF_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) l3pmu->events[hwc->idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) bitmap_release_region(l3pmu->used_mask, hwc->idx, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Propagate changes to the userspace mapping. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) perf_event_update_userpage(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static void qcom_l3_cache__event_read(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) const struct l3cache_event_ops *ops = l3cache_event_get_ops(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ops->update(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * Add sysfs attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * We export:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * - formats, used by perf user space and other tools to configure events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * - events, used by perf user space and other tools to create events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * symbolically, e.g.:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * perf stat -a -e l3cache_0_0/event=read-miss/ ls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * perf stat -a -e l3cache_0_0/event=0x21/ ls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * - cpumask, used by perf user space and other tools to know on which CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * to open the events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static ssize_t l3cache_pmu_format_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct dev_ext_attribute *eattr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) eattr = container_of(attr, struct dev_ext_attribute, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return sprintf(buf, "%s\n", (char *) eattr->var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define L3CACHE_PMU_FORMAT_ATTR(_name, _config) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) (&((struct dev_ext_attribute[]) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) { .attr = __ATTR(_name, 0444, l3cache_pmu_format_show, NULL), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .var = (void *) _config, } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) })[0].attr.attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static struct attribute *qcom_l3_cache_pmu_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) L3CACHE_PMU_FORMAT_ATTR(event, "config:0-7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) L3CACHE_PMU_FORMAT_ATTR(lc, "config:" __stringify(L3_EVENT_LC_BIT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static struct attribute_group qcom_l3_cache_pmu_format_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .name = "format",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .attrs = qcom_l3_cache_pmu_formats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static ssize_t l3cache_pmu_event_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct device_attribute *attr, char *page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct perf_pmu_events_attr *pmu_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define L3CACHE_EVENT_ATTR(_name, _id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) (&((struct perf_pmu_events_attr[]) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) { .attr = __ATTR(_name, 0444, l3cache_pmu_event_show, NULL), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .id = _id, } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) })[0].attr.attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static struct attribute *qcom_l3_cache_pmu_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) L3CACHE_EVENT_ATTR(cycles, L3_EVENT_CYCLES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) L3CACHE_EVENT_ATTR(read-hit, L3_EVENT_READ_HIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) L3CACHE_EVENT_ATTR(read-miss, L3_EVENT_READ_MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) L3CACHE_EVENT_ATTR(read-hit-d-side, L3_EVENT_READ_HIT_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) L3CACHE_EVENT_ATTR(read-miss-d-side, L3_EVENT_READ_MISS_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) L3CACHE_EVENT_ATTR(write-hit, L3_EVENT_WRITE_HIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) L3CACHE_EVENT_ATTR(write-miss, L3_EVENT_WRITE_MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static struct attribute_group qcom_l3_cache_pmu_events_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .name = "events",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .attrs = qcom_l3_cache_pmu_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* cpumask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static ssize_t qcom_l3_cache_pmu_cpumask_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct l3cache_pmu *l3pmu = to_l3cache_pmu(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return cpumap_print_to_pagebuf(true, buf, &l3pmu->cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static DEVICE_ATTR(cpumask, 0444, qcom_l3_cache_pmu_cpumask_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static struct attribute *qcom_l3_cache_pmu_cpumask_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) &dev_attr_cpumask.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static struct attribute_group qcom_l3_cache_pmu_cpumask_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .attrs = qcom_l3_cache_pmu_cpumask_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * Per PMU device attribute groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static const struct attribute_group *qcom_l3_cache_pmu_attr_grps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) &qcom_l3_cache_pmu_format_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) &qcom_l3_cache_pmu_events_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) &qcom_l3_cache_pmu_cpumask_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * Probing functions and data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int qcom_l3_cache_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct l3cache_pmu *l3pmu = hlist_entry_safe(node, struct l3cache_pmu, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* If there is not a CPU/PMU association pick this CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (cpumask_empty(&l3pmu->cpumask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) cpumask_set_cpu(cpu, &l3pmu->cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int qcom_l3_cache_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct l3cache_pmu *l3pmu = hlist_entry_safe(node, struct l3cache_pmu, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) unsigned int target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (!cpumask_test_and_clear_cpu(cpu, &l3pmu->cpumask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) target = cpumask_any_but(cpu_online_mask, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (target >= nr_cpu_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) perf_pmu_migrate_context(&l3pmu->pmu, cpu, target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) cpumask_set_cpu(target, &l3pmu->cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int qcom_l3_cache_pmu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct l3cache_pmu *l3pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct acpi_device *acpi_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct resource *memrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* Initialize the PMU data structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) acpi_dev = ACPI_COMPANION(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!acpi_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) l3pmu = devm_kzalloc(&pdev->dev, sizeof(*l3pmu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "l3cache_%s_%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) acpi_dev->parent->pnp.unique_id, acpi_dev->pnp.unique_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (!l3pmu || !name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) l3pmu->pmu = (struct pmu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .task_ctx_nr = perf_invalid_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .pmu_enable = qcom_l3_cache__pmu_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .pmu_disable = qcom_l3_cache__pmu_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .event_init = qcom_l3_cache__event_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .add = qcom_l3_cache__event_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .del = qcom_l3_cache__event_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .start = qcom_l3_cache__event_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .stop = qcom_l3_cache__event_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .read = qcom_l3_cache__event_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .attr_groups = qcom_l3_cache_pmu_attr_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) memrc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) l3pmu->regs = devm_ioremap_resource(&pdev->dev, memrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (IS_ERR(l3pmu->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) dev_err(&pdev->dev, "Can't map PMU @%pa\n", &memrc->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return PTR_ERR(l3pmu->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) qcom_l3_cache__init(l3pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ret = devm_request_irq(&pdev->dev, ret, qcom_l3_cache__handle_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) name, l3pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dev_err(&pdev->dev, "Request for IRQ failed for slice @%pa\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) &memrc->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* Add this instance to the list used by the offline callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE, &l3pmu->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dev_err(&pdev->dev, "Error %d registering hotplug", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = perf_pmu_register(&l3pmu->pmu, name, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_err(&pdev->dev, "Failed to register L3 cache PMU (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dev_info(&pdev->dev, "Registered %s, type: %d\n", name, l3pmu->pmu.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static const struct acpi_device_id qcom_l3_cache_pmu_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) { "QCOM8081", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) MODULE_DEVICE_TABLE(acpi, qcom_l3_cache_pmu_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static struct platform_driver qcom_l3_cache_pmu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .name = "qcom-l3cache-pmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .acpi_match_table = ACPI_PTR(qcom_l3_cache_pmu_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .probe = qcom_l3_cache_pmu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static int __init register_qcom_l3_cache_pmu_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* Install a hook to update the reader CPU in case it goes offline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "perf/qcom/l3cache:online",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) qcom_l3_cache_pmu_online_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) qcom_l3_cache_pmu_offline_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return platform_driver_register(&qcom_l3_cache_pmu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) device_initcall(register_qcom_l3_cache_pmu_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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