Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * ACPI probing code for ARM performance counters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/irqdesc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/perf/arm_pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) static DEFINE_PER_CPU(struct arm_pmu *, probed_pmus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static DEFINE_PER_CPU(int, pmu_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static int arm_pmu_acpi_register_irq(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct acpi_madt_generic_interrupt *gicc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	int gsi, trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	gicc = acpi_cpu_get_madt_gicc(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	gsi = gicc->performance_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	 * Per the ACPI spec, the MADT cannot describe a PMU that doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	 * have an interrupt. QEMU advertises this by using a GSI of zero,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	 * which is not known to be valid on any hardware despite being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	 * valid per the spec. Take the pragmatic approach and reject a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	 * GSI of zero for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	if (!gsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		trigger = ACPI_EDGE_SENSITIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		trigger = ACPI_LEVEL_SENSITIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	 * Helpfully, the MADT GICC doesn't have a polarity flag for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	 * "performance interrupt". Luckily, on compliant GICs the polarity is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	 * a fixed value in HW (for both SPIs and PPIs) that we cannot change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	 * from SW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	 * Here we pass in ACPI_ACTIVE_HIGH to keep the core code happy. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	 * may not match the real polarity, but that should not matter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	 * Other interrupt controllers are not supported with ACPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return acpi_register_gsi(NULL, gsi, trigger, ACPI_ACTIVE_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static void arm_pmu_acpi_unregister_irq(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct acpi_madt_generic_interrupt *gicc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	int gsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	gicc = acpi_cpu_get_madt_gicc(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	gsi = gicc->performance_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (gsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		acpi_unregister_gsi(gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #if IS_ENABLED(CONFIG_ARM_SPE_PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static struct resource spe_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		/* irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.flags          = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static struct platform_device spe_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.name = ARMV8_SPE_PDEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.resource = spe_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.num_resources = ARRAY_SIZE(spe_resources)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * For lack of a better place, hook the normal PMU MADT walk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * and create a SPE device if we detect a recent MADT with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * a homogeneous PPI mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void arm_spe_acpi_register_device(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int cpu, hetid, irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	bool first = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u16 gsi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * Sanity check all the GICC tables for the same interrupt number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 * For now, we only support homogeneous ACPI/SPE machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		struct acpi_madt_generic_interrupt *gicc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		gicc = acpi_cpu_get_madt_gicc(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		if (gicc->header.length < ACPI_MADT_GICC_SPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		if (first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			gsi = gicc->spe_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			if (!gsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			hetid = find_acpi_cpu_topology_hetero_id(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			first = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		} else if ((gsi != gicc->spe_interrupt) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			   (hetid != find_acpi_cpu_topology_hetero_id(cpu))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			pr_warn("ACPI: SPE must be homogeneous\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				ACPI_ACTIVE_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		pr_warn("ACPI: SPE Unable to register interrupt: %d\n", gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	spe_resources[0].start = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	ret = platform_device_register(&spe_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		pr_warn("ACPI: SPE: Unable to register device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		acpi_unregister_gsi(gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline void arm_spe_acpi_register_device(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #endif /* CONFIG_ARM_SPE_PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int arm_pmu_acpi_parse_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	int irq, cpu, irq_cpu, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		irq = arm_pmu_acpi_register_irq(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			err = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			pr_warn("Unable to parse ACPI PMU IRQ for CPU%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				cpu, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		} else if (irq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			pr_warn("No ACPI PMU IRQ for CPU%d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		 * Log and request the IRQ so the core arm_pmu code can manage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		 * it. We'll have to sanity-check IRQs later when we associate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		 * them with their PMUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		per_cpu(pmu_irqs, cpu) = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		armpmu_request_irq(irq, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		irq = per_cpu(pmu_irqs, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		arm_pmu_acpi_unregister_irq(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		 * Blat all copies of the IRQ so that we only unregister the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		 * corresponding GSI once (e.g. when we have PPIs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		for_each_possible_cpu(irq_cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			if (per_cpu(pmu_irqs, irq_cpu) == irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 				per_cpu(pmu_irqs, irq_cpu) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct arm_pmu *arm_pmu_acpi_find_alloc_pmu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	unsigned long cpuid = read_cpuid_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct arm_pmu *pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		pmu = per_cpu(probed_pmus, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		if (!pmu || pmu->acpi_cpuid != cpuid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	pmu = armpmu_alloc_atomic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (!pmu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		pr_warn("Unable to allocate PMU for CPU%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	pmu->acpi_cpuid = cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * Check whether the new IRQ is compatible with those already associated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * the PMU (e.g. we don't have mismatched PPIs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static bool pmu_irq_matches(struct arm_pmu *pmu, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	for_each_cpu(cpu, &pmu->supported_cpus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		int other_irq = per_cpu(hw_events->irq, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		if (!other_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		if (irq == other_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		if (!irq_is_percpu_devid(irq) && !irq_is_percpu_devid(other_irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		pr_warn("mismatched PPIs detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  * This must run before the common arm_pmu hotplug logic, so that we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  * associate a CPU and its interrupt before the common code tries to manage the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  * affinity and so on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  * Note that hotplug events are serialized, so we cannot race with another CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  * coming up. The perf core won't open events while a hotplug event is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  * progress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int arm_pmu_acpi_cpu_starting(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct arm_pmu *pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct pmu_hw_events __percpu *hw_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	/* If we've already probed this CPU, we have nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (per_cpu(probed_pmus, cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	irq = per_cpu(pmu_irqs, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	pmu = arm_pmu_acpi_find_alloc_pmu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (!pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	per_cpu(probed_pmus, cpu) = pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (pmu_irq_matches(pmu, irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		hw_events = pmu->hw_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		per_cpu(hw_events->irq, cpu) = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	cpumask_set_cpu(cpu, &pmu->supported_cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 * Ideally, we'd probe the PMU here when we find the first matching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 * CPU. We can't do that for several reasons; see the comment in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	 * arm_pmu_acpi_init().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	 * So for the time being, we're done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int arm_pmu_acpi_probe(armpmu_init_fn init_fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	int pmu_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	int cpu, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	 * Initialise and register the set of PMUs which we know about right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	 * now. Ideally we'd do this in arm_pmu_acpi_cpu_starting() so that we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	 * could handle late hotplug, but this may lead to deadlock since we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	 * might try to register a hotplug notifier instance from within a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	 * hotplug notifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	 * There's also the problem of having access to the right init_fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	 * without tying this too deeply into the "real" PMU driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	 * For the moment, as with the platform/DT case, we need at least one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	 * of a PMU's CPUs to be online at probe time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		struct arm_pmu *pmu = per_cpu(probed_pmus, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		char *base_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		if (!pmu || pmu->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		ret = init_fn(pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		if (ret == -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			/* PMU not handled by this driver, or not present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		} else if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			pr_warn("Unable to initialise PMU for CPU%d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		base_name = pmu->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		pmu->name = kasprintf(GFP_KERNEL, "%s_%d", base_name, pmu_idx++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		if (!pmu->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			pr_warn("Unable to allocate PMU name for CPU%d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		ret = armpmu_register(pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			pr_warn("Failed to register PMU for CPU%d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			kfree(pmu->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int arm_pmu_acpi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (acpi_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	arm_spe_acpi_register_device();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	ret = arm_pmu_acpi_parse_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	ret = cpuhp_setup_state(CPUHP_AP_PERF_ARM_ACPI_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 				"perf/arm/pmu_acpi:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 				arm_pmu_acpi_cpu_starting, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) subsys_initcall(arm_pmu_acpi_init)