^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2016-2020 Arm Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // CMN-600 Coherent Mesh Network PMU driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sort.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Common register stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CMN_NODE_INFO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CMN_NI_NODE_ID GENMASK_ULL(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CMN_NODEID_DEVID(reg) ((reg) & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CMN_NODEID_PID(reg) (((reg) >> 2) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CMN_NODEID_X(reg, bits) ((reg) >> (3 + (bits)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CMN_NODEID_Y(reg, bits) (((reg) >> 3) & ((1U << (bits)) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CMN_CHILD_INFO 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CMN_CHILD_NODE_ADDR GENMASK(27,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CMN_CHILD_NODE_EXTERNAL BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CMN_ADDR_NODE_PTR GENMASK(27, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CMN_NODE_PTR_DEVID(ptr) (((ptr) >> 2) & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CMN_NODE_PTR_PID(ptr) ((ptr) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CMN_NODE_PTR_X(ptr, bits) ((ptr) >> (6 + (bits)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CMN_NODE_PTR_Y(ptr, bits) (((ptr) >> 6) & ((1U << (bits)) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CMN_MAX_XPS (8 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* The CFG node has one other useful purpose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CMN_CFGM_PERIPH_ID_2 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CMN_CFGM_PID2_REVISION GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* PMU registers occupy the 3rd 4KB page of each node's 16KB space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CMN_PMU_OFFSET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* For most nodes, this is all there is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CMN_PMU_EVENT_SEL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CMN_PMU_EVENTn_ID_SHIFT(n) ((n) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* DTMs live in the PMU space of XP registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CMN_DTM_WPn_CONFIG_WP_GRP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CMN_DTM_WPn_MASK(n) (CMN_DTM_WPn(n) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CMN_DTM_PMU_CONFIG 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CMN__PMEVCNT0_INPUT_SEL_WP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CMN__PMEVCNT0_INPUT_SEL_XP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CMN__PMEVCNT0_INPUT_SEL_DEV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n) ((n) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CMN__PMEVCNT_PAIRED(n) BIT(4 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CMN__PMEVCNT23_COMBINED BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CMN__PMEVCNT01_COMBINED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CMN_DTM_PMU_CONFIG_PMU_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CMN_DTM_PMEVCNT 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CMN_DTM_PMEVCNTSR 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CMN_DTM_NUM_COUNTERS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* The DTC node is where the magic happens */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CMN_DT_DTC_CTL 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CMN_DT_DTC_CTL_DT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define _CMN_DT_CNT_REG(n) ((((n) / 2) * 4 + (n) % 2) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CMN_DT_PMEVCNT(n) (CMN_PMU_OFFSET + _CMN_DT_CNT_REG(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CMN_DT_PMCCNTR (CMN_PMU_OFFSET + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CMN_DT_PMEVCNTSR(n) (CMN_PMU_OFFSET + 0x50 + _CMN_DT_CNT_REG(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CMN_DT_PMCCNTRSR (CMN_PMU_OFFSET + 0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CMN_DT_PMCR (CMN_PMU_OFFSET + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CMN_DT_PMCR_PMU_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CMN_DT_PMCR_CNTR_RST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CMN_DT_PMCR_OVFL_INTR_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CMN_DT_PMOVSR (CMN_PMU_OFFSET + 0x118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CMN_DT_PMOVSR_CLR (CMN_PMU_OFFSET + 0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CMN_DT_PMSSR (CMN_PMU_OFFSET + 0x128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CMN_DT_PMSSR_SS_STATUS(n) BIT(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CMN_DT_PMSRR (CMN_PMU_OFFSET + 0x130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CMN_DT_PMSRR_SS_REQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CMN_DT_NUM_COUNTERS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CMN_MAX_DTCS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * so throwing away one bit to make overflow handling easy is no big deal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CMN_COUNTER_INIT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Similarly for the 40-bit cycle counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CMN_CC_INIT 0x8000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Event attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CMN_CONFIG_TYPE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CMN_CONFIG_EVENTID GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CMN_CONFIG_OCCUPID GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CMN_CONFIG_BYNODEID BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CMN_CONFIG_NODEID GENMASK(47, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CMN_EVENT_OCCUPID(event) FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CMN_CONFIG_WP_COMBINE GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CMN_CONFIG_WP_DEV_SEL BIT(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CMN_CONFIG_WP_CHN_SEL GENMASK(50, 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CMN_CONFIG_WP_GRP BIT(52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CMN_CONFIG_WP_EXCLUSIVE BIT(53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CMN_CONFIG1_WP_VAL GENMASK(63, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CMN_CONFIG2_WP_MASK GENMASK(63, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CMN_EVENT_WP_CHN_SEL(event) FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CMN_EVENT_WP_GRP(event) FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CMN_EVENT_WP_EXCLUSIVE(event) FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CMN_EVENT_WP_VAL(event) FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CMN_EVENT_WP_MASK(event) FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Made-up event IDs for watchpoint direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CMN_WP_UP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CMN_WP_DOWN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* r0px probably don't exist in silicon, thankfully */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) enum cmn_revision {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CMN600_R1P0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CMN600_R1P1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) CMN600_R1P2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CMN600_R1P3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) CMN600_R2P0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) CMN600_R3P0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) enum cmn_node_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) CMN_TYPE_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) CMN_TYPE_DVM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CMN_TYPE_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) CMN_TYPE_DTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CMN_TYPE_HNI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CMN_TYPE_HNF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CMN_TYPE_XP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CMN_TYPE_SBSX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CMN_TYPE_RNI = 0xa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) CMN_TYPE_RND = 0xd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) CMN_TYPE_RNSAM = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) CMN_TYPE_CXRA = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CMN_TYPE_CXHA = 0x101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) CMN_TYPE_CXLA = 0x102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Not a real node type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) CMN_TYPE_WP = 0x7770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct arm_cmn_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void __iomem *pmu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u16 id, logid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) enum cmn_node_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Device node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int to_xp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* DN/HN-F/CXHA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int occupid_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int occupid_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* XP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int dtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 pmu_config_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 input_sel[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) __le32 pmu_config_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) s8 wp_event[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 event[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) __le32 event_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct arm_cmn_dtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int irq_friend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) bool cc_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct perf_event *counters[CMN_DT_NUM_COUNTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct perf_event *cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CMN_STATE_DISABLED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CMN_STATE_TXN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct arm_cmn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) enum cmn_revision rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 mesh_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u8 mesh_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u16 num_xps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u16 num_dns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct arm_cmn_node *xps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct arm_cmn_node *dns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct arm_cmn_dtc *dtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int num_dtcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct hlist_node cpuhp_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct pmu pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define to_cmn(p) container_of(p, struct arm_cmn, pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int arm_cmn_hp_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct arm_cmn_hw_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct arm_cmn_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u64 dtm_idx[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int dtc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 dtcs_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 num_dns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define for_each_hw_dn(hw, dn, i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) BUILD_BUG_ON(sizeof(struct arm_cmn_hw_event) > offsetof(struct hw_perf_event, target));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return (struct arm_cmn_hw_event *)&event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) x[pos / 32] |= (u64)val << ((pos % 32) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return (x[pos / 32] >> ((pos % 32) * 2)) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct arm_cmn_event_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct device_attribute attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) enum cmn_node_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u8 eventid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 occupid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct arm_cmn_format_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct device_attribute attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u64 field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int arm_cmn_xyidbits(const struct arm_cmn *cmn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return cmn->mesh_x > 4 || cmn->mesh_y > 4 ? 3 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void arm_cmn_init_node_to_xp(const struct arm_cmn *cmn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct arm_cmn_node *dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int bits = arm_cmn_xyidbits(cmn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int x = CMN_NODEID_X(dn->id, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int y = CMN_NODEID_Y(dn->id, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int xp_idx = cmn->mesh_x * y + x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dn->to_xp = (cmn->xps + xp_idx) - dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct arm_cmn_node *arm_cmn_node_to_xp(struct arm_cmn_node *dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return dn->type == CMN_TYPE_XP ? dn : dn + dn->to_xp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) enum cmn_node_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) for (i = 0; i < cmn->num_dns; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (cmn->dns[i].type == type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return &cmn->dns[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CMN_EVENT_ATTR(_name, _type, _eventid, _occupid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) (&((struct arm_cmn_event_attr[]) {{ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .type = _type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .eventid = _eventid, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .occupid = _occupid, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }})[0].attr.attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static bool arm_cmn_is_occup_event(enum cmn_node_type type, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return (type == CMN_TYPE_DVM && id == 0x05) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) (type == CMN_TYPE_HNF && id == 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static ssize_t arm_cmn_event_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct arm_cmn_event_attr *eattr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) eattr = container_of(attr, typeof(*eattr), attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (eattr->type == CMN_TYPE_DTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return snprintf(buf, PAGE_SIZE, "type=0x%x\n", eattr->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (eattr->type == CMN_TYPE_WP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return snprintf(buf, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) eattr->type, eattr->eventid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (arm_cmn_is_occup_event(eattr->type, eattr->eventid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return snprintf(buf, PAGE_SIZE, "type=0x%x,eventid=0x%x,occupid=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) eattr->type, eattr->eventid, eattr->occupid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return snprintf(buf, PAGE_SIZE, "type=0x%x,eventid=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) eattr->type, eattr->eventid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct device *dev = kobj_to_dev(kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct arm_cmn_event_attr *eattr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) enum cmn_node_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) eattr = container_of(attr, typeof(*eattr), attr.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) type = eattr->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Watchpoints aren't nodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (type == CMN_TYPE_WP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) type = CMN_TYPE_XP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Revision-specific differences */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (cmn->rev < CMN600_R1P2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (type == CMN_TYPE_HNF && eattr->eventid == 0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!arm_cmn_node(cmn, type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define _CMN_EVENT_DVM(_name, _event, _occup) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) CMN_EVENT_ATTR(dn_##_name, CMN_TYPE_DVM, _event, _occup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define CMN_EVENT_DTC(_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) CMN_EVENT_ATTR(dtc_##_name, CMN_TYPE_DTC, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define _CMN_EVENT_HNF(_name, _event, _occup) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) CMN_EVENT_ATTR(hnf_##_name, CMN_TYPE_HNF, _event, _occup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define CMN_EVENT_HNI(_name, _event) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) CMN_EVENT_ATTR(hni_##_name, CMN_TYPE_HNI, _event, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define __CMN_EVENT_XP(_name, _event) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) CMN_EVENT_ATTR(mxp_##_name, CMN_TYPE_XP, _event, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define CMN_EVENT_SBSX(_name, _event) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) CMN_EVENT_ATTR(sbsx_##_name, CMN_TYPE_SBSX, _event, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define CMN_EVENT_RNID(_name, _event) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) CMN_EVENT_ATTR(rnid_##_name, CMN_TYPE_RNI, _event, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define CMN_EVENT_DVM(_name, _event) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) _CMN_EVENT_DVM(_name, _event, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define CMN_EVENT_HNF(_name, _event) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) _CMN_EVENT_HNF(_name, _event, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define _CMN_EVENT_XP(_name, _event) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Good thing there are only 3 fundamental XP events... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define CMN_EVENT_XP(_name, _event) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct attribute *arm_cmn_event_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) CMN_EVENT_DTC(cycles),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * DVM node events conflict with HN-I events in the equivalent PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * slot, but our lazy short-cut of using the DTM counter index for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * the PMU index as well happens to avoid that by construction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) CMN_EVENT_DVM(rxreq_dvmop, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) CMN_EVENT_DVM(rxreq_dvmsync, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) CMN_EVENT_DVM(rxreq_dvmop_vmid_filtered, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) CMN_EVENT_DVM(rxreq_retried, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) _CMN_EVENT_DVM(rxreq_trk_occupancy_all, 0x05, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) _CMN_EVENT_DVM(rxreq_trk_occupancy_dvmop, 0x05, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) _CMN_EVENT_DVM(rxreq_trk_occupancy_dvmsync, 0x05, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) CMN_EVENT_HNF(cache_miss, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) CMN_EVENT_HNF(slc_sf_cache_access, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) CMN_EVENT_HNF(cache_fill, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) CMN_EVENT_HNF(pocq_retry, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) CMN_EVENT_HNF(pocq_reqs_recvd, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) CMN_EVENT_HNF(sf_hit, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) CMN_EVENT_HNF(sf_evictions, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) CMN_EVENT_HNF(dir_snoops_sent, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) CMN_EVENT_HNF(brd_snoops_sent, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) CMN_EVENT_HNF(slc_eviction, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) CMN_EVENT_HNF(slc_fill_invalid_way, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) CMN_EVENT_HNF(mc_retries, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) CMN_EVENT_HNF(mc_reqs, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) CMN_EVENT_HNF(qos_hh_retry, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) _CMN_EVENT_HNF(qos_pocq_occupancy_all, 0x0f, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) _CMN_EVENT_HNF(qos_pocq_occupancy_read, 0x0f, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) _CMN_EVENT_HNF(qos_pocq_occupancy_write, 0x0f, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) _CMN_EVENT_HNF(qos_pocq_occupancy_atomic, 0x0f, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) _CMN_EVENT_HNF(qos_pocq_occupancy_stash, 0x0f, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) CMN_EVENT_HNF(pocq_addrhaz, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) CMN_EVENT_HNF(pocq_atomic_addrhaz, 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) CMN_EVENT_HNF(ld_st_swp_adq_full, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) CMN_EVENT_HNF(cmp_adq_full, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) CMN_EVENT_HNF(txdat_stall, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) CMN_EVENT_HNF(txrsp_stall, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) CMN_EVENT_HNF(seq_full, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) CMN_EVENT_HNF(seq_hit, 0x17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) CMN_EVENT_HNF(snp_sent, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) CMN_EVENT_HNF(sfbi_dir_snp_sent, 0x19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) CMN_EVENT_HNF(sfbi_brd_snp_sent, 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) CMN_EVENT_HNF(snp_sent_untrk, 0x1b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) CMN_EVENT_HNF(intv_dirty, 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) CMN_EVENT_HNF(stash_snp_sent, 0x1d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) CMN_EVENT_HNF(stash_data_pull, 0x1e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) CMN_EVENT_HNF(snp_fwded, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) CMN_EVENT_HNI(rrt_rd_alloc, 0x25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) CMN_EVENT_HNI(rrt_wr_alloc, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) CMN_EVENT_HNI(rdt_rd_alloc, 0x27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) CMN_EVENT_HNI(rdt_wr_alloc, 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) CMN_EVENT_HNI(wdb_alloc, 0x29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) CMN_EVENT_HNI(txrsp_retryack, 0x2a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) CMN_EVENT_HNI(arvalid_no_arready, 0x2b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) CMN_EVENT_HNI(arready_no_arvalid, 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) CMN_EVENT_HNI(awvalid_no_awready, 0x2d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) CMN_EVENT_HNI(awready_no_awvalid, 0x2e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) CMN_EVENT_HNI(wvalid_no_wready, 0x2f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) CMN_EVENT_HNI(txdat_stall, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) CMN_EVENT_HNI(nonpcie_serialization, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) CMN_EVENT_HNI(pcie_serialization, 0x32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) CMN_EVENT_XP(txflit_valid, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) CMN_EVENT_XP(txflit_stall, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) CMN_EVENT_XP(partial_dat_flit, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* We treat watchpoints as a special made-up class of XP events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) CMN_EVENT_ATTR(watchpoint_up, CMN_TYPE_WP, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) CMN_EVENT_ATTR(watchpoint_down, CMN_TYPE_WP, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) CMN_EVENT_SBSX(rd_req, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) CMN_EVENT_SBSX(wr_req, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) CMN_EVENT_SBSX(cmo_req, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) CMN_EVENT_SBSX(txrsp_retryack, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) CMN_EVENT_SBSX(txdat_flitv, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) CMN_EVENT_SBSX(txrsp_flitv, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) CMN_EVENT_SBSX(rd_req_trkr_occ_cnt_ovfl, 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) CMN_EVENT_SBSX(wr_req_trkr_occ_cnt_ovfl, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) CMN_EVENT_SBSX(cmo_req_trkr_occ_cnt_ovfl, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) CMN_EVENT_SBSX(wdb_occ_cnt_ovfl, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) CMN_EVENT_SBSX(rd_axi_trkr_occ_cnt_ovfl, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) CMN_EVENT_SBSX(cmo_axi_trkr_occ_cnt_ovfl, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) CMN_EVENT_SBSX(arvalid_no_arready, 0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) CMN_EVENT_SBSX(awvalid_no_awready, 0x22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) CMN_EVENT_SBSX(wvalid_no_wready, 0x23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) CMN_EVENT_SBSX(txdat_stall, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) CMN_EVENT_SBSX(txrsp_stall, 0x25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) CMN_EVENT_RNID(s0_rdata_beats, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) CMN_EVENT_RNID(s1_rdata_beats, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) CMN_EVENT_RNID(s2_rdata_beats, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) CMN_EVENT_RNID(rxdat_flits, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) CMN_EVENT_RNID(txdat_flits, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) CMN_EVENT_RNID(txreq_flits_total, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) CMN_EVENT_RNID(txreq_flits_retried, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) CMN_EVENT_RNID(rrt_occ_ovfl, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) CMN_EVENT_RNID(wrt_occ_ovfl, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) CMN_EVENT_RNID(txreq_flits_replayed, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) CMN_EVENT_RNID(wrcancel_sent, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) CMN_EVENT_RNID(s0_wdata_beats, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) CMN_EVENT_RNID(s1_wdata_beats, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) CMN_EVENT_RNID(s2_wdata_beats, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) CMN_EVENT_RNID(rrt_alloc, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) CMN_EVENT_RNID(wrt_alloc, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) CMN_EVENT_RNID(rdb_unord, 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) CMN_EVENT_RNID(rdb_replay, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) CMN_EVENT_RNID(rdb_hybrid, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) CMN_EVENT_RNID(rdb_ord, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static const struct attribute_group arm_cmn_event_attrs_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .name = "events",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .attrs = arm_cmn_event_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .is_visible = arm_cmn_event_attr_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static ssize_t arm_cmn_format_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int lo = __ffs(fmt->field), hi = __fls(fmt->field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (lo == hi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return snprintf(buf, PAGE_SIZE, "config:%d\n", lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!fmt->config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return snprintf(buf, PAGE_SIZE, "config:%d-%d\n", lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return snprintf(buf, PAGE_SIZE, "config%d:%d-%d\n", fmt->config, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define _CMN_FORMAT_ATTR(_name, _cfg, _fld) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) (&((struct arm_cmn_format_attr[]) {{ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .config = _cfg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .field = _fld, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }})[0].attr.attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define CMN_FORMAT_ATTR(_name, _fld) _CMN_FORMAT_ATTR(_name, 0, _fld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static struct attribute *arm_cmn_format_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) CMN_FORMAT_ATTR(occupid, CMN_CONFIG_OCCUPID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const struct attribute_group arm_cmn_format_attrs_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .name = "format",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .attrs = arm_cmn_format_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static ssize_t arm_cmn_cpumask_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static struct device_attribute arm_cmn_cpumask_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static struct attribute *arm_cmn_cpumask_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) &arm_cmn_cpumask_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static struct attribute_group arm_cmn_cpumask_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .attrs = arm_cmn_cpumask_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const struct attribute_group *arm_cmn_attr_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) &arm_cmn_event_attrs_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) &arm_cmn_format_attrs_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) &arm_cmn_cpumask_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int arm_cmn_wp_idx(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return CMN_EVENT_EVENTID(event) + CMN_EVENT_WP_GRP(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static u32 arm_cmn_wp_config(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 dev = CMN_EVENT_WP_DEV_SEL(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 chn = CMN_EVENT_WP_CHN_SEL(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 grp = CMN_EVENT_WP_GRP(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 exc = CMN_EVENT_WP_EXCLUSIVE(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u32 combine = CMN_EVENT_WP_COMBINE(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE, exc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (combine && !grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) config |= CMN_DTM_WPn_CONFIG_WP_COMBINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (!cmn->state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) cmn->state |= state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) cmn->state &= ~state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (!cmn->state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) cmn->dtc[0].base + CMN_DT_PMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static void arm_cmn_pmu_enable(struct pmu *pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static void arm_cmn_pmu_disable(struct pmu *pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) bool snapshot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct arm_cmn_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned int i, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u64 count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) for_each_hw_dn(hw, dn, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct arm_cmn_node *xp = arm_cmn_node_to_xp(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u64 reg = readq_relaxed(xp->pmu_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u16 dtm_count = reg >> (dtm_idx * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) count += dtm_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 val, pmevcnt = CMN_DT_PMEVCNT(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) val = readl_relaxed(dtc->base + pmevcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return val - CMN_COUNTER_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static void arm_cmn_init_counter(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct arm_cmn *cmn = to_cmn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct arm_cmn_hw_event *hw = to_cmn_hw(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) unsigned int i, pmevcnt = CMN_DT_PMEVCNT(hw->dtc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u64 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) for (i = 0; hw->dtcs_used & (1U << i); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + pmevcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) cmn->dtc[i].counters[hw->dtc_idx] = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) count = arm_cmn_read_dtm(cmn, hw, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) local64_set(&event->hw.prev_count, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static void arm_cmn_event_read(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct arm_cmn *cmn = to_cmn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct arm_cmn_hw_event *hw = to_cmn_hw(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u64 delta, new, prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (hw->dtc_idx == CMN_DT_NUM_COUNTERS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) i = __ffs(hw->dtcs_used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) delta = arm_cmn_read_cc(cmn->dtc + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) local64_add(delta, &event->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) new = arm_cmn_read_dtm(cmn, hw, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) prev = local64_xchg(&event->hw.prev_count, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) delta = new - prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) for (i = 0; hw->dtcs_used & (1U << i); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) new = arm_cmn_read_counter(cmn->dtc + i, hw->dtc_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) delta += new << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) local64_add(delta, &event->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static void arm_cmn_event_start(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct arm_cmn *cmn = to_cmn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct arm_cmn_hw_event *hw = to_cmn_hw(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct arm_cmn_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) enum cmn_node_type type = CMN_EVENT_TYPE(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (type == CMN_TYPE_DTC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) i = __ffs(hw->dtcs_used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) cmn->dtc[i].cc_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) } else if (type == CMN_TYPE_WP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int wp_idx = arm_cmn_wp_idx(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u64 val = CMN_EVENT_WP_VAL(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u64 mask = CMN_EVENT_WP_MASK(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) for_each_hw_dn(hw, dn, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) writeq_relaxed(val, dn->pmu_base + CMN_DTM_WPn_VAL(wp_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) writeq_relaxed(mask, dn->pmu_base + CMN_DTM_WPn_MASK(wp_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) } else for_each_hw_dn(hw, dn, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dn->event[dtm_idx] = CMN_EVENT_EVENTID(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static void arm_cmn_event_stop(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct arm_cmn *cmn = to_cmn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct arm_cmn_hw_event *hw = to_cmn_hw(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct arm_cmn_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) enum cmn_node_type type = CMN_EVENT_TYPE(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (type == CMN_TYPE_DTC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) i = __ffs(hw->dtcs_used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) cmn->dtc[i].cc_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) } else if (type == CMN_TYPE_WP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int wp_idx = arm_cmn_wp_idx(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) for_each_hw_dn(hw, dn, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) writeq_relaxed(0, dn->pmu_base + CMN_DTM_WPn_MASK(wp_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) writeq_relaxed(~0ULL, dn->pmu_base + CMN_DTM_WPn_VAL(wp_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) } else for_each_hw_dn(hw, dn, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dn->event[dtm_idx] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) arm_cmn_event_read(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct arm_cmn_val {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u8 dtm_count[CMN_MAX_XPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u8 occupid[CMN_MAX_XPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u8 wp[CMN_MAX_XPS][4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int dtc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) bool cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static void arm_cmn_val_add_event(struct arm_cmn_val *val, struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct arm_cmn_hw_event *hw = to_cmn_hw(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct arm_cmn_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) enum cmn_node_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u8 occupid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (is_software_event(event))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) type = CMN_EVENT_TYPE(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (type == CMN_TYPE_DTC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) val->cycles = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) val->dtc_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) occupid = CMN_EVENT_OCCUPID(event) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) occupid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) for_each_hw_dn(hw, dn, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int wp_idx, xp = arm_cmn_node_to_xp(dn)->logid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) val->dtm_count[xp]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) val->occupid[xp] = occupid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (type != CMN_TYPE_WP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) wp_idx = arm_cmn_wp_idx(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) val->wp[xp][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static int arm_cmn_validate_group(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct arm_cmn_hw_event *hw = to_cmn_hw(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct arm_cmn_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct perf_event *sibling, *leader = event->group_leader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) enum cmn_node_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct arm_cmn_val val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u8 occupid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (leader == event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (event->pmu != leader->pmu && !is_software_event(leader))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) memset(&val, 0, sizeof(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) arm_cmn_val_add_event(&val, leader);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) for_each_sibling_event(sibling, leader)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) arm_cmn_val_add_event(&val, sibling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) type = CMN_EVENT_TYPE(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (type == CMN_TYPE_DTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return val.cycles ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (val.dtc_count == CMN_DT_NUM_COUNTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) occupid = CMN_EVENT_OCCUPID(event) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) occupid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) for_each_hw_dn(hw, dn, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) int wp_idx, wp_cmb, xp = arm_cmn_node_to_xp(dn)->logid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (val.dtm_count[xp] == CMN_DTM_NUM_COUNTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (occupid && val.occupid[xp] && occupid != val.occupid[xp])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (type != CMN_TYPE_WP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) wp_idx = arm_cmn_wp_idx(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (val.wp[xp][wp_idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) wp_cmb = val.wp[xp][wp_idx ^ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (wp_cmb && wp_cmb != CMN_EVENT_WP_COMBINE(event) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static int arm_cmn_event_init(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct arm_cmn *cmn = to_cmn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct arm_cmn_hw_event *hw = to_cmn_hw(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) enum cmn_node_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) bool bynodeid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u16 nodeid, eventid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (event->attr.type != event->pmu->type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) event->cpu = cmn->cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (event->cpu < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) type = CMN_EVENT_TYPE(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* DTC events (i.e. cycles) already have everything they need */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (type == CMN_TYPE_DTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* For watchpoints we need the actual XP node here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (type == CMN_TYPE_WP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) type = CMN_TYPE_XP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* ...and we need a "real" direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) eventid = CMN_EVENT_EVENTID(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) bynodeid = CMN_EVENT_BYNODEID(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) nodeid = CMN_EVENT_NODEID(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) hw->dn = arm_cmn_node(cmn, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) for (i = hw->dn - cmn->dns; i < cmn->num_dns && cmn->dns[i].type == type; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (!bynodeid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) hw->num_dns++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) } else if (cmn->dns[i].id != nodeid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) hw->dn++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) hw->num_dns = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (!hw->num_dns) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) int bits = arm_cmn_xyidbits(cmn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dev_dbg(cmn->dev, "invalid node 0x%x (%d,%d,%d,%d) type 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) nodeid, CMN_NODEID_X(nodeid, bits), CMN_NODEID_Y(nodeid, bits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) CMN_NODEID_PID(nodeid), CMN_NODEID_DEVID(nodeid), type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * By assuming events count in all DTC domains, we cunningly avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * needing to know anything about how XPs are assigned to domains.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) hw->dtcs_used = (1U << cmn->num_dtcs) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return arm_cmn_validate_group(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct arm_cmn_hw_event *hw = to_cmn_hw(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) enum cmn_node_type type = CMN_EVENT_TYPE(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct arm_cmn_node *xp = arm_cmn_node_to_xp(hw->dn + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (type == CMN_TYPE_WP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) hw->dn[i].wp_event[arm_cmn_wp_idx(event)] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) hw->dn[i].occupid_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) xp->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) writel_relaxed(xp->pmu_config_low, xp->pmu_base + CMN_DTM_PMU_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) for (i = 0; hw->dtcs_used & (1U << i); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) cmn->dtc[i].counters[hw->dtc_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static int arm_cmn_event_add(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct arm_cmn *cmn = to_cmn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct arm_cmn_hw_event *hw = to_cmn_hw(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct arm_cmn_dtc *dtc = &cmn->dtc[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct arm_cmn_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) enum cmn_node_type type = CMN_EVENT_TYPE(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) unsigned int i, dtc_idx, input_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (type == CMN_TYPE_DTC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) while (cmn->dtc[i].cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (++i == cmn->num_dtcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) cmn->dtc[i].cycles = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) hw->dtc_idx = CMN_DT_NUM_COUNTERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) hw->dtcs_used = 1U << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (flags & PERF_EF_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) arm_cmn_event_start(event, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* Grab a free global counter first... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) dtc_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) while (dtc->counters[dtc_idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (++dtc_idx == CMN_DT_NUM_COUNTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) hw->dtc_idx = dtc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* ...then the local counters to feed it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) for_each_hw_dn(hw, dn, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct arm_cmn_node *xp = arm_cmn_node_to_xp(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) unsigned int dtm_idx, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) u64 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) dtm_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) while (xp->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (++dtm_idx == CMN_DTM_NUM_COUNTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) goto free_dtms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (type == CMN_TYPE_XP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) } else if (type == CMN_TYPE_WP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) int tmp, wp_idx = arm_cmn_wp_idx(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) u32 cfg = arm_cmn_wp_config(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (dn->wp_event[wp_idx] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) goto free_dtms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) tmp = dn->wp_event[wp_idx ^ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) CMN_EVENT_WP_COMBINE(dtc->counters[tmp]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) goto free_dtms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) dn->wp_event[wp_idx] = dtc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) writel_relaxed(cfg, dn->pmu_base + CMN_DTM_WPn_CONFIG(wp_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) unsigned int port = CMN_NODEID_PID(dn->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) unsigned int dev = CMN_NODEID_DEVID(dn->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) (port << 4) + (dev << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (arm_cmn_is_occup_event(type, CMN_EVENT_EVENTID(event))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) int occupid = CMN_EVENT_OCCUPID(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (dn->occupid_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dn->occupid_val = occupid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) writel_relaxed(occupid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dn->pmu_base + CMN_PMU_EVENT_SEL + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) } else if (dn->occupid_val != occupid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) goto free_dtms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dn->occupid_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) arm_cmn_set_index(hw->dtm_idx, i, dtm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) xp->input_sel[dtm_idx] = input_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) xp->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) xp->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) xp->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) reg = (u64)le32_to_cpu(xp->pmu_config_high) << 32 | xp->pmu_config_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) writeq_relaxed(reg, xp->pmu_base + CMN_DTM_PMU_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* Go go go! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) arm_cmn_init_counter(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (flags & PERF_EF_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) arm_cmn_event_start(event, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) free_dtms:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) arm_cmn_event_clear(cmn, event, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static void arm_cmn_event_del(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct arm_cmn *cmn = to_cmn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct arm_cmn_hw_event *hw = to_cmn_hw(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) enum cmn_node_type type = CMN_EVENT_TYPE(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) arm_cmn_event_stop(event, PERF_EF_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (type == CMN_TYPE_DTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) cmn->dtc[__ffs(hw->dtcs_used)].cycles = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) arm_cmn_event_clear(cmn, event, hw->num_dns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * We stop the PMU for both add and read, to avoid skew across DTM counters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * In theory we could use snapshots to read without stopping, but then it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * becomes a lot trickier to deal with overlow and racing against interrupts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * plus it seems they don't work properly on some hardware anyway :(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static void arm_cmn_end_txn(struct pmu *pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static int arm_cmn_commit_txn(struct pmu *pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) arm_cmn_end_txn(pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct arm_cmn *cmn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) unsigned int i, target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) cmn = hlist_entry_safe(node, struct arm_cmn, cpuhp_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (cpu != cmn->cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) target = cpumask_any_but(cpu_online_mask, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (target >= nr_cpu_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) perf_pmu_migrate_context(&cmn->pmu, cpu, target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) for (i = 0; i < cmn->num_dtcs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) irq_set_affinity_hint(cmn->dtc[i].irq, cpumask_of(target));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) cmn->cpu = target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct arm_cmn_dtc *dtc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u32 status = readl_relaxed(dtc->base + CMN_DT_PMOVSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) u64 delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) for (i = 0; i < CMN_DTM_NUM_COUNTERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (status & (1U << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (WARN_ON(!dtc->counters[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) delta = (u64)arm_cmn_read_counter(dtc, i) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) local64_add(delta, &dtc->counters[i]->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (status & (1U << CMN_DT_NUM_COUNTERS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (dtc->cc_active && !WARN_ON(!dtc->cycles)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) delta = arm_cmn_read_cc(dtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) local64_add(delta, &dtc->cycles->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (!dtc->irq_friend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) dtc += dtc->irq_friend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* We can reasonably accommodate DTCs of the same CMN sharing IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static int arm_cmn_init_irqs(struct arm_cmn *cmn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) int i, j, irq, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) for (i = 0; i < cmn->num_dtcs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) irq = cmn->dtc[i].irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) for (j = i; j--; ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (cmn->dtc[j].irq == irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) cmn->dtc[j].irq_friend = i - j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) IRQF_NOBALANCING | IRQF_NO_THREAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_name(cmn->dev), &cmn->dtc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) err = irq_set_affinity_hint(irq, cpumask_of(cmn->cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ; /* isn't C great? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static void arm_cmn_init_dtm(struct arm_cmn_node *xp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) xp->wp_event[i] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) writeq_relaxed(0, xp->pmu_base + CMN_DTM_WPn_MASK(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) writeq_relaxed(~0ULL, xp->pmu_base + CMN_DTM_WPn_VAL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) xp->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) xp->dtc = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct arm_cmn_dtc *dtc = cmn->dtc + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct arm_cmn_node *xp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) dtc->base = dn->pmu_base - CMN_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (dtc->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return dtc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) writel_relaxed(0, dtc->base + CMN_DT_PMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) writel_relaxed(CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* We do at least know that a DTC's XP must be in that DTC's domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) xp = arm_cmn_node_to_xp(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) xp->dtc = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static int arm_cmn_node_cmp(const void *a, const void *b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) const struct arm_cmn_node *dna = a, *dnb = b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) int cmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) cmp = dna->type - dnb->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (!cmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) cmp = dna->logid - dnb->logid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return cmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static int arm_cmn_init_dtcs(struct arm_cmn *cmn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct arm_cmn_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) int dtc_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (!cmn->dtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) for (dn = cmn->dns; dn < cmn->dns + cmn->num_dns; dn++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (dn->type != CMN_TYPE_XP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) arm_cmn_init_node_to_xp(cmn, dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) else if (cmn->num_dtcs == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dn->dtc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (dn->type == CMN_TYPE_DTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) arm_cmn_init_dtc(cmn, dn, dtc_idx++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (dn->type == CMN_TYPE_RND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dn->type = CMN_TYPE_RNI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) writel_relaxed(CMN_DT_DTC_CTL_DT_EN, cmn->dtc[0].base + CMN_DT_DTC_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) int level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) node->id = FIELD_GET(CMN_NI_NODE_ID, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) node->pmu_base = cmn->base + offset + CMN_PMU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (node->type == CMN_TYPE_CFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) else if (node->type == CMN_TYPE_XP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) level = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) level = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) node->type, node->logid, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) void __iomem *cfg_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct arm_cmn_node cfg, *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) u16 child_count, child_poff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) u32 xp_offset[CMN_MAX_XPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) u64 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) cfg_region = cmn->base + rgn_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) dev_dbg(cmn->dev, "periph_id_2 revision: %d\n", cmn->rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) arm_cmn_init_node_info(cmn, rgn_offset, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (cfg.type != CMN_TYPE_CFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) reg = readq_relaxed(cfg_region + CMN_CHILD_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) cmn->num_xps = child_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) cmn->num_dns = cmn->num_xps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /* Pass 1: visit the XPs, enumerate their children */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) for (i = 0; i < cmn->num_xps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) reg = readq_relaxed(cfg_region + child_poff + i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) xp_offset[i] = reg & CMN_CHILD_NODE_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) reg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* Cheeky +1 to help terminate pointer-based iteration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) cmn->dns = devm_kcalloc(cmn->dev, cmn->num_dns + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) sizeof(*cmn->dns), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (!cmn->dns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /* Pass 2: now we can actually populate the nodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) dn = cmn->dns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) for (i = 0; i < cmn->num_xps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) void __iomem *xp_region = cmn->base + xp_offset[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct arm_cmn_node *xp = dn++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) arm_cmn_init_node_info(cmn, xp_offset[i], xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) arm_cmn_init_dtm(xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * Thanks to the order in which XP logical IDs seem to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * assigned, we can handily infer the mesh X dimension by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * looking out for the XP at (0,1) without needing to know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * the exact node ID format, which we can later derive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (xp->id == (1 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) cmn->mesh_x = xp->logid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) reg = readq_relaxed(xp_region + CMN_CHILD_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) for (j = 0; j < child_count; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) reg = readq_relaxed(xp_region + child_poff + j * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * Don't even try to touch anything external, since in general
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * we haven't a clue how to power up arbitrary CHI requesters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * As of CMN-600r1 these could only be RN-SAMs or CXLAs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * neither of which have any PMU events anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * (Actually, CXLAs do seem to have grown some events in r1p2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * but they don't go to regular XP DTMs, and they depend on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * secure configuration which we can't easily deal with)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (reg & CMN_CHILD_NODE_EXTERNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) dev_dbg(cmn->dev, "ignoring external node %llx\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) switch (dn->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) case CMN_TYPE_DTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) cmn->num_dtcs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) dn++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /* These guys have PMU events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) case CMN_TYPE_DVM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) case CMN_TYPE_HNI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) case CMN_TYPE_HNF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) case CMN_TYPE_SBSX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) case CMN_TYPE_RNI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) case CMN_TYPE_RND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) case CMN_TYPE_CXRA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) case CMN_TYPE_CXHA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) dn++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* Nothing to see here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) case CMN_TYPE_RNSAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) case CMN_TYPE_CXLA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* Something has gone horribly wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) dev_err(cmn->dev, "invalid device node type: 0x%x\n", dn->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* Correct for any nodes we skipped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) cmn->num_dns = dn - cmn->dns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) * If mesh_x wasn't set during discovery then we never saw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * an XP at (0,1), thus we must have an Nx1 configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (!cmn->mesh_x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) cmn->mesh_x = cmn->num_xps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) cmn->mesh_y = cmn->num_xps / cmn->mesh_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) dev_dbg(cmn->dev, "mesh %dx%d, ID width %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static int arm_cmn_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) struct resource *cfg, *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (!cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) root = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (!root)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (!resource_contains(cfg, root))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) swap(cfg, root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) * Note that devm_ioremap_resource() is dumb and won't let the platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) * device claim cfg when the ACPI companion device has already claimed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) * root within it. But since they *are* already both claimed in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) * appropriate name, we don't really need to do it again here anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (!cmn->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return root->start - cfg->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static int arm_cmn_of_probe(struct platform_device *pdev, struct arm_cmn *cmn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) u32 rootnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) cmn->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (IS_ERR(cmn->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) return PTR_ERR(cmn->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ret = of_property_read_u32(np, "arm,root-node", &rootnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return rootnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static int arm_cmn_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) struct arm_cmn *cmn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static atomic_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) int err, rootnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (!cmn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) cmn->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) platform_set_drvdata(pdev, cmn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (has_acpi_companion(cmn->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) rootnode = arm_cmn_acpi_probe(pdev, cmn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) rootnode = arm_cmn_of_probe(pdev, cmn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (rootnode < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) return rootnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) err = arm_cmn_discover(cmn, rootnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) err = arm_cmn_init_dtcs(cmn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) err = arm_cmn_init_irqs(cmn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) cmn->cpu = raw_smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) cmn->pmu = (struct pmu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .attr_groups = arm_cmn_attr_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .task_ctx_nr = perf_invalid_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .pmu_enable = arm_cmn_pmu_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .pmu_disable = arm_cmn_pmu_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .event_init = arm_cmn_event_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .add = arm_cmn_event_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .del = arm_cmn_event_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .start = arm_cmn_event_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .stop = arm_cmn_event_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .read = arm_cmn_event_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .start_txn = arm_cmn_start_txn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .commit_txn = arm_cmn_commit_txn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .cancel_txn = arm_cmn_end_txn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", atomic_fetch_inc(&id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (!name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) err = perf_pmu_register(&cmn->pmu, name, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) cpuhp_state_remove_instance(arm_cmn_hp_state, &cmn->cpuhp_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static int arm_cmn_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) struct arm_cmn *cmn = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) perf_pmu_unregister(&cmn->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) cpuhp_state_remove_instance(arm_cmn_hp_state, &cmn->cpuhp_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) for (i = 0; i < cmn->num_dtcs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) irq_set_affinity_hint(cmn->dtc[i].irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static const struct of_device_id arm_cmn_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) { .compatible = "arm,cmn-600", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) MODULE_DEVICE_TABLE(of, arm_cmn_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static const struct acpi_device_id arm_cmn_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) { "ARMHC600", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static struct platform_driver arm_cmn_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .name = "arm-cmn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .of_match_table = of_match_ptr(arm_cmn_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .probe = arm_cmn_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .remove = arm_cmn_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) static int __init arm_cmn_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) "perf/arm/cmn:online", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) arm_cmn_pmu_offline_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) arm_cmn_hp_state = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) ret = platform_driver_register(&arm_cmn_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) cpuhp_remove_multi_state(arm_cmn_hp_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) static void __exit arm_cmn_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) platform_driver_unregister(&arm_cmn_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) cpuhp_remove_multi_state(arm_cmn_hp_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) module_init(arm_cmn_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) module_exit(arm_cmn_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) MODULE_AUTHOR("Robin Murphy <robin.murphy@arm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) MODULE_DESCRIPTION("Arm CMN-600 PMU driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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