^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/hrtimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/idr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CCN_NUM_XP_PORTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CCN_NUM_VCS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CCN_NUM_REGIONS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CCN_REGION_SIZE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CCN_ALL_OLY_ID 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CCN_MN_ERRINT_STATUS 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CCN_MN_OLY_COMP_LIST_63_0 0x01e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CCN_MN_ERR_SIG_VAL_63_0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CCN_DT_ACTIVE_DSM 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CCN_DT_CTL 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CCN_DT_CTL__DT_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CCN_DT_PMCCNTR 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CCN_DT_PMCCNTRSR 0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CCN_DT_PMOVSR 0x0198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CCN_DT_PMOVSR_CLR 0x01a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CCN_DT_PMOVSR_CLR__MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CCN_DT_PMCR 0x01a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CCN_DT_PMCR__PMU_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CCN_DT_PMSR 0x01b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CCN_DT_PMSR_REQ 0x01b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CCN_DT_PMSR_CLR 0x01c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CCN_HNF_PMU_EVENT_SEL 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CCN_XP_DT_CONFIG 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CCN_XP_DT_INTERFACE_SEL 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CCN_XP_DT_CONTROL 0x0370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CCN_XP_PMU_EVENT_SEL 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CCN_SBAS_PMU_EVENT_SEL 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CCN_RNI_PMU_EVENT_SEL 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CCN_TYPE_MN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CCN_TYPE_DT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CCN_TYPE_HNF 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CCN_TYPE_HNI 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CCN_TYPE_XP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CCN_TYPE_SBSX 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CCN_TYPE_SBAS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CCN_TYPE_RNI_1P 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CCN_TYPE_RNI_2P 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CCN_TYPE_RNI_3P 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CCN_TYPE_RND_2P 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CCN_TYPE_RND_3P 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CCN_TYPE_CYCLES 0xff /* Pseudotype */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CCN_NUM_PMU_EVENTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CCN_NUM_PREDEFINED_MASKS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct arm_ccn_component {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) } xp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct arm_ccn_dt, pmu), struct arm_ccn, dt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct arm_ccn_dt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) spinlock_t config_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct arm_ccn_component *source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct perf_event *event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u64 l, h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct hrtimer hrtimer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct hlist_node node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct pmu pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct arm_ccn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned sbas_present:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned sbsx_present:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct arm_ccn_component *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int num_xps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct arm_ccn_component *xp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct arm_ccn_dt dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int mn_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int arm_ccn_node_to_xp(int node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return node / CCN_NUM_XP_PORTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int arm_ccn_node_to_xp_port(int node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return node % CCN_NUM_XP_PORTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Bit shifts and masks in these defines must be kept in sync with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CCN_CONFIG_BUS(_config) (((_config) >> 24) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *config |= (node_xp << 0) | (type << 8) | (port << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static ssize_t arm_ccn_pmu_format_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct dev_ext_attribute *ea = container_of(attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct dev_ext_attribute, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CCN_FORMAT_ATTR(_name, _config) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) NULL), _config }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static CCN_FORMAT_ATTR(node, "config:0-7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static CCN_FORMAT_ATTR(xp, "config:0-7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static CCN_FORMAT_ATTR(type, "config:8-15");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static CCN_FORMAT_ATTR(event, "config:16-23");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static CCN_FORMAT_ATTR(port, "config:24-25");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static CCN_FORMAT_ATTR(bus, "config:24-25");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static CCN_FORMAT_ATTR(vc, "config:26-28");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static CCN_FORMAT_ATTR(dir, "config:29-29");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static CCN_FORMAT_ATTR(mask, "config:30-33");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct attribute *arm_ccn_pmu_format_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) &arm_ccn_pmu_format_attr_node.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) &arm_ccn_pmu_format_attr_xp.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) &arm_ccn_pmu_format_attr_type.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) &arm_ccn_pmu_format_attr_event.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) &arm_ccn_pmu_format_attr_port.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) &arm_ccn_pmu_format_attr_bus.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) &arm_ccn_pmu_format_attr_vc.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) &arm_ccn_pmu_format_attr_dir.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) &arm_ccn_pmu_format_attr_mask.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) &arm_ccn_pmu_format_attr_cmp_l.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) &arm_ccn_pmu_format_attr_cmp_h.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const struct attribute_group arm_ccn_pmu_format_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .name = "format",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .attrs = arm_ccn_pmu_format_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct arm_ccn_pmu_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct device_attribute attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int num_vcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) const char *def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CCN_EVENT_ATTR(_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * their ports in XP they are connected to. For the sake of usability they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * explicitly defined here (and translated into a relevant watchpoint in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * arm_ccn_pmu_event_init()) so the user can easily request them without deep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * knowledge of the flit format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .def = _def, .mask = _mask, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CCN_EVENT_HNI(_name, _def, _mask) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CCN_EVENT_SBSX(_name, _def, _mask) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .type = CCN_TYPE_HNF, .event = _event, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .type = CCN_TYPE_XP, .event = _event, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * on configuration. One of them is picked to represent the whole group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * as they all share the same event types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .type = CCN_TYPE_RNI_3P, .event = _event, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .type = CCN_TYPE_SBAS, .event = _event, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .type = CCN_TYPE_CYCLES }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static ssize_t arm_ccn_pmu_event_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct arm_ccn_pmu_event *event = container_of(attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct arm_ccn_pmu_event, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ssize_t res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) res = scnprintf(buf, PAGE_SIZE, "type=0x%x", event->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (event->event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) res += scnprintf(buf + res, PAGE_SIZE - res, ",event=0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) event->event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (event->def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) res += scnprintf(buf + res, PAGE_SIZE - res, ",%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) event->def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (event->mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) res += scnprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) event->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Arguments required by an event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) switch (event->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case CCN_TYPE_CYCLES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case CCN_TYPE_XP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) res += scnprintf(buf + res, PAGE_SIZE - res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ",xp=?,vc=?");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (event->event == CCN_EVENT_WATCHPOINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) res += scnprintf(buf + res, PAGE_SIZE - res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) res += scnprintf(buf + res, PAGE_SIZE - res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ",bus=?");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case CCN_TYPE_MN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) res += scnprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) res += scnprintf(buf + res, PAGE_SIZE - res, ",node=?");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) res += scnprintf(buf + res, PAGE_SIZE - res, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct attribute *attr, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct device *dev = kobj_to_dev(kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct device_attribute *dev_attr = container_of(attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct device_attribute, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct arm_ccn_pmu_event *event = container_of(dev_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct arm_ccn_pmu_event, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) CCN_IDX_MASK_ORDER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) CCN_IDX_MASK_ORDER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) CCN_EVENT_HNF(cache_miss, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) CCN_EVENT_HNF(l3_sf_cache_access, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) CCN_EVENT_HNF(cache_fill, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) CCN_EVENT_HNF(pocq_retry, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) CCN_EVENT_HNF(pocq_reqs_recvd, 0x5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) CCN_EVENT_HNF(sf_hit, 0x6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) CCN_EVENT_HNF(sf_evictions, 0x7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) CCN_EVENT_HNF(snoops_sent, 0x8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) CCN_EVENT_HNF(snoops_broadcast, 0x9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) CCN_EVENT_HNF(l3_eviction, 0xa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) CCN_EVENT_HNF(l3_fill_invalid_way, 0xb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) CCN_EVENT_HNF(mc_retries, 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) CCN_EVENT_HNF(mc_reqs, 0xd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) CCN_EVENT_HNF(qos_hh_retry, 0xe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) CCN_EVENT_RNI(rdata_beats_p0, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) CCN_EVENT_RNI(rdata_beats_p1, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) CCN_EVENT_RNI(rdata_beats_p2, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) CCN_EVENT_RNI(rxdat_flits, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) CCN_EVENT_RNI(txdat_flits, 0x5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) CCN_EVENT_RNI(txreq_flits, 0x6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) CCN_EVENT_RNI(txreq_flits_retried, 0x7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) CCN_EVENT_RNI(rrt_full, 0x8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) CCN_EVENT_RNI(wrt_full, 0x9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) CCN_EVENT_RNI(txreq_flits_replayed, 0xa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) CCN_EVENT_XP(upload_starvation, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) CCN_EVENT_XP(download_starvation, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) CCN_EVENT_XP(respin, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) CCN_EVENT_XP(valid_flit, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) CCN_EVENT_SBAS(rdata_beats_p0, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) CCN_EVENT_SBAS(rxdat_flits, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) CCN_EVENT_SBAS(txdat_flits, 0x5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) CCN_EVENT_SBAS(txreq_flits, 0x6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) CCN_EVENT_SBAS(txreq_flits_retried, 0x7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) CCN_EVENT_SBAS(rrt_full, 0x8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) CCN_EVENT_SBAS(wrt_full, 0x9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) CCN_EVENT_SBAS(txreq_flits_replayed, 0xa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) CCN_EVENT_CYCLES(cycles),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Populated in arm_ccn_init() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static struct attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const struct attribute_group arm_ccn_pmu_events_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .name = "events",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .is_visible = arm_ccn_pmu_events_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .attrs = arm_ccn_pmu_events_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) switch (name[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case 'l':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return &ccn->dt.cmp_mask[i].l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case 'h':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return &ccn->dt.cmp_mask[i].h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct device_attribute *attr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) err = kstrtoull(buf, 0, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return err ? err : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define CCN_CMP_MASK_ATTR(_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) __ATTR(_name, S_IRUGO | S_IWUSR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define CCN_CMP_MASK_ATTR_RO(_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static CCN_CMP_MASK_ATTR(0l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static CCN_CMP_MASK_ATTR(0h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static CCN_CMP_MASK_ATTR(1l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static CCN_CMP_MASK_ATTR(1h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static CCN_CMP_MASK_ATTR(2l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static CCN_CMP_MASK_ATTR(2h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static CCN_CMP_MASK_ATTR(3l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static CCN_CMP_MASK_ATTR(3h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static CCN_CMP_MASK_ATTR(4l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static CCN_CMP_MASK_ATTR(4h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static CCN_CMP_MASK_ATTR(5l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static CCN_CMP_MASK_ATTR(5h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static CCN_CMP_MASK_ATTR(6l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static CCN_CMP_MASK_ATTR(6h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static CCN_CMP_MASK_ATTR(7l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static CCN_CMP_MASK_ATTR(7h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static CCN_CMP_MASK_ATTR_RO(8l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static CCN_CMP_MASK_ATTR_RO(8h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static CCN_CMP_MASK_ATTR_RO(9l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static CCN_CMP_MASK_ATTR_RO(9h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static CCN_CMP_MASK_ATTR_RO(al);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static CCN_CMP_MASK_ATTR_RO(ah);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static CCN_CMP_MASK_ATTR_RO(bl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static CCN_CMP_MASK_ATTR_RO(bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .name = "cmp_mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .attrs = arm_ccn_pmu_cmp_mask_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return cpumap_print_to_pagebuf(true, buf, cpumask_of(ccn->dt.cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static struct device_attribute arm_ccn_pmu_cpumask_attr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static struct attribute *arm_ccn_pmu_cpumask_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) &arm_ccn_pmu_cpumask_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static const struct attribute_group arm_ccn_pmu_cpumask_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .attrs = arm_ccn_pmu_cpumask_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * Default poll period is 10ms, which is way over the top anyway,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * as in the worst case scenario (an event every cycle), with 1GHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * clocked bus, the smallest, 32 bit counter will overflow in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * more than 4s.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static unsigned int arm_ccn_pmu_poll_period_us = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static ktime_t arm_ccn_pmu_timer_period(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const struct attribute_group *arm_ccn_pmu_attr_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) &arm_ccn_pmu_events_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) &arm_ccn_pmu_format_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) &arm_ccn_pmu_cmp_mask_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) &arm_ccn_pmu_cpumask_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) bit = find_first_zero_bit(bitmap, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (bit >= size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } while (test_and_set_bit(bit, bitmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* All RN-I and RN-D nodes have identical PMUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int arm_ccn_pmu_type_eq(u32 a, u32 b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (a == b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) switch (a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case CCN_TYPE_RNI_1P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case CCN_TYPE_RNI_2P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case CCN_TYPE_RNI_3P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case CCN_TYPE_RND_1P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case CCN_TYPE_RND_2P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case CCN_TYPE_RND_3P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) switch (b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case CCN_TYPE_RNI_1P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) case CCN_TYPE_RNI_2P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) case CCN_TYPE_RNI_3P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case CCN_TYPE_RND_1P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) case CCN_TYPE_RND_2P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) case CCN_TYPE_RND_3P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int arm_ccn_pmu_event_alloc(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct hw_perf_event *hw = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 node_xp, type, event_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct arm_ccn_component *source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) node_xp = CCN_CONFIG_NODE(event->attr.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) type = CCN_CONFIG_TYPE(event->attr.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) event_id = CCN_CONFIG_EVENT(event->attr.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Allocate the cycle counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (type == CCN_TYPE_CYCLES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ccn->dt.pmu_counters_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) hw->idx = CCN_IDX_PMU_CYCLE_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Allocate an event counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) CCN_NUM_PMU_EVENT_COUNTERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (hw->idx < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dev_dbg(ccn->dev, "No more counters available!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (type == CCN_TYPE_XP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) source = &ccn->xp[node_xp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) source = &ccn->node[node_xp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ccn->dt.pmu_counters[hw->idx].source = source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Allocate an event source or a watchpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) CCN_NUM_XP_WATCHPOINTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) CCN_NUM_PMU_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (bit < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) node_xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) hw->config_base = bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ccn->dt.pmu_counters[hw->idx].event = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static void arm_ccn_pmu_event_release(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct hw_perf_event *hw = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct arm_ccn_component *source =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ccn->dt.pmu_counters[hw->idx].source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) CCN_CONFIG_EVENT(event->attr.config) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) CCN_EVENT_WATCHPOINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) clear_bit(hw->config_base, source->xp.dt_cmp_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) clear_bit(hw->config_base, source->pmu_events_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ccn->dt.pmu_counters[hw->idx].source = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ccn->dt.pmu_counters[hw->idx].event = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static int arm_ccn_pmu_event_init(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct arm_ccn *ccn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct hw_perf_event *hw = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u32 node_xp, type, event_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct perf_event *sibling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (event->attr.type != event->pmu->type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ccn = pmu_to_arm_ccn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (hw->sample_period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_dbg(ccn->dev, "Sampling not supported!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (has_branch_stack(event)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev_dbg(ccn->dev, "Can't exclude execution levels!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (event->cpu < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dev_dbg(ccn->dev, "Can't provide per-task data!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * Many perf core operations (eg. events rotation) operate on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * single CPU context. This is obvious for CPU PMUs, where one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * expects the same sets of events being observed on all CPUs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * but can lead to issues for off-core PMUs, like CCN, where each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * event could be theoretically assigned to a different CPU. To
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * mitigate this, we enforce CPU assignment to one, selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * processor (the one described in the "cpumask" attribute).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) event->cpu = ccn->dt.cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) node_xp = CCN_CONFIG_NODE(event->attr.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) type = CCN_CONFIG_TYPE(event->attr.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) event_id = CCN_CONFIG_EVENT(event->attr.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Validate node/xp vs topology */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) case CCN_TYPE_MN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (node_xp != ccn->mn_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dev_dbg(ccn->dev, "Invalid MN ID %d!\n", node_xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case CCN_TYPE_XP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (node_xp >= ccn->num_xps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) dev_dbg(ccn->dev, "Invalid XP ID %d!\n", node_xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) case CCN_TYPE_CYCLES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (node_xp >= ccn->num_nodes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dev_dbg(ccn->dev, "Invalid node ID %d!\n", node_xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_dbg(ccn->dev, "Invalid type 0x%x for node %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) type, node_xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* Validate event ID vs available for the type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u32 port = CCN_CONFIG_PORT(event->attr.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u32 vc = CCN_CONFIG_VC(event->attr.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (!arm_ccn_pmu_type_eq(type, e->type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (event_id != e->event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (e->num_ports && port >= e->num_ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dev_dbg(ccn->dev, "Invalid port %d for node/XP %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) port, node_xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (e->num_vcs && vc >= e->num_vcs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_dbg(ccn->dev, "Invalid vc %d for node/XP %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) vc, node_xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (!valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_dbg(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) event_id, node_xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* Watchpoint-based event for a node is actually set on XP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u32 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) type = CCN_TYPE_XP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) port = arm_ccn_node_to_xp_port(node_xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) node_xp = arm_ccn_node_to_xp(node_xp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) arm_ccn_pmu_config_set(&event->attr.config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) node_xp, type, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * We must NOT create groups containing mixed PMUs, although software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * events are acceptable (for example to create a CCN group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * periodically read when a hrtimer aka cpu-clock leader triggers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (event->group_leader->pmu != event->pmu &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) !is_software_event(event->group_leader))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) for_each_sibling_event(sibling, event->group_leader) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (sibling->pmu != event->pmu &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) !is_software_event(sibling))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u64 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (idx == CCN_IDX_PMU_CYCLE_COUNTER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #ifdef readq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* 40 bit counter, can do snapshot and read in two parts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) res <<= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static void arm_ccn_pmu_event_update(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct hw_perf_event *hw = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u64 prev_count, new_count, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) prev_count = local64_read(&hw->prev_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) new_count = arm_ccn_pmu_read_counter(ccn, hw->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) } while (local64_xchg(&hw->prev_count, new_count) != prev_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) local64_add((new_count - prev_count) & mask, &event->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct hw_perf_event *hw = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct arm_ccn_component *xp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) u32 val, dt_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* Nothing to do for cycle counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) xp = &ccn->xp[arm_ccn_node_to_xp(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) CCN_CONFIG_NODE(event->attr.config))];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dt_cfg = hw->event_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) spin_lock(&ccn->dt.config_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) val = readl(xp->base + CCN_XP_DT_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) writel(val, xp->base + CCN_XP_DT_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) spin_unlock(&ccn->dt.config_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct hw_perf_event *hw = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) local64_set(&event->hw.prev_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) arm_ccn_pmu_read_counter(ccn, hw->idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) hw->state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* Set the DT bus input, engaging the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) arm_ccn_pmu_xp_dt_config(event, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct hw_perf_event *hw = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* Disable counting, setting the DT bus to pass-through mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) arm_ccn_pmu_xp_dt_config(event, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (flags & PERF_EF_UPDATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) arm_ccn_pmu_event_update(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) hw->state |= PERF_HES_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct hw_perf_event *hw = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct arm_ccn_component *source =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ccn->dt.pmu_counters[hw->idx].source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) unsigned long wp = hw->config_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) u64 cmp_l = event->attr.config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) u64 cmp_h = event->attr.config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* Direction (RX/TX), device (port) & virtual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) val |= CCN_CONFIG_DIR(event->attr.config) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) val |= CCN_CONFIG_PORT(event->attr.config) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) val |= CCN_CONFIG_VC(event->attr.config) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* Comparison values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) writel((cmp_l >> 32) & 0x7fffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) writel((cmp_h >> 32) & 0x0fffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) writel((mask_l >> 32) & 0x7fffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) writel((mask_h >> 32) & 0x0fffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct hw_perf_event *hw = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct arm_ccn_component *source =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ccn->dt.pmu_counters[hw->idx].source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u32 val, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) id = (CCN_CONFIG_VC(event->attr.config) << 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) (CCN_CONFIG_BUS(event->attr.config) << 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) (CCN_CONFIG_EVENT(event->attr.config) << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static void arm_ccn_pmu_node_event_config(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct hw_perf_event *hw = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct arm_ccn_component *source =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ccn->dt.pmu_counters[hw->idx].source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) u32 type = CCN_CONFIG_TYPE(event->attr.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) u32 val, port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) hw->config_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* These *_event_sel regs should be identical, but let's make sure... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) CCN_SBAS_PMU_EVENT_SEL__ID__MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) CCN_RNI_PMU_EVENT_SEL__ID__MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* Set the event id for the pre-allocated counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) val |= CCN_CONFIG_EVENT(event->attr.config) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static void arm_ccn_pmu_event_config(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct hw_perf_event *hw = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) u32 xp, offset, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* Cycle counter requires no setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) xp = CCN_CONFIG_XP(event->attr.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) spin_lock(&ccn->dt.config_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* Set the DT bus "distance" register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) offset = (hw->idx / 4) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (CCN_CONFIG_EVENT(event->attr.config) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) CCN_EVENT_WATCHPOINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) arm_ccn_pmu_xp_watchpoint_config(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) arm_ccn_pmu_xp_event_config(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) arm_ccn_pmu_node_event_config(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) spin_unlock(&ccn->dt.config_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return bitmap_weight(ccn->dt.pmu_counters_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) CCN_NUM_PMU_EVENT_COUNTERS + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct hw_perf_event *hw = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) err = arm_ccn_pmu_event_alloc(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * Pin the timer, so that the overflows are handled by the chosen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * event->cpu (this is the same one as presented in "cpumask"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * attribute).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) HRTIMER_MODE_REL_PINNED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) arm_ccn_pmu_event_config(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) hw->state = PERF_HES_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (flags & PERF_EF_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) arm_ccn_pmu_event_start(event, PERF_EF_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) arm_ccn_pmu_event_release(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) hrtimer_cancel(&ccn->dt.hrtimer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static void arm_ccn_pmu_event_read(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) arm_ccn_pmu_event_update(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static void arm_ccn_pmu_enable(struct pmu *pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) val |= CCN_DT_PMCR__PMU_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) writel(val, ccn->dt.base + CCN_DT_PMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static void arm_ccn_pmu_disable(struct pmu *pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) val &= ~CCN_DT_PMCR__PMU_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) writel(val, ccn->dt.base + CCN_DT_PMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (!pmovsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct perf_event *event = dt->pmu_counters[idx].event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) int overflowed = pmovsr & BIT(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) WARN_ON_ONCE(overflowed && !event &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) idx != CCN_IDX_PMU_CYCLE_COUNTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (!event || !overflowed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) arm_ccn_pmu_event_update(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) hrtimer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) arm_ccn_pmu_overflow_handler(dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return HRTIMER_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static int arm_ccn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) unsigned int target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (cpu != dt->cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) target = cpumask_any_but(cpu_online_mask, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (target >= nr_cpu_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) perf_pmu_migrate_context(&dt->pmu, cpu, target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dt->cpu = target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (ccn->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) WARN_ON(irq_set_affinity_hint(ccn->irq, cpumask_of(dt->cpu)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static DEFINE_IDA(arm_ccn_pmu_ida);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static int arm_ccn_pmu_init(struct arm_ccn *ccn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* Initialize DT subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) ccn->dt.base = ccn->base + CCN_REGION_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) spin_lock_init(&ccn->dt.config_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) ccn->dt.base + CCN_DT_PMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) for (i = 0; i < ccn->num_xps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) CCN_XP_DT_CONTROL__DT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ccn->xp[i].base + CCN_XP_DT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* Get a convenient /sys/event_source/devices/ name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (ccn->dt.id == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) name = "ccn";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) name = devm_kasprintf(ccn->dev, GFP_KERNEL, "ccn_%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ccn->dt.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (!name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) goto error_choose_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* Perf driver registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) ccn->dt.pmu = (struct pmu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .attr_groups = arm_ccn_pmu_attr_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .task_ctx_nr = perf_invalid_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .event_init = arm_ccn_pmu_event_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .add = arm_ccn_pmu_event_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .del = arm_ccn_pmu_event_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .start = arm_ccn_pmu_event_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .stop = arm_ccn_pmu_event_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .read = arm_ccn_pmu_event_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .pmu_enable = arm_ccn_pmu_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .pmu_disable = arm_ccn_pmu_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) /* No overflow interrupt? Have to use a timer instead. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (!ccn->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) dev_info(ccn->dev, "No access to interrupts, using timer.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /* Pick one CPU which we will use to collect data from CCN... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) ccn->dt.cpu = raw_smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* Also make sure that the overflow interrupt is handled by this CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (ccn->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) err = irq_set_affinity_hint(ccn->irq, cpumask_of(ccn->dt.cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) dev_err(ccn->dev, "Failed to set interrupt affinity!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) goto error_set_affinity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) &ccn->dt.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) err = perf_pmu_register(&ccn->dt.pmu, name, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) goto error_pmu_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) error_pmu_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) &ccn->dt.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) error_set_affinity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) error_choose_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) for (i = 0; i < ccn->num_xps; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) writel(0, ccn->dt.base + CCN_DT_PMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) &ccn->dt.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (ccn->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) irq_set_affinity_hint(ccn->irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) for (i = 0; i < ccn->num_xps; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) writel(0, ccn->dt.base + CCN_DT_PMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) perf_pmu_unregister(&ccn->dt.pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) int (*callback)(struct arm_ccn *ccn, int region,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) void __iomem *base, u32 type, u32 id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) int region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) for (region = 0; region < CCN_NUM_REGIONS; region++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) u32 val, type, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) 4 * (region / 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (!(val & (1 << (region % 32))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) base = ccn->base + region * CCN_REGION_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) val = readl(base + CCN_ALL_OLY_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) CCN_ALL_OLY_ID__OLY_ID__MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) CCN_ALL_OLY_ID__NODE_ID__MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) err = callback(ccn, region, base, type, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) void __iomem *base, u32 type, u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (type == CCN_TYPE_XP && id >= ccn->num_xps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ccn->num_xps = id + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) else if (id >= ccn->num_nodes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ccn->num_nodes = id + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) void __iomem *base, u32 type, u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct arm_ccn_component *component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) case CCN_TYPE_MN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ccn->mn_id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) case CCN_TYPE_DT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) case CCN_TYPE_XP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) component = &ccn->xp[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) case CCN_TYPE_SBSX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ccn->sbsx_present = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) component = &ccn->node[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) case CCN_TYPE_SBAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ccn->sbas_present = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) component = &ccn->node[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) component->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) component->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) const u32 *err_sig_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* This should be really handled by firmware... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) err_sig_val[5], err_sig_val[4], err_sig_val[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) err_sig_val[2], err_sig_val[1], err_sig_val[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) ccn->base + CCN_MN_ERRINT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) irqreturn_t res = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct arm_ccn *ccn = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) u32 err_sig_val[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) u32 err_or;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /* PMU overflow is a special case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) res = arm_ccn_pmu_overflow_handler(&ccn->dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* Have to read all err_sig_vals to clear them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) err_sig_val[i] = readl(ccn->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) CCN_MN_ERR_SIG_VAL_63_0 + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) err_or |= err_sig_val[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (err_or)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) res |= arm_ccn_error_handler(ccn, err_sig_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (res != IRQ_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) ccn->base + CCN_MN_ERRINT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static int arm_ccn_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) struct arm_ccn *ccn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (!ccn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ccn->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) platform_set_drvdata(pdev, ccn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) ccn->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (IS_ERR(ccn->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return PTR_ERR(ccn->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) irq = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /* Check if we can use the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ccn->base + CCN_MN_ERRINT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /* Can set 'disable' bits, so can acknowledge interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) ccn->base + CCN_MN_ERRINT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) IRQF_NOBALANCING | IRQF_NO_THREAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) dev_name(ccn->dev), ccn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) ccn->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) /* Build topology */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) ccn->node = devm_kcalloc(ccn->dev, ccn->num_nodes, sizeof(*ccn->node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) ccn->xp = devm_kcalloc(ccn->dev, ccn->num_xps, sizeof(*ccn->node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (!ccn->node || !ccn->xp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) return arm_ccn_pmu_init(ccn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) static int arm_ccn_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) struct arm_ccn *ccn = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) arm_ccn_pmu_cleanup(ccn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static const struct of_device_id arm_ccn_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) { .compatible = "arm,ccn-502", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) { .compatible = "arm,ccn-504", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) { .compatible = "arm,ccn-512", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) MODULE_DEVICE_TABLE(of, arm_ccn_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static struct platform_driver arm_ccn_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .name = "arm-ccn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .of_match_table = arm_ccn_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .probe = arm_ccn_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .remove = arm_ccn_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static int __init arm_ccn_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CCN_ONLINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) "perf/arm/ccn:online", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) arm_ccn_pmu_offline_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) ret = platform_driver_register(&arm_ccn_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) static void __exit arm_ccn_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) platform_driver_unregister(&arm_ccn_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) module_init(arm_ccn_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) module_exit(arm_ccn_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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