^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) # Performance Monitor Drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) menu "Performance monitor support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) depends on PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) config ARM_CCI_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) tristate "ARM CCI PMU driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) depends on (ARM && CPU_V7) || ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) select ARM_CCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Support for PMU events monitoring on the ARM CCI (Cache Coherent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Interconnect) family of products.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) If compiled as a module, it will be called arm-cci.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) config ARM_CCI400_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) bool "support CCI-400"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) depends on ARM_CCI_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) select ARM_CCI400_COMMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) CCI-400 provides 4 independent event counters counting events related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) to the connected slave/master interfaces, plus a cycle counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) config ARM_CCI5xx_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) bool "support CCI-500/CCI-550"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) depends on ARM_CCI_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) CCI-500/CCI-550 both provide 8 independent event counters, which can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) count events pertaining to the slave/master interfaces as well as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) internal events to the CCI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) config ARM_CCN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) tristate "ARM CCN driver support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) depends on ARM || ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) interconnect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) config ARM_CMN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) tristate "Arm CMN-600 PMU support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) depends on ARM64 || (COMPILE_TEST && 64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Network interconnect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) config ARM_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) depends on ARM || ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) bool "ARM PMU framework"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Say y if you want to use CPU performance monitors on ARM-based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) config ARM_PMU_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) depends on ARM_PMU && ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) config ARM_SMMU_V3_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) tristate "ARM SMMUv3 Performance Monitors Extension"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) depends on ARM64 && ACPI && ARM_SMMU_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Provides support for the ARM SMMUv3 Performance Monitor Counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Groups (PMCG), which provide monitoring of transactions passing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) through the SMMU and allow the resulting information to be filtered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) based on the Stream ID of the corresponding master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) config ARM_DSU_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) tristate "ARM DynamIQ Shared Unit (DSU) PMU"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) depends on ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) Provides support for performance monitor unit in ARM DynamIQ Shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) Unit (DSU). The DSU integrates one or more cores with an L3 memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) system, control logic. The PMU allows counting various events related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) to DSU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) config FSL_IMX8_DDR_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) tristate "Freescale i.MX8 DDR perf monitor"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) depends on ARCH_MXC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) Provides support for the DDR performance monitor in i.MX8, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) can give information about memory throughput and other related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) config QCOM_L2_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bool "Qualcomm Technologies L2-cache PMU"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) depends on ARCH_QCOM && ARM64 && ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) select QCOM_KRYO_L2_ACCESSORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) Provides support for the L2 cache performance monitor unit (PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) in Qualcomm Technologies processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) Adds the L2 cache PMU into the perf events subsystem for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) monitoring L2 cache events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) config QCOM_L3_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bool "Qualcomm Technologies L3-cache PMU"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) depends on ARCH_QCOM && ARM64 && ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) select QCOM_IRQ_COMBINER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Provides support for the L3 cache performance monitor unit (PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) in Qualcomm Technologies processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) Adds the L3 cache PMU into the perf events subsystem for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) monitoring L3 cache events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) config THUNDERX2_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) tristate "Cavium ThunderX2 SoC PMU UNCORE"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) default m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) Provides support for ThunderX2 UNCORE events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) The SoC has PMU support in its L3 cache controller (L3C) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) in the DDR4 Memory Controller (DMC).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) config XGENE_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) depends on ARCH_XGENE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bool "APM X-Gene SoC PMU"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) Say y if you want to use APM X-Gene SoC performance monitors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) config ARM_SPE_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) depends on ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) Enable perf support for the ARMv8.2 Statistical Profiling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) Extension, which provides periodic sampling of operations in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) the CPU pipeline and reports this via the perf AUX interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) source "drivers/perf/hisilicon/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) endmenu
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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