^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __YENTA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __YENTA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define CB_SOCKET_EVENT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define CB_CSTSEVENT 0x00000001 /* Card status event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CB_CD1EVENT 0x00000002 /* Card detect 1 change event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CB_CD2EVENT 0x00000004 /* Card detect 2 change event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CB_PWREVENT 0x00000008 /* PWRCYCLE change event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CB_SOCKET_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CB_CSTSMASK 0x00000001 /* Card status mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CB_CDMASK 0x00000006 /* Card detect 1&2 mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CB_PWRMASK 0x00000008 /* PWRCYCLE change mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CB_SOCKET_STATE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CB_CARDSTS 0x00000001 /* CSTSCHG status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CB_CDETECT1 0x00000002 /* Card detect status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CB_CDETECT2 0x00000004 /* Card detect status 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CB_PWRCYCLE 0x00000008 /* Socket powered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CB_16BITCARD 0x00000010 /* 16-bit card detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CB_CBCARD 0x00000020 /* CardBus card detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CB_IREQCINT 0x00000040 /* READY(xIRQ)/xCINT high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CB_NOTACARD 0x00000080 /* Unrecognizable PC card detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CB_DATALOST 0x00000100 /* Potential data loss due to card removal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CB_BADVCCREQ 0x00000200 /* Invalid Vcc request by host software */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CB_5VCARD 0x00000400 /* Card Vcc at 5.0 volts? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CB_3VCARD 0x00000800 /* Card Vcc at 3.3 volts? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CB_XVCARD 0x00001000 /* Card Vcc at X.X volts? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CB_YVCARD 0x00002000 /* Card Vcc at Y.Y volts? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CB_5VSOCKET 0x10000000 /* Socket Vcc at 5.0 volts? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CB_3VSOCKET 0x20000000 /* Socket Vcc at 3.3 volts? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CB_XVSOCKET 0x40000000 /* Socket Vcc at X.X volts? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CB_YVSOCKET 0x80000000 /* Socket Vcc at Y.Y volts? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CB_SOCKET_FORCE 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CB_FCARDSTS 0x00000001 /* Force CSTSCHG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CB_FCDETECT1 0x00000002 /* Force CD1EVENT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CB_FCDETECT2 0x00000004 /* Force CD2EVENT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CB_FPWRCYCLE 0x00000008 /* Force PWREVENT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CB_F16BITCARD 0x00000010 /* Force 16-bit PCMCIA card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CB_FCBCARD 0x00000020 /* Force CardBus line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CB_FNOTACARD 0x00000080 /* Force NOTACARD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CB_FDATALOST 0x00000100 /* Force data lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CB_FBADVCCREQ 0x00000200 /* Force bad Vcc request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CB_F5VCARD 0x00000400 /* Force 5.0 volt card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CB_F3VCARD 0x00000800 /* Force 3.3 volt card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CB_FXVCARD 0x00001000 /* Force X.X volt card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CB_FYVCARD 0x00002000 /* Force Y.Y volt card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CB_CVSTEST 0x00004000 /* Card VS test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CB_SOCKET_CONTROL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CB_SC_VPP_MASK 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CB_SC_VPP_OFF 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CB_SC_VPP_12V 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CB_SC_VPP_5V 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CB_SC_VPP_3V 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CB_SC_VPP_XV 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CB_SC_VPP_YV 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CB_SC_VCC_MASK 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CB_SC_VCC_OFF 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CB_SC_VCC_5V 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CB_SC_VCC_3V 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CB_SC_VCC_XV 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CB_SC_VCC_YV 0x00000050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CB_SC_CCLK_STOP 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CB_SOCKET_POWER 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CB_SKTACCES 0x02000000 /* A PC card access has occurred (clear on read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CB_SKTMODE 0x01000000 /* Clock frequency has changed (clear on read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CB_CLKCTRLEN 0x00010000 /* Clock control enabled (RW) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CB_CLKCTRL 0x00000001 /* Stop(0) or slow(1) CB clock (RW) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Cardbus configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CB_BRIDGE_BASE(m) (0x1c + 8*(m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CB_BRIDGE_LIMIT(m) (0x20 + 8*(m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CB_BRIDGE_CONTROL 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CB_BRIDGE_CPERREN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CB_BRIDGE_CSERREN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CB_BRIDGE_ISAEN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CB_BRIDGE_VGAEN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CB_BRIDGE_MABTMODE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CB_BRIDGE_CRST 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CB_BRIDGE_INTR 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CB_BRIDGE_PREFETCH0 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CB_BRIDGE_PREFETCH1 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CB_BRIDGE_POSTEN 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CB_LEGACY_MODE_BASE 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * ExCA area extensions in Yenta
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CB_MEM_PAGE(map) (0x40 + (map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* control how 16bit cards are powered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define YENTA_16BIT_POWER_EXCA 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define YENTA_16BIT_POWER_DF 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct yenta_socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct cardbus_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int (*override)(struct yenta_socket *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void (*save_state)(struct yenta_socket *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void (*restore_state)(struct yenta_socket *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int (*sock_init)(struct yenta_socket *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct yenta_socket {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int cb_irq, io_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct timer_list poll_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct pcmcia_socket socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct cardbus_type *type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* for PCI interrupt probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int probe_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* A few words of private data for special stuff of overrides... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int private[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* PCI saved state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 saved_state[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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