^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Regular cardbus driver ("yenta_socket")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) Copyright 1999, 2000 Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Changelog:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Aug 2002: Manfred Spraul <manfred@colorfullife.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Dynamically adjust the size of the bridge resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * May 2003: Dominik Brodowski <linux@brodo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Merge pci_socket.c and yenta.c into one file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <pcmcia/ss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "yenta_socket.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "i82365.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static bool disable_clkrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) module_param(disable_clkrun, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_PARM_DESC(disable_clkrun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "If PC card doesn't function properly, please try this option (TI and Ricoh bridges only)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static bool isa_probe = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) module_param(isa_probe, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_PARM_DESC(isa_probe, "If set ISA interrupts are probed (default). Set to N to disable probing");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static bool pwr_irqs_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) module_param(pwr_irqs_off, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MODULE_PARM_DESC(pwr_irqs_off, "Force IRQs off during power-on of slot. Use only when seeing IRQ storms!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static char o2_speedup[] = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) module_param_string(o2_speedup, o2_speedup, sizeof(o2_speedup), 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_PARM_DESC(o2_speedup, "Use prefetch/burst for O2-bridges: 'on', 'off' "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "or 'default' (uses recommended behaviour for the detected bridge)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Only probe "regular" interrupts, don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * touch dangerous spots like the mouse irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * because there are mice that apparently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * get really confused if they get fondled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * too intimately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Default to 11, 10, 9, 7, 6, 5, 4, 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static u32 isa_interrupts = 0x0ef8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define debug(x, s, args...) dev_dbg(&s->dev->dev, x, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Don't ask.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define to_cycles(ns) ((ns)/120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define to_ns(cycles) ((cycles)*120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * yenta PCI irq probing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * currently only used in the TI/EnE initialization code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #ifdef CONFIG_YENTA_TI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int yenta_probe_cb_irq(struct yenta_socket *socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static unsigned int yenta_probe_irq(struct yenta_socket *socket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 isa_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static unsigned int override_bios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) module_param(override_bios, uint, 0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MODULE_PARM_DESC(override_bios, "yenta ignore bios resource allocation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Generate easy-to-use ways of reading a cardbus sockets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * regular memory space ("cb_xxx"), configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * ("config_xxx") and compatibility space ("exca_xxxx")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static inline u32 cb_readl(struct yenta_socket *socket, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 val = readl(socket->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) debug("%04x %08x\n", socket, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline void cb_writel(struct yenta_socket *socket, unsigned reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) debug("%04x %08x\n", socket, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel(val, socket->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) readl(socket->base + reg); /* avoid problems with PCI write posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline u8 config_readb(struct yenta_socket *socket, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pci_read_config_byte(socket->dev, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) debug("%04x %02x\n", socket, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline u16 config_readw(struct yenta_socket *socket, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pci_read_config_word(socket->dev, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) debug("%04x %04x\n", socket, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline u32 config_readl(struct yenta_socket *socket, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pci_read_config_dword(socket->dev, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) debug("%04x %08x\n", socket, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline void config_writeb(struct yenta_socket *socket, unsigned offset, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) debug("%04x %02x\n", socket, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) pci_write_config_byte(socket->dev, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline void config_writew(struct yenta_socket *socket, unsigned offset, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) debug("%04x %04x\n", socket, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pci_write_config_word(socket->dev, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline void config_writel(struct yenta_socket *socket, unsigned offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) debug("%04x %08x\n", socket, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pci_write_config_dword(socket->dev, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline u8 exca_readb(struct yenta_socket *socket, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 val = readb(socket->base + 0x800 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) debug("%04x %02x\n", socket, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static inline u8 exca_readw(struct yenta_socket *socket, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) val = readb(socket->base + 0x800 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) val |= readb(socket->base + 0x800 + reg + 1) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) debug("%04x %04x\n", socket, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static inline void exca_writeb(struct yenta_socket *socket, unsigned reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) debug("%04x %02x\n", socket, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) writeb(val, socket->base + 0x800 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) readb(socket->base + 0x800 + reg); /* PCI write posting... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void exca_writew(struct yenta_socket *socket, unsigned reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) debug("%04x %04x\n", socket, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) writeb(val, socket->base + 0x800 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) writeb(val >> 8, socket->base + 0x800 + reg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* PCI write posting... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) readb(socket->base + 0x800 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) readb(socket->base + 0x800 + reg + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static ssize_t show_yenta_registers(struct device *yentadev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct yenta_socket *socket = dev_get_drvdata(yentadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int offset = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) offset = snprintf(buf, PAGE_SIZE, "CB registers:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) for (i = 0; i < 0x24; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!(i & 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) offset += scnprintf(buf + offset, PAGE_SIZE - offset, "\n%02x:", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val = cb_readl(socket, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) offset += scnprintf(buf + offset, PAGE_SIZE - offset, " %08x", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) offset += scnprintf(buf + offset, PAGE_SIZE - offset, "\n\nExCA registers:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) for (i = 0; i < 0x45; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!(i & 7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (i & 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) memcpy(buf + offset, " -", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) offset += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) offset += scnprintf(buf + offset, PAGE_SIZE - offset, "\n%02x:", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) val = exca_readb(socket, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) offset += scnprintf(buf + offset, PAGE_SIZE - offset, " %02x", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) buf[offset++] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static DEVICE_ATTR(yenta_registers, S_IRUSR, show_yenta_registers, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Ugh, mixed-mode cardbus and 16-bit pccard state: things depend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * on what kind of card is inserted..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int yenta_get_status(struct pcmcia_socket *sock, unsigned int *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 state = cb_readl(socket, CB_SOCKET_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) val = (state & CB_3VCARD) ? SS_3VCARD : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) val |= (state & CB_XVCARD) ? SS_XVCARD : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) val |= (state & (CB_5VCARD | CB_3VCARD | CB_XVCARD | CB_YVCARD)) ? 0 : SS_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) val |= (state & (CB_CDETECT1 | CB_CDETECT2)) ? SS_PENDING : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (state & CB_CBCARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) val |= SS_CARDBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) val |= (state & CB_CARDSTS) ? SS_STSCHG : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) val |= (state & (CB_CDETECT1 | CB_CDETECT2)) ? 0 : SS_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) val |= (state & CB_PWRCYCLE) ? SS_POWERON | SS_READY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) } else if (state & CB_16BITCARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 status = exca_readb(socket, I365_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) val |= ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (exca_readb(socket, I365_INTCTL) & I365_PC_IOCARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) val |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) val |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val |= (status & I365_CS_READY) ? SS_READY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) val |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *value = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void yenta_set_power(struct yenta_socket *socket, socket_state_t *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* some birdges require to use the ExCA registers to power 16bit cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!(cb_readl(socket, CB_SOCKET_STATE) & CB_CBCARD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) (socket->flags & YENTA_16BIT_POWER_EXCA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 reg, old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) reg = old = exca_readb(socket, I365_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) reg &= ~(I365_VCC_MASK | I365_VPP1_MASK | I365_VPP2_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* i82365SL-DF style */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (socket->flags & YENTA_16BIT_POWER_DF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) switch (state->Vcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case 33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) reg |= I365_VCC_3V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) reg |= I365_VCC_5V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) switch (state->Vpp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case 33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) reg |= I365_VPP1_5V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case 120:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) reg |= I365_VPP1_12V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* i82365SL-B style */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) switch (state->Vcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) reg |= I365_VCC_5V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) switch (state->Vpp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) reg |= I365_VPP1_5V | I365_VPP2_5V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case 120:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) reg |= I365_VPP1_12V | I365_VPP2_12V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (reg != old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) exca_writeb(socket, I365_POWER, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 reg = 0; /* CB_SC_STPCLK? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) switch (state->Vcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case 33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) reg = CB_SC_VCC_3V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) reg = CB_SC_VCC_5V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) switch (state->Vpp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case 33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) reg |= CB_SC_VPP_3V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) reg |= CB_SC_VPP_5V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case 120:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) reg |= CB_SC_VPP_12V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (reg != cb_readl(socket, CB_SOCKET_CONTROL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) cb_writel(socket, CB_SOCKET_CONTROL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int yenta_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u16 bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* if powering down: do it immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (state->Vcc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) yenta_set_power(socket, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) socket->io_irq = state->io_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) bridge = config_readw(socket, CB_BRIDGE_CONTROL) & ~(CB_BRIDGE_CRST | CB_BRIDGE_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (cb_readl(socket, CB_SOCKET_STATE) & CB_CBCARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bridge |= (state->flags & SS_RESET) ? CB_BRIDGE_CRST : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* ISA interrupt control? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) intr = exca_readb(socket, I365_INTCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) intr = (intr & ~0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!socket->dev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) intr |= socket->cb_irq ? socket->cb_irq : state->io_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) bridge |= CB_BRIDGE_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) exca_writeb(socket, I365_INTCTL, intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) reg = exca_readb(socket, I365_INTCTL) & (I365_RING_ENA | I365_INTR_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (state->io_irq != socket->dev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) reg |= state->io_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) bridge |= CB_BRIDGE_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) exca_writeb(socket, I365_INTCTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) reg = exca_readb(socket, I365_POWER) & (I365_VCC_MASK|I365_VPP1_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) reg |= I365_PWR_NORESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (state->flags & SS_PWR_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) reg |= I365_PWR_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (state->flags & SS_OUTPUT_ENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) reg |= I365_PWR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (exca_readb(socket, I365_POWER) != reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) exca_writeb(socket, I365_POWER, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* CSC interrupt: no ISA irq for CSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) reg = exca_readb(socket, I365_CSCINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) reg &= I365_CSC_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) reg |= I365_CSC_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (state->flags & SS_IOCARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (state->csc_mask & SS_STSCHG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) reg |= I365_CSC_STSCHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (state->csc_mask & SS_BATDEAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) reg |= I365_CSC_BVD1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (state->csc_mask & SS_BATWARN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) reg |= I365_CSC_BVD2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (state->csc_mask & SS_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) reg |= I365_CSC_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) exca_writeb(socket, I365_CSCINT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) exca_readb(socket, I365_CSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (sock->zoom_video)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) sock->zoom_video(sock, state->flags & SS_ZVCARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) config_writew(socket, CB_BRIDGE_CONTROL, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Socket event mask: get card insert/remove events.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) cb_writel(socket, CB_SOCKET_EVENT, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) cb_writel(socket, CB_SOCKET_MASK, CB_CDMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* if powering up: do it as the last step when the socket is configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (state->Vcc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) yenta_set_power(socket, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int yenta_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned char ioctl, addr, enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) map = io->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (map > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) enable = I365_ENA_IO(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) addr = exca_readb(socket, I365_ADDRWIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Disable the window before changing it.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (addr & enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) addr &= ~enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) exca_writeb(socket, I365_ADDRWIN, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) exca_writew(socket, I365_IO(map)+I365_W_START, io->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) exca_writew(socket, I365_IO(map)+I365_W_STOP, io->stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ioctl = exca_readb(socket, I365_IOCTL) & ~I365_IOCTL_MASK(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (io->flags & MAP_0WS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ioctl |= I365_IOCTL_0WS(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (io->flags & MAP_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ioctl |= I365_IOCTL_16BIT(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (io->flags & MAP_AUTOSZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ioctl |= I365_IOCTL_IOCS16(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) exca_writeb(socket, I365_IOCTL, ioctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (io->flags & MAP_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) exca_writeb(socket, I365_ADDRWIN, addr | enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int yenta_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned char addr, enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int start, stop, card_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned short word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pcibios_resource_to_bus(socket->dev->bus, ®ion, mem->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) map = mem->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) start = region.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) stop = region.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) card_start = mem->card_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (map > 4 || start > stop || ((start ^ stop) >> 24) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) (card_start >> 26) || mem->speed > 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) enable = I365_ENA_MEM(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) addr = exca_readb(socket, I365_ADDRWIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (addr & enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) addr &= ~enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) exca_writeb(socket, I365_ADDRWIN, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) exca_writeb(socket, CB_MEM_PAGE(map), start >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) word = (start >> 12) & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (mem->flags & MAP_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) word |= I365_MEM_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (mem->flags & MAP_0WS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) word |= I365_MEM_0WS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) exca_writew(socket, I365_MEM(map) + I365_W_START, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) word = (stop >> 12) & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) switch (to_cycles(mem->speed)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) word |= I365_MEM_WS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) word |= I365_MEM_WS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) word |= I365_MEM_WS1 | I365_MEM_WS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) exca_writew(socket, I365_MEM(map) + I365_W_STOP, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) word = ((card_start - start) >> 12) & 0x3fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (mem->flags & MAP_WRPROT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) word |= I365_MEM_WRPROT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (mem->flags & MAP_ATTRIB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) word |= I365_MEM_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) exca_writew(socket, I365_MEM(map) + I365_W_OFF, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (mem->flags & MAP_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) exca_writeb(socket, I365_ADDRWIN, addr | enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static irqreturn_t yenta_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned int events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct yenta_socket *socket = (struct yenta_socket *) dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u8 csc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u32 cb_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Clear interrupt status for the event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) cb_event = cb_readl(socket, CB_SOCKET_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) cb_writel(socket, CB_SOCKET_EVENT, cb_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) csc = exca_readb(socket, I365_CSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!(cb_event || csc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) events = (cb_event & (CB_CD1EVENT | CB_CD2EVENT)) ? SS_DETECT : 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) events |= (csc & I365_CSC_DETECT) ? SS_DETECT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (exca_readb(socket, I365_INTCTL) & I365_PC_IOCARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) events |= (csc & I365_CSC_READY) ? SS_READY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pcmcia_parse_events(&socket->socket, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static void yenta_interrupt_wrapper(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct yenta_socket *socket = from_timer(socket, t, poll_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) yenta_interrupt(0, (void *)socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) socket->poll_timer.expires = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) add_timer(&socket->poll_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void yenta_clear_maps(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct resource res = { .start = 0, .end = 0x0fff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pccard_io_map io = { 0, 0, 0, 0, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pccard_mem_map mem = { .res = &res, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) yenta_set_socket(&socket->socket, &dead_socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) io.map = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) yenta_set_io_map(&socket->socket, &io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mem.map = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) yenta_set_mem_map(&socket->socket, &mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* redoes voltage interrogation if required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static void yenta_interrogate(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) state = cb_readl(socket, CB_SOCKET_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (!(state & (CB_5VCARD | CB_3VCARD | CB_XVCARD | CB_YVCARD)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) (state & (CB_CDETECT1 | CB_CDETECT2 | CB_NOTACARD | CB_BADVCCREQ)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ((state & (CB_16BITCARD | CB_CBCARD)) == (CB_16BITCARD | CB_CBCARD)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) cb_writel(socket, CB_SOCKET_FORCE, CB_CVSTEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Called at resume and initialization events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int yenta_sock_init(struct pcmcia_socket *sock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) exca_writeb(socket, I365_GBLCTL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) exca_writeb(socket, I365_GENCTL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Redo card voltage interrogation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) yenta_interrogate(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) yenta_clear_maps(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (socket->type && socket->type->sock_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) socket->type->sock_init(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Re-enable CSC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) cb_writel(socket, CB_SOCKET_MASK, CB_CDMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int yenta_sock_suspend(struct pcmcia_socket *sock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Disable CSC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) cb_writel(socket, CB_SOCKET_MASK, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * Use an adaptive allocation for the memory resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * sometimes the memory behind pci bridges is limited:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * 1/8 of the size of the io window of the parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * max 4 MB, min 16 kB. We try very hard to not get below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * the "ACC" values, though.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define BRIDGE_MEM_MAX (4*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define BRIDGE_MEM_ACC (128*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define BRIDGE_MEM_MIN (16*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define BRIDGE_IO_MAX 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define BRIDGE_IO_ACC 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define BRIDGE_IO_MIN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #ifndef PCIBIOS_MIN_CARDBUS_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define PCIBIOS_MIN_CARDBUS_IO PCIBIOS_MIN_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static int yenta_search_one_res(struct resource *root, struct resource *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u32 min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 align, size, start, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (res->flags & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) align = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) size = BRIDGE_IO_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) start = PCIBIOS_MIN_CARDBUS_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) end = ~0U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned long avail = root->end - root->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) size = BRIDGE_MEM_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (size > avail/8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) size = (avail+1)/8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* round size down to next power of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) while ((size /= 2) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) size = 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (size < min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) size = min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) align = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) start = PCIBIOS_MIN_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) end = ~0U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (allocate_resource(root, res, size, start, end, align,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) NULL, NULL) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) size = size/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) align = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) } while (size >= min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int yenta_search_res(struct yenta_socket *socket, struct resource *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u32 min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct resource *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pci_bus_for_each_resource(socket->dev->bus, root, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (!root)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if ((res->flags ^ root->flags) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) continue; /* Wrong type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (yenta_search_one_res(root, res, min))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static int yenta_allocate_res(struct yenta_socket *socket, int nr, unsigned type, int addr_start, int addr_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct pci_dev *dev = socket->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) res = &dev->resource[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Already allocated? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* The granularity of the memory limit is 4kB, on IO it's 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) mask = ~0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (type & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) mask = ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) res->name = dev->subordinate->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) res->flags = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) region.start = config_readl(socket, addr_start) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) region.end = config_readl(socket, addr_end) | ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (region.start && region.end > region.start && !override_bios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) pcibios_bus_to_resource(dev->bus, res, ®ion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (pci_claim_resource(dev, nr) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_info(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) "Preassigned resource %d busy or not available, reconfiguring...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (type & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if ((yenta_search_res(socket, res, BRIDGE_IO_MAX)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) (yenta_search_res(socket, res, BRIDGE_IO_ACC)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) (yenta_search_res(socket, res, BRIDGE_IO_MIN)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (type & IORESOURCE_PREFETCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if ((yenta_search_res(socket, res, BRIDGE_MEM_MAX)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) (yenta_search_res(socket, res, BRIDGE_MEM_ACC)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) (yenta_search_res(socket, res, BRIDGE_MEM_MIN)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* Approximating prefetchable by non-prefetchable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) res->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if ((yenta_search_res(socket, res, BRIDGE_MEM_MAX)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) (yenta_search_res(socket, res, BRIDGE_MEM_ACC)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) (yenta_search_res(socket, res, BRIDGE_MEM_MIN)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev_info(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "no resource of type %x available, trying to continue...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) res->start = res->end = res->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static void yenta_free_res(struct yenta_socket *socket, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct pci_dev *dev = socket->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) res = &dev->resource[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (res->start != 0 && res->end != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) release_resource(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) res->start = res->end = res->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * Allocate the bridge mappings for the device..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static void yenta_allocate_resources(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) int program = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) program += yenta_allocate_res(socket, PCI_CB_BRIDGE_IO_0_WINDOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PCI_CB_IO_BASE_0, PCI_CB_IO_LIMIT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) program += yenta_allocate_res(socket, PCI_CB_BRIDGE_IO_1_WINDOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PCI_CB_IO_BASE_1, PCI_CB_IO_LIMIT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) program += yenta_allocate_res(socket, PCI_CB_BRIDGE_MEM_0_WINDOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) IORESOURCE_MEM | IORESOURCE_PREFETCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PCI_CB_MEMORY_BASE_0, PCI_CB_MEMORY_LIMIT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) program += yenta_allocate_res(socket, PCI_CB_BRIDGE_MEM_1_WINDOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PCI_CB_MEMORY_BASE_1, PCI_CB_MEMORY_LIMIT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (program)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pci_setup_cardbus(socket->dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * Free the bridge mappings for the device..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static void yenta_free_resources(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) yenta_free_res(socket, PCI_CB_BRIDGE_IO_0_WINDOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) yenta_free_res(socket, PCI_CB_BRIDGE_IO_1_WINDOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) yenta_free_res(socket, PCI_CB_BRIDGE_MEM_0_WINDOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) yenta_free_res(socket, PCI_CB_BRIDGE_MEM_1_WINDOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * Close it down - release our resources and go home..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static void yenta_close(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct yenta_socket *sock = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Remove the register attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) device_remove_file(&dev->dev, &dev_attr_yenta_registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* we don't want a dying socket registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) pcmcia_unregister_socket(&sock->socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* Disable all events so we don't die in an IRQ storm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) cb_writel(sock, CB_SOCKET_MASK, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) exca_writeb(sock, I365_CSCINT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (sock->cb_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) free_irq(sock->cb_irq, sock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) del_timer_sync(&sock->poll_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) iounmap(sock->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) yenta_free_resources(sock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) pci_set_drvdata(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) kfree(sock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static struct pccard_operations yenta_socket_operations = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .init = yenta_sock_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .suspend = yenta_sock_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .get_status = yenta_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .set_socket = yenta_set_socket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .set_io_map = yenta_set_io_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .set_mem_map = yenta_set_mem_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #ifdef CONFIG_YENTA_TI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #include "ti113x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #ifdef CONFIG_YENTA_RICOH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #include "ricoh.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #ifdef CONFIG_YENTA_TOSHIBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #include "topic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #ifdef CONFIG_YENTA_O2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #include "o2micro.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) CARDBUS_TYPE_DEFAULT = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) CARDBUS_TYPE_TI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) CARDBUS_TYPE_TI113X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) CARDBUS_TYPE_TI12XX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) CARDBUS_TYPE_TI1250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) CARDBUS_TYPE_RICOH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) CARDBUS_TYPE_TOPIC95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) CARDBUS_TYPE_TOPIC97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) CARDBUS_TYPE_O2MICRO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) CARDBUS_TYPE_ENE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * Different cardbus controllers have slightly different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * initialization sequences etc details. List them here..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static struct cardbus_type cardbus_type[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #ifdef CONFIG_YENTA_TI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) [CARDBUS_TYPE_TI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .override = ti_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .save_state = ti_save_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .restore_state = ti_restore_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .sock_init = ti_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) [CARDBUS_TYPE_TI113X] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .override = ti113x_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .save_state = ti_save_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .restore_state = ti_restore_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .sock_init = ti_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) [CARDBUS_TYPE_TI12XX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .override = ti12xx_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .save_state = ti_save_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .restore_state = ti_restore_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .sock_init = ti_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) [CARDBUS_TYPE_TI1250] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .override = ti1250_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .save_state = ti_save_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .restore_state = ti_restore_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .sock_init = ti_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) [CARDBUS_TYPE_ENE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .override = ene_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .save_state = ti_save_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .restore_state = ti_restore_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .sock_init = ti_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #ifdef CONFIG_YENTA_RICOH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) [CARDBUS_TYPE_RICOH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .override = ricoh_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .save_state = ricoh_save_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .restore_state = ricoh_restore_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #ifdef CONFIG_YENTA_TOSHIBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) [CARDBUS_TYPE_TOPIC95] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .override = topic95_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) [CARDBUS_TYPE_TOPIC97] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .override = topic97_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #ifdef CONFIG_YENTA_O2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) [CARDBUS_TYPE_O2MICRO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .override = o2micro_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .restore_state = o2micro_restore_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static unsigned int yenta_probe_irq(struct yenta_socket *socket, u32 isa_irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * Probe for usable interrupts using the force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * register to generate bogus card status events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) cb_writel(socket, CB_SOCKET_EVENT, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) reg = exca_readb(socket, I365_CSCINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) exca_writeb(socket, I365_CSCINT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) val = probe_irq_on() & isa_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) for (i = 1; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (!((val >> i) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) exca_writeb(socket, I365_CSCINT, I365_CSC_STSCHG | (i << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) cb_writel(socket, CB_SOCKET_FORCE, CB_FCARDSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) cb_writel(socket, CB_SOCKET_EVENT, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) cb_writel(socket, CB_SOCKET_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) exca_writeb(socket, I365_CSCINT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) mask = probe_irq_mask(val) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * yenta PCI irq probing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * currently only used in the TI/EnE initialization code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #ifdef CONFIG_YENTA_TI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* interrupt handler, only used during probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static irqreturn_t yenta_probe_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct yenta_socket *socket = (struct yenta_socket *) dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) u8 csc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u32 cb_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* Clear interrupt status for the event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) cb_event = cb_readl(socket, CB_SOCKET_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) cb_writel(socket, CB_SOCKET_EVENT, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) csc = exca_readb(socket, I365_CSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (cb_event || csc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) socket->probe_status = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* probes the PCI interrupt, use only on override functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static int yenta_probe_cb_irq(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) u8 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (!socket->cb_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) socket->probe_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (request_irq(socket->cb_irq, yenta_probe_handler, IRQF_SHARED, "yenta", socket)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dev_warn(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) "request_irq() in yenta_probe_cb_irq() failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* generate interrupt, wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (!socket->dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) reg = exca_readb(socket, I365_CSCINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) exca_writeb(socket, I365_CSCINT, reg | I365_CSC_STSCHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) cb_writel(socket, CB_SOCKET_EVENT, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) cb_writel(socket, CB_SOCKET_FORCE, CB_FCARDSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) cb_writel(socket, CB_SOCKET_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) exca_writeb(socket, I365_CSCINT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) cb_writel(socket, CB_SOCKET_EVENT, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) exca_readb(socket, I365_CSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) free_irq(socket->cb_irq, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return (int) socket->probe_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #endif /* CONFIG_YENTA_TI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * Set static data that doesn't need re-initializing..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static void yenta_get_socket_capabilities(struct yenta_socket *socket, u32 isa_irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) socket->socket.pci_irq = socket->cb_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (isa_probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) socket->socket.irq_mask = yenta_probe_irq(socket, isa_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) socket->socket.irq_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) dev_info(&socket->dev->dev, "ISA IRQ mask 0x%04x, PCI irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) socket->socket.irq_mask, socket->cb_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * Initialize the standard cardbus registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static void yenta_config_init(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) u16 bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct pci_dev *dev = socket->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) pcibios_resource_to_bus(socket->dev->bus, ®ion, &dev->resource[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) config_writel(socket, CB_LEGACY_MODE_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) config_writel(socket, PCI_BASE_ADDRESS_0, region.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) config_writew(socket, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PCI_COMMAND_IO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PCI_COMMAND_MEMORY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PCI_COMMAND_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PCI_COMMAND_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* MAGIC NUMBERS! Fixme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) config_writeb(socket, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) config_writeb(socket, PCI_LATENCY_TIMER, 168);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) config_writel(socket, PCI_PRIMARY_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) (176 << 24) | /* sec. latency timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ((unsigned int)dev->subordinate->busn_res.end << 16) | /* subordinate bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ((unsigned int)dev->subordinate->busn_res.start << 8) | /* secondary bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dev->subordinate->primary); /* primary bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * Set up the bridging state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * - enable write posting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * - memory window 0 prefetchable, window 1 non-prefetchable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * - PCI interrupts enabled if a PCI interrupt exists..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) bridge = config_readw(socket, CB_BRIDGE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) bridge &= ~(CB_BRIDGE_CRST | CB_BRIDGE_PREFETCH1 | CB_BRIDGE_ISAEN | CB_BRIDGE_VGAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) bridge |= CB_BRIDGE_PREFETCH0 | CB_BRIDGE_POSTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) config_writew(socket, CB_BRIDGE_CONTROL, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * yenta_fixup_parent_bridge - Fix subordinate bus# of the parent bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * @cardbus_bridge: The PCI bus which the CardBus bridge bridges to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * Checks if devices on the bus which the CardBus bridge bridges to would be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * invisible during PCI scans because of a misconfigured subordinate number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * of the parent brige - some BIOSes seem to be too lazy to set it right.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * Does the fixup carefully by checking how far it can go without conflicts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * See http://bugzilla.kernel.org/show_bug.cgi?id=2944 for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static void yenta_fixup_parent_bridge(struct pci_bus *cardbus_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct pci_bus *sibling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) unsigned char upper_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * We only check and fix the parent bridge: All systems which need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * this fixup that have been reviewed are laptops and the only bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * which needed fixing was the parent bridge of the CardBus bridge:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct pci_bus *bridge_to_fix = cardbus_bridge->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* Check bus numbers are already set up correctly: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (bridge_to_fix->busn_res.end >= cardbus_bridge->busn_res.end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return; /* The subordinate number is ok, nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (!bridge_to_fix->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return; /* Root bridges are ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* stay within the limits of the bus range of the parent: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) upper_limit = bridge_to_fix->parent->busn_res.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /* check the bus ranges of all sibling bridges to prevent overlap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) list_for_each_entry(sibling, &bridge_to_fix->parent->children,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * If the sibling has a higher secondary bus number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * and it's secondary is equal or smaller than our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * current upper limit, set the new upper limit to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * the bus number below the sibling's range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (sibling->busn_res.start > bridge_to_fix->busn_res.end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) && sibling->busn_res.start <= upper_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) upper_limit = sibling->busn_res.start - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* Show that the wanted subordinate number is not possible: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (cardbus_bridge->busn_res.end > upper_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dev_warn(&cardbus_bridge->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) "Upper limit for fixing this bridge's parent bridge: #%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) upper_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* If we have room to increase the bridge's subordinate number, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (bridge_to_fix->busn_res.end < upper_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* use the highest number of the hidden bus, within limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) unsigned char subordinate_to_assign =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) min_t(int, cardbus_bridge->busn_res.end, upper_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) dev_info(&bridge_to_fix->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) "Raising subordinate bus# of parent bus (#%02x) from #%02x to #%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) bridge_to_fix->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) (int)bridge_to_fix->busn_res.end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) subordinate_to_assign);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* Save the new subordinate in the bus struct of the bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) bridge_to_fix->busn_res.end = subordinate_to_assign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* and update the PCI config space with the new subordinate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) pci_write_config_byte(bridge_to_fix->self,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PCI_SUBORDINATE_BUS, bridge_to_fix->busn_res.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * Initialize a cardbus controller. Make sure we have a usable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * interrupt, and that we can map the cardbus area. Fill in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * socket information structure..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static int yenta_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct yenta_socket *socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * If we failed to assign proper bus numbers for this cardbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * controller during PCI probe, its subordinate pci_bus is NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * Bail out if so.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (!dev->subordinate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) dev_err(&dev->dev, "no bus associated! (try 'pci=assign-busses')\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) socket = kzalloc(sizeof(struct yenta_socket), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (!socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /* prepare pcmcia_socket */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) socket->socket.ops = ¥ta_socket_operations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) socket->socket.resource_ops = &pccard_nonstatic_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) socket->socket.dev.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) socket->socket.driver_data = socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) socket->socket.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) socket->socket.features = SS_CAP_PAGE_REGS | SS_CAP_PCCARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) socket->socket.map_size = 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) socket->socket.cb_dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* prepare struct yenta_socket */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) socket->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) pci_set_drvdata(dev, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * Do some basic sanity checking..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (pci_enable_device(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ret = pci_request_regions(dev, "yenta_socket");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (!pci_resource_start(dev, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) dev_err(&dev->dev, "No cardbus resource!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * Ok, start setup.. Map the cardbus registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * and request the IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) socket->base = ioremap(pci_resource_start(dev, 0), 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (!socket->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * report the subsystem vendor and device for help debugging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * the irq stuff...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_info(&dev->dev, "CardBus bridge found [%04x:%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dev->subsystem_vendor, dev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) yenta_config_init(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* Disable all events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) cb_writel(socket, CB_SOCKET_MASK, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* Set up the bridge regions.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) yenta_allocate_resources(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) socket->cb_irq = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* Do we have special options for the device? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (id->driver_data != CARDBUS_TYPE_DEFAULT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) id->driver_data < ARRAY_SIZE(cardbus_type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) socket->type = &cardbus_type[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) ret = socket->type->override(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /* We must finish initialization here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (!socket->cb_irq || request_irq(socket->cb_irq, yenta_interrupt, IRQF_SHARED, "yenta", socket)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* No IRQ or request_irq failed. Poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) socket->cb_irq = 0; /* But zero is a valid IRQ number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) timer_setup(&socket->poll_timer, yenta_interrupt_wrapper, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) mod_timer(&socket->poll_timer, jiffies + HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) dev_info(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) "no PCI IRQ, CardBus support disabled for this socket.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) dev_info(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) "check your BIOS CardBus, BIOS IRQ or ACPI settings.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) socket->socket.features |= SS_CAP_CARDBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /* Figure out what the dang thing can do for the PCMCIA layer... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) yenta_interrogate(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) yenta_get_socket_capabilities(socket, isa_interrupts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) dev_info(&dev->dev, "Socket status: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) cb_readl(socket, CB_SOCKET_STATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) yenta_fixup_parent_bridge(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* Register it with the pcmcia layer.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ret = pcmcia_register_socket(&socket->socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) goto free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* Add the yenta register attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ret = device_create_file(&dev->dev, &dev_attr_yenta_registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) goto unregister_socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* error path... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) unregister_socket:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) pcmcia_unregister_socket(&socket->socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (socket->cb_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) free_irq(socket->cb_irq, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) del_timer_sync(&socket->poll_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) iounmap(socket->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) yenta_free_resources(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) pci_set_drvdata(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) kfree(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static int yenta_dev_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct yenta_socket *socket = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (!socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (socket->type && socket->type->save_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) socket->type->save_state(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) pci_read_config_dword(pdev, 16*4, &socket->saved_state[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) pci_read_config_dword(pdev, 17*4, &socket->saved_state[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static int yenta_dev_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct yenta_socket *socket = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (!socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) pci_write_config_dword(pdev, 16*4, socket->saved_state[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) pci_write_config_dword(pdev, 17*4, socket->saved_state[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ret = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (socket->type && socket->type->restore_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) socket->type->restore_state(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static const struct dev_pm_ops yenta_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .suspend_noirq = yenta_dev_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .resume_noirq = yenta_dev_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .freeze_noirq = yenta_dev_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .thaw_noirq = yenta_dev_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .poweroff_noirq = yenta_dev_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .restore_noirq = yenta_dev_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define YENTA_PM_OPS (¥ta_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define YENTA_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define CB_ID(vend, dev, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .vendor = vend, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .device = dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .subvendor = PCI_ANY_ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .subdevice = PCI_ANY_ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .class = PCI_CLASS_BRIDGE_CARDBUS << 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .class_mask = ~0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .driver_data = CARDBUS_TYPE_##type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static const struct pci_device_id yenta_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1031, TI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * TBD: Check if these TI variants can use more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * advanced overrides instead. (I can't get the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * data sheets for these devices. --rmk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #ifdef CONFIG_YENTA_TI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1210, TI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1130, TI113X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1131, TI113X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1211, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1220, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1221, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1225, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1251A, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1251B, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1450, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1451A, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1520, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1620, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_4410, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_4450, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_4451, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_4510, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_4520, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1250, TI1250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1410, TI1250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XX21_XX11, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_X515, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XX12, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_X420, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_X620, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_7410, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_7510, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) CB_ID(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_7610, TI12XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_710, ENE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_712, ENE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_720, ENE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_722, ENE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_1211, ENE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_1225, ENE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_1410, ENE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) CB_ID(PCI_VENDOR_ID_ENE, PCI_DEVICE_ID_ENE_1420, ENE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #endif /* CONFIG_YENTA_TI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #ifdef CONFIG_YENTA_RICOH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) CB_ID(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C465, RICOH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) CB_ID(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C466, RICOH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) CB_ID(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C475, RICOH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) CB_ID(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, RICOH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) CB_ID(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C478, RICOH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #ifdef CONFIG_YENTA_TOSHIBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) CB_ID(PCI_VENDOR_ID_TOSHIBA, PCI_DEVICE_ID_TOSHIBA_TOPIC95, TOPIC95),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) CB_ID(PCI_VENDOR_ID_TOSHIBA, PCI_DEVICE_ID_TOSHIBA_TOPIC97, TOPIC97),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) CB_ID(PCI_VENDOR_ID_TOSHIBA, PCI_DEVICE_ID_TOSHIBA_TOPIC100, TOPIC97),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #ifdef CONFIG_YENTA_O2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) CB_ID(PCI_VENDOR_ID_O2, PCI_ANY_ID, O2MICRO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* match any cardbus bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) CB_ID(PCI_ANY_ID, PCI_ANY_ID, DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) { /* all zeroes */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) MODULE_DEVICE_TABLE(pci, yenta_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) static struct pci_driver yenta_cardbus_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .name = "yenta_cardbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .id_table = yenta_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .probe = yenta_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .remove = yenta_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .driver.pm = YENTA_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) module_pci_driver(yenta_cardbus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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