Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * FILE NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *	drivers/pcmcia/vrc4173_cardu.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * BRIEF MODULE DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Include file for NEC VRC4173 CARDU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright 2002 Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *  option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *  You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *  with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *  675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #ifndef _VRC4173_CARDU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define _VRC4173_CARDU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <pcmcia/ss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CARDU_MAX_SOCKETS	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CARDU1			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CARDU2			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * PCI Configuration Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define BRGCNT			0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  #define POST_WR_EN		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  #define MEM1_PREF_EN		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  #define MEM0_PREF_EN		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  #define IREQ_INT		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  #define CARD_RST		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  #define MABORT_MODE		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  #define VGA_EN			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  #define ISA_EN			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  #define SERR_EN		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  #define PERR_EN		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SYSCNT			0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  #define BAD_VCC_REQ_DISB	0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  #define PCPCI_EN		0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  #define CH_ASSIGN_MASK		0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  #define CH_ASSIGN_NODMA	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  #define SUB_ID_WR_EN		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  #define ASYN_INT_MODE		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  #define PCI_CLK_RIN		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define DEVCNT			0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  #define ZOOM_VIDEO_EN		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  #define SR_PCI_INT_SEL_MASK	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  #define SR_PCI_INT_SEL_NONE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  #define PCI_INT_MODE		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  #define IRQ_MODE		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  #define IFG			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CHIPCNT			0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  #define S_PREF_DISB		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define SERRDIS			0x9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  #define SERR_DIS_MAB		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  #define SERR_DIS_TAB		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  #define SERR_DIS_DT_PERR	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * ExCA Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define EXCA_REGS_BASE		0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define EXCA_REGS_SIZE		0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define ID_REV			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  #define IF_TYPE_16BIT		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define IF_STATUS		0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  #define CARD_PWR		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  #define READY			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  #define CARD_WP		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  #define CARD_DETECT2		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  #define CARD_DETECT1		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  #define BV_DETECT_MASK		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  #define BV_DETECT_GOOD		0x03	/* Memory card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  #define BV_DETECT_WARN		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  #define BV_DETECT_BAD1		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  #define BV_DETECT_BAD0		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  #define STSCHG			0x02	/* I/O card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  #define SPKR			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PWR_CNT			0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  #define CARD_OUT_EN		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  #define VCC_MASK		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  #define VCC_3V			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  #define VCC_5V			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  #define VCC_0V			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  #define VPP_MASK		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  #define VPP_12V		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  #define VPP_VCC		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  #define VPP_0V			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define INT_GEN_CNT		0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  #define CARD_REST0		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  #define CARD_TYPE_MASK		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  #define CARD_TYPE_IO		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  #define CARD_TYPE_MEM		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CARD_SC			0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  #define CARD_DT_CHG		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  #define RDY_CHG		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  #define BAT_WAR_CHG		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  #define BAT_DEAD_ST_CHG	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CARD_SCI		0x005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  #define CARD_DT_EN		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  #define RDY_EN			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  #define BAT_WAR_EN		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  #define BAT_DEAD_EN		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ADR_WIN_EN		0x006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  #define IO_WIN_EN(x)		(0x40 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  #define MEM_WIN_EN(x)		(0x01 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IO_WIN_CNT		0x007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  #define IO_WIN_CNT_MASK(x)	(0x03 << ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  #define IO_WIN_DATA_AUTOSZ(x)	(0x02 << ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  #define IO_WIN_DATA_16BIT(x)	(0x01 << ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IO_WIN_SA(x)		(0x008 + ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IO_WIN_EA(x)		(0x00a + ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MEM_WIN_SA(x)		(0x010 + ((x) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  #define MEM_WIN_DSIZE		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MEM_WIN_EA(x)		(0x012 + ((x) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MEM_WIN_OA(x)		(0x014 + ((x) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  #define MEM_WIN_WP		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  #define MEM_WIN_REGSET		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GEN_CNT			0x016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  #define VS2_STATUS		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  #define VS1_STATUS		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  #define EXCA_REG_RST_EN	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GLO_CNT			0x01e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  #define FUN_INT_LEV		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  #define INT_WB_CLR		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  #define CSC_INT_LEV		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IO_WIN_OAL(x)		(0x036 + ((x) << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IO_WIN_OAH(x)		(0x037 + ((x) << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MEM_WIN_SAU(x)		(0x040 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IO_SETUP_TIM		0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IO_CMD_TIM		0x081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IO_HOLD_TIM		0x082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MEM_SETUP_TIM(x)	(0x084 + ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MEM_CMD_TIM(x)		(0x085 + ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MEM_HOLD_TIM(x)		(0x086 + ((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  #define TIM_CLOCKS(x)		((x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MEM_TIM_SEL1		0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MEM_TIM_SEL2		0x08d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  #define MEM_WIN_TIMSEL1(x)	(0x03 << (((x) & 3) << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MEM_WIN_PWEN		0x091
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  #define POSTWEN		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  * CardBus Socket Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CARDBUS_SOCKET_REGS_BASE	0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CARDBUS_SOCKET_REGS_SIZE	0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SKT_EV			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  #define POW_CYC_EV		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  #define CCD2_EV		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  #define CCD1_EV		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  #define CSTSCHG_EV		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SKT_MASK		0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  #define POW_CYC_MASK		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  #define CCD_MASK		0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  #define CSC_MASK		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SKT_PRE_STATE		0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SKT_FORCE_EV		0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  #define VOL_3V_SKT		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  #define VOL_5V_SKT		0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  #define CVS_TEST		0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  #define VOL_YV_CARD_DT		0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  #define VOL_XV_CARD_DT		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  #define VOL_3V_CARD_DT		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  #define VOL_5V_CARD_DT		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  #define BAD_VCC_REQ		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  #define DATA_LOST		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  #define NOT_A_CARD		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  #define CREADY			0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  #define CB_CARD_DT		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  #define R2_CARD_DT		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  #define POW_UP			0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  #define CCD20			0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  #define CCD10			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  #define CSTSCHG		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SKT_CNT			0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  #define STP_CLK_EN		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  #define VCC_CNT_MASK		0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  #define VCC_CNT_3V		0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  #define VCC_CNT_5V		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  #define VCC_CNT_0V		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  #define VPP_CNT_MASK		0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  #define VPP_CNT_3V		0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  #define VPP_CNT_5V		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  #define VPP_CNT_12V		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  #define VPP_CNT_0V		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) typedef struct vrc4173_socket {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	int noprobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	void *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	void (*handler)(void *, unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	void *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	socket_cap_t cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	spinlock_t event_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	uint16_t events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct socket_info_t *pcmcia_socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct work_struct tq_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	char name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) } vrc4173_socket_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #endif /* _VRC4173_CARDU_H */