^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * vrc4171_card.c, NEC VRC4171 Card Controller driver for Socket Services.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <pcmcia/ss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "i82365.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MODULE_DESCRIPTION("NEC VRC4171 Card Controllers driver for Socket Services");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CARD_MAX_SLOTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CARD_SLOTA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CARD_SLOTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CARD_SLOTB_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CARD_MEM_START 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CARD_MEM_END 0x13ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CARD_MAX_MEM_OFFSET 0x3ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CARD_MAX_MEM_SPEED 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CARD_CONTROLLER_INDEX 0x03e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CARD_CONTROLLER_DATA 0x03e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Power register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VPP_GET_VCC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define POWER_ENABLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CARD_VOLTAGE_SENSE 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VCC_3VORXV_CAPABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VCC_XV_ONLY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VCC_3V_CAPABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VCC_5V_ONLY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CARD_VOLTAGE_SELECT 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VCC_3V 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VCC_5V 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VCC_XV 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VCC_STATUS_3V 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VCC_STATUS_5V 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VCC_STATUS_XV 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GLOBAL_CONTROL 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EXWRBK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IRQPM_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLRPMIRQ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define INTERRUPT_STATUS 0x05fa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IRQ_A 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IRQ_B 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CONFIGURATION1 0x05fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SLOTB_CONFIG 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SLOTB_NONE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SLOTB_PCCARD 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SLOTB_CF 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SLOTB_FLASHROM 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CARD_CONTROLLER_START CARD_CONTROLLER_INDEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CARD_CONTROLLER_END CARD_CONTROLLER_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IO_MAX_MAPS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MEM_MAX_MAPS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enum vrc4171_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SLOT_PROBE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SLOT_NOPROBE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SLOT_NOPROBE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SLOT_NOPROBE_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SLOT_INITIALIZED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum vrc4171_slotb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SLOTB_IS_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SLOTB_IS_PCCARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SLOTB_IS_CF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SLOTB_IS_FLASHROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct vrc4171_socket {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) enum vrc4171_slot slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct pcmcia_socket pcmcia_socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) char name[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int csc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int io_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct vrc4171_socket vrc4171_sockets[CARD_MAX_SLOTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static enum vrc4171_slotb vrc4171_slotb = SLOTB_IS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static char vrc4171_card_name[] = "NEC VRC4171 Card Controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static unsigned int vrc4171_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static uint16_t vrc4171_irq_mask = 0xdeb8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct resource vrc4171_card_resource[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { .name = vrc4171_card_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .start = CARD_CONTROLLER_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .end = CARD_CONTROLLER_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .flags = IORESOURCE_IO, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { .name = vrc4171_card_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .start = INTERRUPT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .end = INTERRUPT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .flags = IORESOURCE_IO, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { .name = vrc4171_card_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .start = CONFIGURATION1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .end = CONFIGURATION1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .flags = IORESOURCE_IO, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct platform_device vrc4171_card_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .name = vrc4171_card_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .num_resources = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .resource = vrc4171_card_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline uint16_t vrc4171_get_irq_status(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return inw(INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline void vrc4171_set_multifunction_pin(enum vrc4171_slotb config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) uint16_t config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) config1 = inw(CONFIGURATION1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) config1 &= ~SLOTB_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) switch (config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case SLOTB_IS_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) config1 |= SLOTB_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case SLOTB_IS_PCCARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) config1 |= SLOTB_PCCARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case SLOTB_IS_CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) config1 |= SLOTB_CF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case SLOTB_IS_FLASHROM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) config1 |= SLOTB_FLASHROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) outw(config1, CONFIGURATION1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static inline uint8_t exca_read_byte(int slot, uint8_t index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (slot == CARD_SLOTB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) index += CARD_SLOTB_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) outb(index, CARD_CONTROLLER_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return inb(CARD_CONTROLLER_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline uint16_t exca_read_word(int slot, uint8_t index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) uint16_t data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (slot == CARD_SLOTB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) index += CARD_SLOTB_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) outb(index++, CARD_CONTROLLER_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) data = inb(CARD_CONTROLLER_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) outb(index, CARD_CONTROLLER_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) data |= ((uint16_t)inb(CARD_CONTROLLER_DATA)) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static inline uint8_t exca_write_byte(int slot, uint8_t index, uint8_t data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (slot == CARD_SLOTB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) index += CARD_SLOTB_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) outb(index, CARD_CONTROLLER_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) outb(data, CARD_CONTROLLER_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static inline uint16_t exca_write_word(int slot, uint8_t index, uint16_t data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (slot == CARD_SLOTB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) index += CARD_SLOTB_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) outb(index++, CARD_CONTROLLER_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) outb(data, CARD_CONTROLLER_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) outb(index, CARD_CONTROLLER_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) outb((uint8_t)(data >> 8), CARD_CONTROLLER_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static inline int search_nonuse_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (vrc4171_irq_mask & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) vrc4171_irq_mask &= ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int pccard_init(struct pcmcia_socket *sock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct vrc4171_socket *socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) sock->features |= SS_CAP_PCCARD | SS_CAP_PAGE_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) sock->irq_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) sock->map_size = 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) sock->pci_irq = vrc4171_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) slot = sock->sock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) socket = &vrc4171_sockets[slot];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) socket->csc_irq = search_nonuse_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) socket->io_irq = search_nonuse_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) spin_lock_init(&socket->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int pccard_get_status(struct pcmcia_socket *sock, u_int *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) uint8_t status, sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u_int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (sock == NULL || sock->sock >= CARD_MAX_SLOTS || value == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) slot = sock->sock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) status = exca_read_byte(slot, I365_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (exca_read_byte(slot, I365_INTCTL) & I365_PC_IOCARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (status & I365_CS_STSCHG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) val |= SS_STSCHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!(status & I365_CS_BVD1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) val |= SS_BATDEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) else if ((status & (I365_CS_BVD1 | I365_CS_BVD2)) == I365_CS_BVD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) val |= SS_BATWARN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if ((status & I365_CS_DETECT) == I365_CS_DETECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) val |= SS_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (status & I365_CS_WRPROT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) val |= SS_WRPROT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (status & I365_CS_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) val |= SS_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (status & I365_CS_POWERON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val |= SS_POWERON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) sense = exca_read_byte(slot, CARD_VOLTAGE_SENSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) switch (sense) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case VCC_3VORXV_CAPABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) val |= SS_3VCARD | SS_XVCARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case VCC_XV_ONLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) val |= SS_XVCARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case VCC_3V_CAPABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) val |= SS_3VCARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* 5V only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *value = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static inline uint8_t set_Vcc_value(u_char Vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) switch (Vcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case 33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return VCC_3V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return VCC_5V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Small voltage is chosen for safety. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return VCC_3V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int pccard_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct vrc4171_socket *socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) uint8_t voltage, power, control, cscint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (sock == NULL || sock->sock >= CARD_MAX_SLOTS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) (state->Vpp != state->Vcc && state->Vpp != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) (state->Vcc != 50 && state->Vcc != 33 && state->Vcc != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) slot = sock->sock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) socket = &vrc4171_sockets[slot];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) spin_lock_irq(&socket->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) voltage = set_Vcc_value(state->Vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) exca_write_byte(slot, CARD_VOLTAGE_SELECT, voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) power = POWER_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (state->Vpp == state->Vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) power |= VPP_GET_VCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (state->flags & SS_OUTPUT_ENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) power |= I365_PWR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) exca_write_byte(slot, I365_POWER, power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (state->io_irq != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) control |= socket->io_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (state->flags & SS_IOCARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) control |= I365_PC_IOCARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (state->flags & SS_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) control &= ~I365_PC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) control |= I365_PC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) exca_write_byte(slot, I365_INTCTL, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) cscint = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) exca_write_byte(slot, I365_CSCINT, cscint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) exca_read_byte(slot, I365_CSC); /* clear CardStatus change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (state->csc_mask != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) cscint |= socket->csc_irq << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (state->flags & SS_IOCARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (state->csc_mask & SS_STSCHG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cscint |= I365_CSC_STSCHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (state->csc_mask & SS_BATDEAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) cscint |= I365_CSC_BVD1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (state->csc_mask & SS_BATWARN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) cscint |= I365_CSC_BVD2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (state->csc_mask & SS_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cscint |= I365_CSC_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (state->csc_mask & SS_DETECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) cscint |= I365_CSC_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) exca_write_byte(slot, I365_CSCINT, cscint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) spin_unlock_irq(&socket->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int pccard_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) uint8_t ioctl, addrwin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u_char map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (sock == NULL || sock->sock >= CARD_MAX_SLOTS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) io == NULL || io->map >= IO_MAX_MAPS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) io->start > 0xffff || io->stop > 0xffff || io->start > io->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) slot = sock->sock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) map = io->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) addrwin = exca_read_byte(slot, I365_ADDRWIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (addrwin & I365_ENA_IO(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) addrwin &= ~I365_ENA_IO(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) exca_write_byte(slot, I365_ADDRWIN, addrwin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) exca_write_word(slot, I365_IO(map)+I365_W_START, io->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) exca_write_word(slot, I365_IO(map)+I365_W_STOP, io->stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ioctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (io->speed > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ioctl |= I365_IOCTL_WAIT(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (io->flags & MAP_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ioctl |= I365_IOCTL_16BIT(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (io->flags & MAP_AUTOSZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ioctl |= I365_IOCTL_IOCS16(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (io->flags & MAP_0WS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ioctl |= I365_IOCTL_0WS(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) exca_write_byte(slot, I365_IOCTL, ioctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (io->flags & MAP_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) addrwin |= I365_ENA_IO(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) exca_write_byte(slot, I365_ADDRWIN, addrwin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int pccard_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) uint16_t start, stop, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) uint8_t addrwin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u_char map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (sock == NULL || sock->sock >= CARD_MAX_SLOTS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mem == NULL || mem->map >= MEM_MAX_MAPS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) mem->res->start < CARD_MEM_START || mem->res->start > CARD_MEM_END ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) mem->res->end < CARD_MEM_START || mem->res->end > CARD_MEM_END ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mem->res->start > mem->res->end ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mem->card_start > CARD_MAX_MEM_OFFSET ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mem->speed > CARD_MAX_MEM_SPEED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) slot = sock->sock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) map = mem->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) addrwin = exca_read_byte(slot, I365_ADDRWIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (addrwin & I365_ENA_MEM(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) addrwin &= ~I365_ENA_MEM(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) exca_write_byte(slot, I365_ADDRWIN, addrwin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) start = (mem->res->start >> 12) & 0x3fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (mem->flags & MAP_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) start |= I365_MEM_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) exca_write_word(slot, I365_MEM(map)+I365_W_START, start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) stop = (mem->res->end >> 12) & 0x3fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) switch (mem->speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) stop |= I365_MEM_WS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) stop |= I365_MEM_WS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) stop |= I365_MEM_WS0 | I365_MEM_WS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) exca_write_word(slot, I365_MEM(map)+I365_W_STOP, stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) offset = (mem->card_start >> 12) & 0x3fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (mem->flags & MAP_ATTRIB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) offset |= I365_MEM_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (mem->flags & MAP_WRPROT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) offset |= I365_MEM_WRPROT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) exca_write_word(slot, I365_MEM(map)+I365_W_OFF, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (mem->flags & MAP_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) addrwin |= I365_ENA_MEM(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) exca_write_byte(slot, I365_ADDRWIN, addrwin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct pccard_operations vrc4171_pccard_operations = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .init = pccard_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .get_status = pccard_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .set_socket = pccard_set_socket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .set_io_map = pccard_set_io_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .set_mem_map = pccard_set_mem_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static inline unsigned int get_events(int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned int events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) uint8_t status, csc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) status = exca_read_byte(slot, I365_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) csc = exca_read_byte(slot, I365_CSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (exca_read_byte(slot, I365_INTCTL) & I365_PC_IOCARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if ((csc & I365_CSC_STSCHG) && (status & I365_CS_STSCHG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) events |= SS_STSCHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (csc & (I365_CSC_BVD1 | I365_CSC_BVD2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!(status & I365_CS_BVD1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) events |= SS_BATDEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) else if ((status & (I365_CS_BVD1 | I365_CS_BVD2)) == I365_CS_BVD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) events |= SS_BATWARN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if ((csc & I365_CSC_READY) && (status & I365_CS_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) events |= SS_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if ((csc & I365_CSC_DETECT) && ((status & I365_CS_DETECT) == I365_CS_DETECT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) events |= SS_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static irqreturn_t pccard_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct vrc4171_socket *socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned int events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) irqreturn_t retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) uint16_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) status = vrc4171_get_irq_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (status & IRQ_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) socket = &vrc4171_sockets[CARD_SLOTA];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (socket->slot == SLOT_INITIALIZED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (status & (1 << socket->csc_irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) events = get_events(CARD_SLOTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (events != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pcmcia_parse_events(&socket->pcmcia_socket, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) retval = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (status & IRQ_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) socket = &vrc4171_sockets[CARD_SLOTB];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (socket->slot == SLOT_INITIALIZED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (status & (1 << socket->csc_irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) events = get_events(CARD_SLOTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (events != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pcmcia_parse_events(&socket->pcmcia_socket, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) retval = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static inline void reserve_using_irq(int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) irq = exca_read_byte(slot, I365_INTCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) irq &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) vrc4171_irq_mask &= ~(1 << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) irq = exca_read_byte(slot, I365_CSCINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) irq = (irq & 0xf0) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) vrc4171_irq_mask &= ~(1 << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int vrc4171_add_sockets(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct vrc4171_socket *socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int slot, retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) for (slot = 0; slot < CARD_MAX_SLOTS; slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (slot == CARD_SLOTB && vrc4171_slotb == SLOTB_IS_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) socket = &vrc4171_sockets[slot];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (socket->slot != SLOT_PROBE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) uint8_t addrwin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) switch (socket->slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case SLOT_NOPROBE_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) addrwin = exca_read_byte(slot, I365_ADDRWIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) addrwin &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) exca_write_byte(slot, I365_ADDRWIN, addrwin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case SLOT_NOPROBE_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) addrwin = exca_read_byte(slot, I365_ADDRWIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) addrwin &= 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) exca_write_byte(slot, I365_ADDRWIN, addrwin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) reserve_using_irq(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) sprintf(socket->name, "NEC VRC4171 Card Slot %1c", 'A' + slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) socket->pcmcia_socket.dev.parent = &vrc4171_card_device.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) socket->pcmcia_socket.ops = &vrc4171_pccard_operations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) socket->pcmcia_socket.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) retval = pcmcia_register_socket(&socket->pcmcia_socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) exca_write_byte(slot, I365_ADDRWIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) exca_write_byte(slot, GLOBAL_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) socket->slot = SLOT_INITIALIZED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static void vrc4171_remove_sockets(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct vrc4171_socket *socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) for (slot = 0; slot < CARD_MAX_SLOTS; slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (slot == CARD_SLOTB && vrc4171_slotb == SLOTB_IS_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) socket = &vrc4171_sockets[slot];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (socket->slot == SLOT_INITIALIZED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) pcmcia_unregister_socket(&socket->pcmcia_socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) socket->slot = SLOT_PROBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int vrc4171_card_setup(char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (options == NULL || *options == '\0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (strncmp(options, "irq:", 4) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) options += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) irq = simple_strtoul(options, &options, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (irq >= 0 && irq < nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) vrc4171_irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (*options != ',')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) options++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (strncmp(options, "slota:", 6) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) options += 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (*options != '\0') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (strncmp(options, "memnoprobe", 10) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) vrc4171_sockets[CARD_SLOTA].slot = SLOT_NOPROBE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) options += 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) } else if (strncmp(options, "ionoprobe", 9) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) vrc4171_sockets[CARD_SLOTA].slot = SLOT_NOPROBE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) options += 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) } else if ( strncmp(options, "noprobe", 7) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) vrc4171_sockets[CARD_SLOTA].slot = SLOT_NOPROBE_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) options += 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (*options != ',')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) options++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (strncmp(options, "slotb:", 6) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) options += 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (*options != '\0') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (strncmp(options, "pccard", 6) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) vrc4171_slotb = SLOTB_IS_PCCARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) options += 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) } else if (strncmp(options, "cf", 2) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) vrc4171_slotb = SLOTB_IS_CF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) options += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) } else if (strncmp(options, "flashrom", 8) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) vrc4171_slotb = SLOTB_IS_FLASHROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) options += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) } else if (strncmp(options, "none", 4) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) vrc4171_slotb = SLOTB_IS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) options += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (*options != ',')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) options++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (strncmp(options, "memnoprobe", 10) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) vrc4171_sockets[CARD_SLOTB].slot = SLOT_NOPROBE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (strncmp(options, "ionoprobe", 9) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) vrc4171_sockets[CARD_SLOTB].slot = SLOT_NOPROBE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (strncmp(options, "noprobe", 7) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) vrc4171_sockets[CARD_SLOTB].slot = SLOT_NOPROBE_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) __setup("vrc4171_card=", vrc4171_card_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static struct platform_driver vrc4171_card_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .name = vrc4171_card_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int vrc4171_card_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) retval = platform_driver_register(&vrc4171_card_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) retval = platform_device_register(&vrc4171_card_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) platform_driver_unregister(&vrc4171_card_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) vrc4171_set_multifunction_pin(vrc4171_slotb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) retval = vrc4171_add_sockets();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (retval == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) retval = request_irq(vrc4171_irq, pccard_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) vrc4171_card_name, vrc4171_sockets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) vrc4171_remove_sockets();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) platform_device_unregister(&vrc4171_card_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) platform_driver_unregister(&vrc4171_card_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) printk(KERN_INFO "%s, connected to IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) vrc4171_card_driver.driver.name, vrc4171_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static void vrc4171_card_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) free_irq(vrc4171_irq, vrc4171_sockets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) vrc4171_remove_sockets();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) platform_device_unregister(&vrc4171_card_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) platform_driver_unregister(&vrc4171_card_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) module_init(vrc4171_card_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) module_exit(vrc4171_card_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags