^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * topic.h 1.8 1999/08/28 04:01:47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * The contents of this file are subject to the Mozilla Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Version 1.1 (the "License"); you may not use this file except in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * compliance with the License. You may obtain a copy of the License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * at http://www.mozilla.org/MPL/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software distributed under the License is distributed on an "AS IS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the License for the specific language governing rights and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * limitations under the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * The initial developer of the original code is David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Alternatively, the contents of this file may be used under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * terms of the GNU General Public License version 2 (the "GPL"), in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * case the provisions of the GPL are applicable instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * above. If you wish to allow the use of your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * only under the terms of the GPL and not to allow others to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * your version of this file under the MPL, indicate your decision by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * deleting the provisions above and replace them with the notice and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * other provisions required by the GPL. If you do not delete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * provisions above, a recipient may use your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * under either the MPL or the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * topic.h $Release$ 1999/08/28 04:01:47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifndef _LINUX_TOPIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define _LINUX_TOPIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Register definitions for Toshiba ToPIC95/97/100 controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TOPIC_SOCKET_CONTROL 0x0090 /* 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TOPIC_SCR_IRQSEL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TOPIC_SLOT_CONTROL 0x00a0 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TOPIC_SLOT_SLOTON 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TOPIC_SLOT_SLOTEN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TOPIC_SLOT_ID_LOCK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TOPIC_SLOT_ID_WP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TOPIC_SLOT_PORT_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TOPIC_SLOT_PORT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TOPIC_SLOT_OFS_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TOPIC_CARD_CONTROL 0x00a1 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TOPIC_CCR_INTB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TOPIC_CCR_INTA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TOPIC_CCR_CLOCK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TOPIC_CCR_PCICLK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TOPIC_CCR_PCICLK_2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TOPIC_CCR_CCLK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TOPIC97_INT_CONTROL 0x00a1 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TOPIC97_ICR_INTB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TOPIC97_ICR_INTA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TOPIC97_ICR_STSIRQNP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TOPIC97_ICR_IRQNP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TOPIC97_ICR_IRQSEL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TOPIC_CARD_DETECT 0x00a3 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TOPIC_CDR_MODE_PC32 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TOPIC_CDR_VS1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TOPIC_CDR_VS2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TOPIC_CDR_SW_DETECT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TOPIC_REGISTER_CONTROL 0x00a4 /* 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TOPIC_RCR_RESUME_RESET 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TOPIC_RCR_REMOVE_RESET 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TOPIC97_RCR_CLKRUN_ENA 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TOPIC97_RCR_TESTMODE 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TOPIC97_RCR_IOPLUP 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TOPIC_RCR_BUFOFF_PWROFF 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TOPIC_RCR_BUFOFF_SIGOFF 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TOPIC97_RCR_CB_DEV_MASK 0x0000f800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TOPIC97_RCR_CB_DEV_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TOPIC97_RCR_RI_DISABLE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TOPIC97_RCR_CAUDIO_OFF 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TOPIC_RCR_CAUDIO_INVERT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TOPIC97_MISC1 0x00ad /* 8bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TOPIC97_MISC1_CLOCKRUN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TOPIC97_MISC1_CLOCKRUN_MODE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TOPIC97_MISC1_DETECT_REQ_ENA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TOPIC97_MISC1_SCK_CLEAR_DIS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TOPIC97_MISC1_R2_LOW_ENABLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TOPIC97_MISC2 0x00ae /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TOPIC97_MISC2_SPWRCLK_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TOPIC97_MISC2_SPWRMOD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TOPIC97_MISC2_SPWR_ENABLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TOPIC97_MISC2_ZV_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TOPIC97_MISC2_ZV_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TOPIC97_ZOOM_VIDEO_CONTROL 0x009c /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TOPIC97_ZV_CONTROL_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TOPIC97_AUDIO_VIDEO_SWITCH 0x003c /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TOPIC97_AVS_AUDIO_CONTROL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TOPIC97_AVS_VIDEO_CONTROL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TOPIC_EXCA_IF_CONTROL 0x3e /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TOPIC_EXCA_IFC_33V_ENA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TOPIC_PCI_CFG_PPBCN 0x3e /* 16-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TOPIC_PCI_CFG_PPBCN_WBEN 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void topic97_zoom_video(struct pcmcia_socket *sock, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 reg_zv, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg_zv = config_readb(socket, TOPIC97_ZOOM_VIDEO_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (onoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reg_zv |= TOPIC97_ZV_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) config_writeb(socket, TOPIC97_ZOOM_VIDEO_CONTROL, reg_zv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) reg = config_readb(socket, TOPIC97_AUDIO_VIDEO_SWITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) reg |= TOPIC97_AVS_AUDIO_CONTROL | TOPIC97_AVS_VIDEO_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) config_writeb(socket, TOPIC97_AUDIO_VIDEO_SWITCH, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) reg_zv &= ~TOPIC97_ZV_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) config_writeb(socket, TOPIC97_ZOOM_VIDEO_CONTROL, reg_zv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg = config_readb(socket, TOPIC97_AUDIO_VIDEO_SWITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) reg &= ~(TOPIC97_AVS_AUDIO_CONTROL | TOPIC97_AVS_VIDEO_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) config_writeb(socket, TOPIC97_AUDIO_VIDEO_SWITCH, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int topic97_override(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* ToPIC97/100 support ZV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) socket->socket.zoom_video = topic97_zoom_video;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int topic95_override(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 fctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u16 ppbcn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* enable 3.3V support for 16bit cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) fctrl = exca_readb(socket, TOPIC_EXCA_IF_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) exca_writeb(socket, TOPIC_EXCA_IF_CONTROL, fctrl | TOPIC_EXCA_IFC_33V_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* tell yenta to use exca registers to power 16bit cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) socket->flags |= YENTA_16BIT_POWER_EXCA | YENTA_16BIT_POWER_DF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Disable write buffers to prevent lockups under load with numerous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) Cardbus cards, observed on Tecra 500CDT and reported elsewhere on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) net. This is not a power-on default according to the datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) but some BIOSes seem to set it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (pci_read_config_word(socket->dev, TOPIC_PCI_CFG_PPBCN, &ppbcn) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) && socket->dev->revision <= 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) && (ppbcn & TOPIC_PCI_CFG_PPBCN_WBEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ppbcn &= ~TOPIC_PCI_CFG_PPBCN_WBEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pci_write_config_word(socket->dev, TOPIC_PCI_CFG_PPBCN, ppbcn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_info(&socket->dev->dev, "Disabled ToPIC95 Cardbus write buffers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif /* _LINUX_TOPIC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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