^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * ti113x.h 1.16 1999/10/25 20:03:34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * The contents of this file are subject to the Mozilla Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Version 1.1 (the "License"); you may not use this file except in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * compliance with the License. You may obtain a copy of the License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * at http://www.mozilla.org/MPL/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software distributed under the License is distributed on an "AS IS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the License for the specific language governing rights and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * limitations under the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * The initial developer of the original code is David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Alternatively, the contents of this file may be used under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * terms of the GNU General Public License version 2 (the "GPL"), in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * case the provisions of the GPL are applicable instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * above. If you wish to allow the use of your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * only under the terms of the GPL and not to allow others to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * your version of this file under the MPL, indicate your decision by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * deleting the provisions above and replace them with the notice and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * other provisions required by the GPL. If you do not delete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * provisions above, a recipient may use your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * under either the MPL or the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifndef _LINUX_TI113X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define _LINUX_TI113X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Register definitions for TI 113X PCI-to-CardBus bridges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* System Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TI113X_SYSTEM_CONTROL 0x0080 /* 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TI113X_SCR_SMIROUTE 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TI113X_SCR_SMISTATUS 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TI113X_SCR_SMIENB 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TI113X_SCR_VCCPROT 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TI113X_SCR_REDUCEZV 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TI113X_SCR_CDREQEN 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TI113X_SCR_CDMACHAN 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TI113X_SCR_SOCACTIVE 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TI113X_SCR_PWRSTREAM 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TI113X_SCR_DELAYUP 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TI113X_SCR_DELAYDOWN 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TI113X_SCR_INTERROGATE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TI113X_SCR_CLKRUN_SEL 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TI113X_SCR_PWRSAVINGS 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TI113X_SCR_SUBSYSRW 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TI113X_SCR_CB_DPAR 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TI113X_SCR_CDMA_EN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TI113X_SCR_ASYNC_IRQ 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TI113X_SCR_KEEPCLK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TI113X_SCR_CLKRUN_ENA 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TI122X_SCR_SER_STEP 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TI122X_SCR_INTRTIE 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TIXX21_SCR_TIEALL 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TI122X_SCR_CBRSVD 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TI122X_SCR_MRBURSTDN 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TI122X_SCR_MRBURSTUP 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TI122X_SCR_RIMUX 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Multimedia Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TI1250_MULTIMEDIA_CTL 0x0084 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TI1250_MMC_ZVOUTEN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TI1250_MMC_PORTSEL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TI1250_MMC_ZVEN1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TI1250_MMC_ZVEN0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TI1250_GENERAL_STATUS 0x0085 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TI1250_GPIO0_CONTROL 0x0088 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TI1250_GPIO1_CONTROL 0x0089 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TI1250_GPIO2_CONTROL 0x008a /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TI1250_GPIO3_CONTROL 0x008b /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TI1250_GPIO_MODE_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* IRQMUX/MFUNC Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TI122X_MFUNC 0x008c /* 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TI122X_MFUNC0_MASK 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TI122X_MFUNC1_MASK 0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TI122X_MFUNC2_MASK 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TI122X_MFUNC3_MASK 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TI122X_MFUNC4_MASK 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TI122X_MFUNC5_MASK 0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TI122X_MFUNC6_MASK 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TI122X_MFUNC0_INTA 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TI125X_MFUNC0_INTB 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TI122X_MFUNC1_INTB 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TI122X_MFUNC3_IRQSER 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Retry Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TI113X_RETRY_STATUS 0x0090 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TI113X_RSR_PCIRETRY 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TI113X_RSR_CBRETRY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TI113X_RSR_TEXP_CBB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TI113X_RSR_MEXP_CBB 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TI113X_RSR_TEXP_CBA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TI113X_RSR_MEXP_CBA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TI113X_RSR_TEXP_PCI 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TI113X_RSR_MEXP_PCI 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Card Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TI113X_CARD_CONTROL 0x0091 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TI113X_CCR_RIENB 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TI113X_CCR_ZVENABLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TI113X_CCR_PCI_IRQ_ENA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TI113X_CCR_PCI_IREQ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TI113X_CCR_PCI_CSC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TI113X_CCR_SPKROUTEN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TI113X_CCR_IFG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TI1220_CCR_PORT_SEL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TI122X_CCR_AUD2MUX 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Device Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TI113X_DEVICE_CONTROL 0x0092 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TI113X_DCR_5V_FORCE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TI113X_DCR_3V_FORCE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TI113X_DCR_IMODE_MASK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TI113X_DCR_IMODE_ISA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TI113X_DCR_IMODE_SERIAL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TI12XX_DCR_IMODE_PCI_ONLY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Buffer Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TI113X_BUFFER_CONTROL 0x0093 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TI113X_BCR_CB_READ_DEPTH 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TI113X_BCR_CB_WRITE_DEPTH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TI113X_BCR_PCI_READ_DEPTH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TI113X_BCR_PCI_WRITE_DEPTH 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Diagnostic Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TI1250_DIAGNOSTIC 0x0093 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TI1250_DIAG_TRUE_VALUE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TI1250_DIAG_PCI_IREQ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TI1250_DIAG_PCI_CSC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TI1250_DIAG_ASYNC_CSC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* DMA Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TI113X_DMA_0 0x0094 /* 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TI113X_DMA_1 0x0098 /* 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* ExCA IO offset registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TI113X_IO_OFFSET(map) (0x36+((map)<<1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* EnE test register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ENE_TEST_C9 0xc9 /* 8bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ENE_TEST_C9_TLTENABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ENE_TEST_C9_PFENABLE_F0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ENE_TEST_C9_PFENABLE_F1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ENE_TEST_C9_PFENABLE (ENE_TEST_C9_PFENABLE_F0 | ENE_TEST_C9_PFENABLE_F1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ENE_TEST_C9_WPDISALBLE_F0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ENE_TEST_C9_WPDISALBLE_F1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ENE_TEST_C9_WPDISALBLE (ENE_TEST_C9_WPDISALBLE_F0 | ENE_TEST_C9_WPDISALBLE_F1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Texas Instruments CardBus controller overrides.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ti_sysctl(socket) ((socket)->private[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ti_cardctl(socket) ((socket)->private[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ti_devctl(socket) ((socket)->private[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ti_diag(socket) ((socket)->private[3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ti_mfunc(socket) ((socket)->private[4])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ene_test_c9(socket) ((socket)->private[5])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * These are the TI specific power management handlers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void ti_save_state(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ti_sysctl(socket) = config_readl(socket, TI113X_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ti_mfunc(socket) = config_readl(socket, TI122X_MFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ti_cardctl(socket) = config_readb(socket, TI113X_CARD_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ti_devctl(socket) = config_readb(socket, TI113X_DEVICE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ti_diag(socket) = config_readb(socket, TI1250_DIAGNOSTIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (socket->dev->vendor == PCI_VENDOR_ID_ENE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ene_test_c9(socket) = config_readb(socket, ENE_TEST_C9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void ti_restore_state(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) config_writel(socket, TI113X_SYSTEM_CONTROL, ti_sysctl(socket));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) config_writel(socket, TI122X_MFUNC, ti_mfunc(socket));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) config_writeb(socket, TI113X_CARD_CONTROL, ti_cardctl(socket));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) config_writeb(socket, TI113X_DEVICE_CONTROL, ti_devctl(socket));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) config_writeb(socket, TI1250_DIAGNOSTIC, ti_diag(socket));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (socket->dev->vendor == PCI_VENDOR_ID_ENE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) config_writeb(socket, ENE_TEST_C9, ene_test_c9(socket));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Zoom video control for TI122x/113x chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void ti_zoom_video(struct pcmcia_socket *sock, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* If we don't have a Zoom Video switch this is harmless,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) we just tristate the unused (ZV) lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) reg = config_readb(socket, TI113X_CARD_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Zoom zoom, we will all go together, zoom zoom, zoom zoom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg |= TI113X_CCR_ZVENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg &= ~TI113X_CCR_ZVENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) config_writeb(socket, TI113X_CARD_CONTROL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * The 145x series can also use this. They have an additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * ZV autodetect mode we don't use but don't actually need.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * FIXME: manual says its in func0 and func1 but disagrees with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * itself about this - do we need to force func0, if so we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * to know a lot more about socket pairings in pcmcia_socket than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * we do now.. uggh.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void ti1250_zoom_video(struct pcmcia_socket *sock, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ti_zoom_video(sock, onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) reg = config_readb(socket, TI1250_MULTIMEDIA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) reg |= TI1250_MMC_ZVOUTEN; /* ZV bus enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if(PCI_FUNC(socket->dev->devfn)==1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) shift = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if(onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) reg &= ~(1<<6); /* Clear select bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) reg |= shift<<6; /* Favour our socket */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) reg |= 1<<shift; /* Socket zoom video on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) reg &= ~(1<<6); /* Clear select bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) reg |= (1^shift)<<6; /* Favour other socket */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) reg &= ~(1<<shift); /* Socket zoon video off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) config_writeb(socket, TI1250_MULTIMEDIA_CTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void ti_set_zv(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if(socket->dev->vendor == PCI_VENDOR_ID_TI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) switch(socket->dev->device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* There may be more .. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case PCI_DEVICE_ID_TI_1220:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case PCI_DEVICE_ID_TI_1221:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case PCI_DEVICE_ID_TI_1225:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case PCI_DEVICE_ID_TI_4510:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) socket->socket.zoom_video = ti_zoom_video;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case PCI_DEVICE_ID_TI_1250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case PCI_DEVICE_ID_TI_1251A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case PCI_DEVICE_ID_TI_1251B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case PCI_DEVICE_ID_TI_1450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) socket->socket.zoom_video = ti1250_zoom_video;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Generic TI init - TI has an extension for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * INTCTL register that sets the PCI CSC interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * Make sure we set it correctly at open and init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * - override: disable the PCI CSC interrupt. This makes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * it possible to use the CSC interrupt to probe the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * ISA interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * - init: set the interrupt to match our PCI state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * This makes us correctly get PCI CSC interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int ti_init(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u8 new, reg = exca_readb(socket, I365_INTCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) new = reg & ~I365_INTR_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (socket->dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) new |= I365_INTR_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (new != reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) exca_writeb(socket, I365_INTCTL, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int ti_override(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u8 new, reg = exca_readb(socket, I365_INTCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) new = reg & ~I365_INTR_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (new != reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) exca_writeb(socket, I365_INTCTL, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ti_set_zv(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void ti113x_use_isa_irq(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int isa_irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u8 intctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 isa_irq_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!isa_probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* get a free isa int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) isa_irq_mask = yenta_probe_irq(socket, isa_interrupts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!isa_irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return; /* no useable isa irq found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* choose highest available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) for (; isa_irq_mask; isa_irq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) isa_irq_mask >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) socket->cb_irq = isa_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) exca_writeb(socket, I365_CSCINT, (isa_irq << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) intctl = exca_readb(socket, I365_INTCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) intctl &= ~(I365_INTR_ENA | I365_IRQ_MASK); /* CSC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) exca_writeb(socket, I365_INTCTL, intctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "Yenta TI113x: using isa irq %d for CardBus\n", isa_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int ti113x_override(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 cardctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) cardctl = config_readb(socket, TI113X_CARD_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) cardctl &= ~(TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_IREQ | TI113X_CCR_PCI_CSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (socket->dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cardctl |= TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_CSC | TI113X_CCR_PCI_IREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ti113x_use_isa_irq(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) config_writeb(socket, TI113X_CARD_CONTROL, cardctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ti_override(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* irqrouting for func0, probes PCI interrupt and ISA interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static void ti12xx_irqroute_func0(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 mfunc, mfunc_old, devctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u8 gpio3, gpio3_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int pci_irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mfunc = mfunc_old = config_readl(socket, TI122X_MFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) devctl = config_readb(socket, TI113X_DEVICE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_info(&socket->dev->dev, "TI: mfunc 0x%08x, devctl 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mfunc, devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* make sure PCI interrupts are enabled before probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ti_init(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* test PCI interrupts first. only try fixing if return value is 0! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pci_irq_status = yenta_probe_cb_irq(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (pci_irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * We're here which means PCI interrupts are _not_ delivered. try to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * find the right setting (all serial or parallel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "TI: probing PCI interrupt failed, trying to fix\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* for serial PCI make sure MFUNC3 is set to IRQSER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if ((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) switch (socket->dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case PCI_DEVICE_ID_TI_1250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case PCI_DEVICE_ID_TI_1251A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case PCI_DEVICE_ID_TI_1251B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case PCI_DEVICE_ID_TI_1450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case PCI_DEVICE_ID_TI_1451A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case PCI_DEVICE_ID_TI_4450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case PCI_DEVICE_ID_TI_4451:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* these chips have no IRQSER setting in MFUNC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mfunc = (mfunc & ~TI122X_MFUNC3_MASK) | TI122X_MFUNC3_IRQSER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* write down if changed, probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (mfunc != mfunc_old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) config_writel(socket, TI122X_MFUNC, mfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pci_irq_status = yenta_probe_cb_irq(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (pci_irq_status == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) "TI: all-serial interrupts ok\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mfunc_old = mfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* not working, back to old value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mfunc = mfunc_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) config_writel(socket, TI122X_MFUNC, mfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (pci_irq_status == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* serial PCI interrupts not working fall back to parallel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "TI: falling back to parallel PCI interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) devctl &= ~TI113X_DCR_IMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) devctl |= TI113X_DCR_IMODE_SERIAL; /* serial ISA could be right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) config_writeb(socket, TI113X_DEVICE_CONTROL, devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* parallel PCI interrupts: route INTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) switch (socket->dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case PCI_DEVICE_ID_TI_1250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case PCI_DEVICE_ID_TI_1251A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case PCI_DEVICE_ID_TI_1251B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case PCI_DEVICE_ID_TI_1450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* make sure GPIO3 is set to INTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) gpio3 = gpio3_old = config_readb(socket, TI1250_GPIO3_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) gpio3 &= ~TI1250_GPIO_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (gpio3 != gpio3_old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) gpio3 = gpio3_old = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mfunc = (mfunc & ~TI122X_MFUNC0_MASK) | TI122X_MFUNC0_INTA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (mfunc != mfunc_old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) config_writel(socket, TI122X_MFUNC, mfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* time to probe again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pci_irq_status = yenta_probe_cb_irq(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (pci_irq_status == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mfunc_old = mfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_info(&socket->dev->dev, "TI: parallel PCI interrupts ok\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* not working, back to old value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mfunc = mfunc_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) config_writel(socket, TI122X_MFUNC, mfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (gpio3 != gpio3_old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3_old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (pci_irq_status < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) socket->cb_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "Yenta TI: no PCI interrupts. Fish. Please report.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* changes the irq of func1 to match that of func0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int ti12xx_align_irqs(struct yenta_socket *socket, int *old_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct pci_dev *func0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* find func0 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) func0 = pci_get_slot(socket->dev->bus, socket->dev->devfn & ~0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!func0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (old_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) *old_irq = socket->cb_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) socket->cb_irq = socket->dev->irq = func0->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pci_dev_put(func0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * ties INTA and INTB together. also changes the devices irq to that of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * the function 0 device. call from func1 only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * returns 1 if INTRTIE changed, 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int ti12xx_tie_interrupts(struct yenta_socket *socket, int *old_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 sysctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (sysctl & TI122X_SCR_INTRTIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = ti12xx_align_irqs(socket, old_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* tie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) sysctl |= TI122X_SCR_INTRTIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) config_writel(socket, TI113X_SYSTEM_CONTROL, sysctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* undo what ti12xx_tie_interrupts() did */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void ti12xx_untie_interrupts(struct yenta_socket *socket, int old_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) sysctl &= ~TI122X_SCR_INTRTIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) config_writel(socket, TI113X_SYSTEM_CONTROL, sysctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) socket->cb_irq = socket->dev->irq = old_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * irqrouting for func1, plays with INTB routing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * only touches MFUNC for INTB routing. all other bits are taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * care of in func0 already.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void ti12xx_irqroute_func1(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 mfunc, mfunc_old, devctl, sysctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int pci_irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) mfunc = mfunc_old = config_readl(socket, TI122X_MFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) devctl = config_readb(socket, TI113X_DEVICE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dev_info(&socket->dev->dev, "TI: mfunc 0x%08x, devctl 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mfunc, devctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* if IRQs are configured as tied, align irq of func1 with func0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (sysctl & TI122X_SCR_INTRTIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ti12xx_align_irqs(socket, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* make sure PCI interrupts are enabled before probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ti_init(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* test PCI interrupts first. only try fixing if return value is 0! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) pci_irq_status = yenta_probe_cb_irq(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (pci_irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * We're here which means PCI interrupts are _not_ delivered. try to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * find the right setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "TI: probing PCI interrupt failed, trying to fix\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* if all serial: set INTRTIE, probe again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if ((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int old_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (ti12xx_tie_interrupts(socket, &old_irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pci_irq_status = yenta_probe_cb_irq(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (pci_irq_status == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) "TI: all-serial interrupts, tied ok\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ti12xx_untie_interrupts(socket, old_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* parallel PCI: route INTB, probe again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int old_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) switch (socket->dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case PCI_DEVICE_ID_TI_1250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* the 1250 has one pin for IRQSER/INTB depending on devctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case PCI_DEVICE_ID_TI_1251A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) case PCI_DEVICE_ID_TI_1251B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case PCI_DEVICE_ID_TI_1450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * those have a pin for IRQSER/INTB plus INTB in MFUNC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * we alread probed the shared pin, now go for MFUNC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) mfunc = (mfunc & ~TI122X_MFUNC0_MASK) | TI125X_MFUNC0_INTB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mfunc = (mfunc & ~TI122X_MFUNC1_MASK) | TI122X_MFUNC1_INTB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* write, probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (mfunc != mfunc_old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) config_writel(socket, TI122X_MFUNC, mfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) pci_irq_status = yenta_probe_cb_irq(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (pci_irq_status == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "TI: parallel PCI interrupts ok\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mfunc = mfunc_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) config_writel(socket, TI122X_MFUNC, mfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (pci_irq_status == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* still nothing: set INTRTIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (ti12xx_tie_interrupts(socket, &old_irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pci_irq_status = yenta_probe_cb_irq(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (pci_irq_status == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) "TI: parallel PCI interrupts, tied ok\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ti12xx_untie_interrupts(socket, old_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (pci_irq_status < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) socket->cb_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) "TI: no PCI interrupts. Fish. Please report.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Returns true value if the second slot of a two-slot controller is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int ti12xx_2nd_slot_empty(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct pci_dev *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct yenta_socket *slot2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) unsigned int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 sysctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* catch the two-slot controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) switch (socket->dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) case PCI_DEVICE_ID_TI_1220:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) case PCI_DEVICE_ID_TI_1221:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) case PCI_DEVICE_ID_TI_1225:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case PCI_DEVICE_ID_TI_1251A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case PCI_DEVICE_ID_TI_1251B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) case PCI_DEVICE_ID_TI_1420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) case PCI_DEVICE_ID_TI_1450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) case PCI_DEVICE_ID_TI_1451A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) case PCI_DEVICE_ID_TI_1520:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) case PCI_DEVICE_ID_TI_1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) case PCI_DEVICE_ID_TI_4520:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) case PCI_DEVICE_ID_TI_4450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) case PCI_DEVICE_ID_TI_4451:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * there are way more, but they need to be added in yenta_socket.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * and pci_ids.h first anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) case PCI_DEVICE_ID_TI_XX12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case PCI_DEVICE_ID_TI_X515:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case PCI_DEVICE_ID_TI_X420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case PCI_DEVICE_ID_TI_X620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) case PCI_DEVICE_ID_TI_XX21_XX11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case PCI_DEVICE_ID_TI_7410:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case PCI_DEVICE_ID_TI_7610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * those are either single or dual slot CB with additional functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * like 1394, smartcard reader, etc. check the TIEALL flag for them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * the TIEALL flag binds the IRQ of all functions together.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * we catch the single slot variants later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (sysctl & TIXX21_SCR_TIEALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* single-slot controllers have the 2nd slot empty always :) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* get other slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) devfn = socket->dev->devfn & ~0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) func = pci_get_slot(socket->dev->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) (socket->dev->devfn & 0x07) ? devfn : devfn | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (!func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * check that the device id of both slots match. this is needed for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * XX21 and the XX11 controller that share the same device id for single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * and dual slot controllers. return '2nd slot empty'. we already checked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * if the interrupt is tied to another function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (socket->dev->device != func->device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) slot2 = pci_get_drvdata(func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (!slot2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* check state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) yenta_get_status(&slot2->socket, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (state & SS_DETECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) pci_dev_put(func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * TI specifiy parts for the power hook.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * some TI's with some CB's produces interrupt storm on power on. it has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * seen with atheros wlan cards on TI1225 and TI1410. solution is simply to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * disable any CB interrupts during this time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int ti12xx_power_hook(struct pcmcia_socket *sock, int operation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) u32 mfunc, devctl, sysctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u8 gpio3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* only POWER_PRE and POWER_POST are interesting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if ((operation != HOOK_POWER_PRE) && (operation != HOOK_POWER_POST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) devctl = config_readb(socket, TI113X_DEVICE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) mfunc = config_readl(socket, TI122X_MFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * all serial/tied: only disable when modparm set. always doing it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * would mean a regression for working setups 'cos it disables the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * interrupts for both both slots on 2-slot controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * (and users of single slot controllers where it's save have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * live with setting the modparm, most don't have to anyway)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) (pwr_irqs_off || ti12xx_2nd_slot_empty(socket))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) switch (socket->dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) case PCI_DEVICE_ID_TI_1250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case PCI_DEVICE_ID_TI_1251A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case PCI_DEVICE_ID_TI_1251B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) case PCI_DEVICE_ID_TI_1450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case PCI_DEVICE_ID_TI_1451A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case PCI_DEVICE_ID_TI_4450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) case PCI_DEVICE_ID_TI_4451:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* these chips have no IRQSER setting in MFUNC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (operation == HOOK_POWER_PRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) mfunc = (mfunc & ~TI122X_MFUNC3_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) mfunc = (mfunc & ~TI122X_MFUNC3_MASK) | TI122X_MFUNC3_IRQSER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* do the job differently for func0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if ((PCI_FUNC(socket->dev->devfn) == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ((sysctl & TI122X_SCR_INTRTIE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) (pwr_irqs_off || ti12xx_2nd_slot_empty(socket)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* some bridges are different */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) switch (socket->dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) case PCI_DEVICE_ID_TI_1250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) case PCI_DEVICE_ID_TI_1251A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case PCI_DEVICE_ID_TI_1251B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) case PCI_DEVICE_ID_TI_1450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* those oldies use gpio3 for INTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) gpio3 = config_readb(socket, TI1250_GPIO3_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (operation == HOOK_POWER_PRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) gpio3 = (gpio3 & ~TI1250_GPIO_MODE_MASK) | 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) gpio3 &= ~TI1250_GPIO_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* all new bridges are the same */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (operation == HOOK_POWER_PRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) mfunc &= ~TI122X_MFUNC0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) mfunc |= TI122X_MFUNC0_INTA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) config_writel(socket, TI122X_MFUNC, mfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) switch (socket->dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case PCI_DEVICE_ID_TI_1251A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) case PCI_DEVICE_ID_TI_1251B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case PCI_DEVICE_ID_TI_1450:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* those have INTA elsewhere and INTB in MFUNC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (operation == HOOK_POWER_PRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) mfunc &= ~TI122X_MFUNC0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) mfunc |= TI125X_MFUNC0_INTB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) config_writel(socket, TI122X_MFUNC, mfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* all new bridges are the same */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (operation == HOOK_POWER_PRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) mfunc &= ~TI122X_MFUNC1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) mfunc |= TI122X_MFUNC1_INTB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) config_writel(socket, TI122X_MFUNC, mfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int ti12xx_override(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u32 val, val_orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* make sure that memory burst is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) val_orig = val = config_readl(socket, TI113X_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (disable_clkrun && PCI_FUNC(socket->dev->devfn) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev_info(&socket->dev->dev, "Disabling CLKRUN feature\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) val |= TI113X_SCR_KEEPCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (!(val & TI122X_SCR_MRBURSTUP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) "Enabling burst memory read transactions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) val |= TI122X_SCR_MRBURSTUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (val_orig != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) config_writel(socket, TI113X_SYSTEM_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Yenta expects controllers to use CSCINT to route
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * CSC interrupts to PCI rather than INTVAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) val = config_readb(socket, TI1250_DIAGNOSTIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dev_info(&socket->dev->dev, "Using %s to route CSC interrupts to PCI\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) (val & TI1250_DIAG_PCI_CSC) ? "CSCINT" : "INTVAL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev_info(&socket->dev->dev, "Routing CardBus interrupts to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) (val & TI1250_DIAG_PCI_IREQ) ? "PCI" : "ISA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* do irqrouting, depending on function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (PCI_FUNC(socket->dev->devfn) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ti12xx_irqroute_func0(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ti12xx_irqroute_func1(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* install power hook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) socket->socket.power_hook = ti12xx_power_hook;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return ti_override(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static int ti1250_override(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u8 old, diag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) old = config_readb(socket, TI1250_DIAGNOSTIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) diag = old & ~(TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (socket->cb_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) diag |= TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (diag != old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) "adjusting diagnostic: %02x -> %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) old, diag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) config_writeb(socket, TI1250_DIAGNOSTIC, diag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return ti12xx_override(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * EnE specific part. EnE bridges are register compatible with TI bridges but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * have their own test registers and more important their own little problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * Some fixup code to make everybody happy (TM).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #ifdef CONFIG_YENTA_ENE_TUNE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * set/clear various test bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * Defaults to clear the bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * - mask (u8) defines what bits to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * - bits (u8) is the values to change them to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * -> it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * current = (current & ~mask) | bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* pci ids of devices that wants to have the bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define DEVID(_vend,_dev,_subvend,_subdev,mask,bits) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .vendor = _vend, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .device = _dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .subvendor = _subvend, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .subdevice = _subdev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .driver_data = ((mask) << 8 | (bits)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static struct pci_device_id ene_tune_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* Echo Audio products based on motorola DSP56301 and DSP56361 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) DEVID(PCI_VENDOR_ID_MOTOROLA, 0x1801, 0xECC0, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ENE_TEST_C9_TLTENABLE | ENE_TEST_C9_PFENABLE, ENE_TEST_C9_TLTENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) DEVID(PCI_VENDOR_ID_MOTOROLA, 0x3410, 0xECC0, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ENE_TEST_C9_TLTENABLE | ENE_TEST_C9_PFENABLE, ENE_TEST_C9_TLTENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static void ene_tune_bridge(struct pcmcia_socket *sock, struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct pci_device_id *id = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u8 test_c9, old_c9, mask, bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) id = (struct pci_device_id *) pci_match_id(ene_tune_tbl, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) test_c9 = old_c9 = config_readb(socket, ENE_TEST_C9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) mask = (id->driver_data >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) bits = id->driver_data & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) test_c9 = (test_c9 & ~mask) | bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* default to clear TLTEnable bit, old behaviour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) test_c9 &= ~ENE_TEST_C9_TLTENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) "EnE: changing testregister 0xC9, %02x -> %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) old_c9, test_c9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) config_writeb(socket, ENE_TEST_C9, test_c9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static int ene_override(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* install tune_bridge() function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) socket->socket.tune_bridge = ene_tune_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return ti1250_override(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) # define ene_override ti1250_override
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #endif /* !CONFIG_YENTA_ENE_TUNE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #endif /* _LINUX_TI113X_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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