Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * tcic.h 1.13 1999/10/25 20:03:34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * The contents of this file are subject to the Mozilla Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Version 1.1 (the "License"); you may not use this file except in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * compliance with the License. You may obtain a copy of the License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * at http://www.mozilla.org/MPL/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Software distributed under the License is distributed on an "AS IS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * the License for the specific language governing rights and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * limitations under the License. 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * The initial developer of the original code is David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Alternatively, the contents of this file may be used under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * terms of the GNU General Public License version 2 (the "GPL"), in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * case the provisions of the GPL are applicable instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * above.  If you wish to allow the use of your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * only under the terms of the GPL and not to allow others to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * your version of this file under the MPL, indicate your decision by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * deleting the provisions above and replace them with the notice and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * other provisions required by the GPL.  If you do not delete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * provisions above, a recipient may use your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * under either the MPL or the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #ifndef _LINUX_TCIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define _LINUX_TCIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TCIC_BASE		0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* offsets of registers from TCIC_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TCIC_DATA		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TCIC_ADDR		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TCIC_SCTRL		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TCIC_SSTAT		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TCIC_MODE		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TCIC_PWR		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TCIC_EDC		0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TCIC_ICSR		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TCIC_IENA		0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TCIC_AUX		0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TCIC_SS_SHFT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TCIC_SS_MASK		0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* Flags for TCIC_ADDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TCIC_ADR2_REG		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define TCIC_ADR2_INDREG	0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TCIC_ADDR_REG		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TCIC_ADDR_SS_SHFT	(TCIC_SS_SHFT+16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TCIC_ADDR_SS_MASK	(TCIC_SS_MASK<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TCIC_ADDR_INDREG	0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define TCIC_ADDR_IO		0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define TCIC_ADDR_MASK		0x03ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* Flags for TCIC_SCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define TCIC_SCTRL_ENA		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define TCIC_SCTRL_INCMODE	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define TCIC_SCTRL_INCMODE_HOLD	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define TCIC_SCTRL_INCMODE_WORD	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define TCIC_SCTRL_INCMODE_REG	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TCIC_SCTRL_INCMODE_AUTO	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define TCIC_SCTRL_EDCSUM	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TCIC_SCTRL_RESET	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* Flags for TCIC_SSTAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define TCIC_SSTAT_6US		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define TCIC_SSTAT_10US		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define TCIC_SSTAT_PROGTIME	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define TCIC_SSTAT_LBAT1	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define TCIC_SSTAT_LBAT2	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define TCIC_SSTAT_RDY		0x20	/* Inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define TCIC_SSTAT_WP		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define TCIC_SSTAT_CD		0x80	/* Card detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* Flags for TCIC_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define TCIC_MODE_PGMMASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define TCIC_MODE_NORMAL	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define TCIC_MODE_PGMWR		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define TCIC_MODE_PGMRD		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define TCIC_MODE_PGMCE		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define TCIC_MODE_PGMDBW	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define TCIC_MODE_PGMWORD	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define TCIC_MODE_AUXSEL_MASK	0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* Registers accessed through TCIC_AUX, by setting TCIC_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TCIC_AUX_TCTL		(0<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TCIC_AUX_PCTL		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define TCIC_AUX_WCTL		(2<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define TCIC_AUX_EXTERN		(3<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define TCIC_AUX_PDATA		(4<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define TCIC_AUX_SYSCFG		(5<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define TCIC_AUX_ILOCK		(6<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define TCIC_AUX_TEST		(7<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Flags for TCIC_PWR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TCIC_PWR_VCC(sock)	(0x01<<(sock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TCIC_PWR_VCC_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TCIC_PWR_VPP(sock)	(0x08<<(sock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TCIC_PWR_VPP_MASK	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TCIC_PWR_CLIMENA	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TCIC_PWR_CLIMSTAT	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Flags for TCIC_ICSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TCIC_ICSR_CLEAR		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TCIC_ICSR_SET		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TCIC_ICSR_JAM		(TCIC_ICSR_CLEAR|TCIC_ICSR_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TCIC_ICSR_STOPCPU	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TCIC_ICSR_ILOCK		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TCIC_ICSR_PROGTIME	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TCIC_ICSR_ERR		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TCIC_ICSR_CDCHG		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TCIC_ICSR_IOCHK		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Flags for TCIC_IENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TCIC_IENA_CFG_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TCIC_IENA_CFG_OFF	0x00	/* disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TCIC_IENA_CFG_OD	0x01	/* active low, open drain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TCIC_IENA_CFG_LOW	0x02	/* active low, totem pole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TCIC_IENA_CFG_HIGH	0x03	/* active high, totem pole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TCIC_IENA_ILOCK		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TCIC_IENA_PROGTIME	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TCIC_IENA_ERR		0x20	/* overcurrent or iochk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TCIC_IENA_CDCHG		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Flags for TCIC_AUX_WCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TCIC_WAIT_COUNT_MASK	0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TCIC_WAIT_ASYNC		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TCIC_WAIT_SENSE		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TCIC_WAIT_SRC		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TCIC_WCTL_WR		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TCIC_WCTL_RD		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TCIC_WCTL_CE		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TCIC_WCTL_LLBAT1	0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TCIC_WCTL_LLBAT2	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TCIC_WCTL_LRDY		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TCIC_WCTL_LWP		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TCIC_WCTL_LCD		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Flags for TCIC_AUX_SYSCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TCIC_SYSCFG_IRQ_MASK	0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TCIC_SYSCFG_MCSFULL	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TCIC_SYSCFG_IO1723	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TCIC_SYSCFG_MCSXB	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TCIC_SYSCFG_ICSXB	0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TCIC_SYSCFG_NOPDN	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TCIC_SYSCFG_MPSEL_SHFT	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TCIC_SYSCFG_MPSEL_MASK	0x0e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TCIC_SYSCFG_MPSENSE	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TCIC_SYSCFG_AUTOBUSY	0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TCIC_SYSCFG_ACC		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TCIC_ILOCK_OUT		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TCIC_ILOCK_SENSE	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TCIC_ILOCK_CRESET	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TCIC_ILOCK_CRESENA	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TCIC_ILOCK_CWAIT	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TCIC_ILOCK_CWAITSNS	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TCIC_ILOCK_HOLD_MASK	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TCIC_ILOCK_HOLD_CCLK	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TCIC_ILOCKTEST_ID_SH	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TCIC_ILOCKTEST_ID_MASK	0x7f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TCIC_ILOCKTEST_MCIC_1	0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TCIC_ID_DB86082		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TCIC_ID_DB86082A	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TCIC_ID_DB86084		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TCIC_ID_DB86084A	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TCIC_ID_DB86072		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TCIC_ID_DB86184		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TCIC_ID_DB86082B	0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TCIC_TEST_DIAG		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  * Indirectly addressed registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TCIC_SCF1(sock)	((sock)<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TCIC_SCF2(sock) (((sock)<<3)+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Flags for SCF1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TCIC_SCF1_IRQ_MASK	0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TCIC_SCF1_IRQ_OFF	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TCIC_SCF1_IRQOC		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TCIC_SCF1_PCVT		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TCIC_SCF1_IRDY		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TCIC_SCF1_ATA		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TCIC_SCF1_DMA_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TCIC_SCF1_DMA_MASK	0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TCIC_SCF1_DMA_OFF	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TCIC_SCF1_DREQ2		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TCIC_SCF1_IOSTS		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TCIC_SCF1_SPKR		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TCIC_SCF1_FINPACK	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TCIC_SCF1_DELWR		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TCIC_SCF1_HD7IDE	0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Flags for SCF2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TCIC_SCF2_RI		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TCIC_SCF2_IDBR		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TCIC_SCF2_MDBR		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TCIC_SCF2_MLBAT1	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TCIC_SCF2_MLBAT2	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TCIC_SCF2_MRDY		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TCIC_SCF2_MWP		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TCIC_SCF2_MCD		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TCIC_SCF2_MALL		0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Indirect addresses for memory window registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TCIC_MWIN(sock,map)	(0x100+(((map)+((sock)<<2))<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TCIC_MBASE_X		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TCIC_MMAP_X		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TCIC_MCTL_X		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TCIC_MBASE_4K_BIT	0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TCIC_MBASE_HA_SHFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TCIC_MBASE_HA_MASK	0x0fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TCIC_MMAP_REG		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TCIC_MMAP_CA_SHFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TCIC_MMAP_CA_MASK	0x3fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TCIC_MCTL_WSCNT_MASK	0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TCIC_MCTL_WCLK		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TCIC_MCTL_WCLK_CCLK	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TCIC_MCTL_WCLK_BCLK	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TCIC_MCTL_QUIET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TCIC_MCTL_WP		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TCIC_MCTL_ACC		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TCIC_MCTL_KE		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TCIC_MCTL_EDC		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TCIC_MCTL_B8		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TCIC_MCTL_SS_SHFT	TCIC_SS_SHFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TCIC_MCTL_SS_MASK	TCIC_SS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TCIC_MCTL_ENA		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Indirect addresses for I/O window registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TCIC_IWIN(sock,map)	(0x200+(((map)+((sock)<<1))<<2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TCIC_IBASE_X		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TCIC_ICTL_X		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TCIC_ICTL_WSCNT_MASK	TCIC_MCTL_WSCNT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TCIC_ICTL_QUIET		TCIC_MCTL_QUIET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TCIC_ICTL_1K		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TCIC_ICTL_PASS16	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define TCIC_ICTL_ACC		TCIC_MCTL_ACC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TCIC_ICTL_TINY		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TCIC_ICTL_B16		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TCIC_ICTL_B8		TCIC_MCTL_B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TCIC_ICTL_BW_MASK	(TCIC_ICTL_B16|TCIC_ICTL_B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TCIC_ICTL_BW_DYN	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TCIC_ICTL_BW_8		TCIC_ICTL_B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TCIC_ICTL_BW_16		TCIC_ICTL_B16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TCIC_ICTL_BW_ATA	(TCIC_ICTL_B16|TCIC_ICTL_B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TCIC_ICTL_SS_SHFT	TCIC_SS_SHFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TCIC_ICTL_SS_MASK	TCIC_SS_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TCIC_ICTL_ENA		TCIC_MCTL_ENA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #endif /* _LINUX_TCIC_H */