Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/drivers/pcmcia/soc_common.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This file contains definitions for the PCMCIA support code common to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * integrated SOCs like the SA-11x0 and PXA2xx microprocessors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef _ASM_ARCH_PCMCIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define _ASM_ARCH_PCMCIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* include the world */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <pcmcia/ss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <pcmcia/cistpl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) struct device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) struct gpio_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) struct pcmcia_low_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) struct regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct soc_pcmcia_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct regulator	*reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	bool			on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * This structure encapsulates per-socket state which we might need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * use when responding to a Card Services query of some kind.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) struct soc_pcmcia_socket {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct pcmcia_socket	socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	 * Info from low level handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	unsigned int		nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	 * Core PCMCIA state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	const struct pcmcia_low_level *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned int		status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	socket_state_t		cs_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned short		spd_io[MAX_IO_WIN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned short		spd_mem[MAX_WIN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned short		spd_attr[MAX_WIN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct resource		res_skt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct resource		res_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct resource		res_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct resource		res_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	void __iomem		*virt_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		int		gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		struct gpio_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		unsigned int	irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		const char	*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	} stat[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SOC_STAT_CD		0	/* Card detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SOC_STAT_BVD1		1	/* BATDEAD / IOSTSCHG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SOC_STAT_BVD2		2	/* BATWARN / IOSPKR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SOC_STAT_RDY		3	/* Ready / Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SOC_STAT_VS1		4	/* Voltage sense 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SOC_STAT_VS2		5	/* Voltage sense 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct gpio_desc	*gpio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct gpio_desc	*gpio_bus_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct soc_pcmcia_regulator vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct soc_pcmcia_regulator vpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	unsigned int		irq_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct notifier_block	cpufreq_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct timer_list	poll_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct list_head	node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	void *driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) struct skt_dev_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	int nskt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct soc_pcmcia_socket skt[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) struct pcmcia_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)   unsigned detect: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)             ready: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)              bvd1: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)              bvd2: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)            wrprot: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)             vs_3v: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)             vs_Xv: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct pcmcia_low_level {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct module *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* first socket in system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	int first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* nr of sockets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int (*hw_init)(struct soc_pcmcia_socket *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	void (*hw_shutdown)(struct soc_pcmcia_socket *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	void (*socket_state)(struct soc_pcmcia_socket *, struct pcmcia_state *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int (*configure_socket)(struct soc_pcmcia_socket *, const socket_state_t *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * Enable card status IRQs on (re-)initialisation.  This can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 * be called at initialisation, power management event, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 * pcmcia event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	void (*socket_init)(struct soc_pcmcia_socket *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 * Disable card status IRQs and PCMCIA bus on suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	void (*socket_suspend)(struct soc_pcmcia_socket *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 * Hardware specific timing routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 * If provided, the get_timing routine overrides the SOC default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	unsigned int (*get_timing)(struct soc_pcmcia_socket *, unsigned int, unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int (*set_timing)(struct soc_pcmcia_socket *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	int (*show_timing)(struct soc_pcmcia_socket *, char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * CPUFREQ support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	int (*frequency_change)(struct soc_pcmcia_socket *, unsigned long, struct cpufreq_freqs *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct soc_pcmcia_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	unsigned short io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	unsigned short mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	unsigned short attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) extern void soc_common_pcmcia_get_timing(struct soc_pcmcia_socket *, struct soc_pcmcia_timing *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void soc_pcmcia_init_one(struct soc_pcmcia_socket *skt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	const struct pcmcia_low_level *ops, struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void soc_pcmcia_remove_one(struct soc_pcmcia_socket *skt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int soc_pcmcia_add_one(struct soc_pcmcia_socket *skt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int soc_pcmcia_request_gpiods(struct soc_pcmcia_socket *skt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void soc_common_cf_socket_state(struct soc_pcmcia_socket *skt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct pcmcia_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int soc_pcmcia_regulator_set(struct soc_pcmcia_socket *skt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct soc_pcmcia_regulator *r, int v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #ifdef CONFIG_PCMCIA_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) extern void soc_pcmcia_debug(struct soc_pcmcia_socket *skt, const char *func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			     int lvl, const char *fmt, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define debug(skt, lvl, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	soc_pcmcia_debug(skt, __func__, lvl, fmt , ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define debug(skt, lvl, fmt, arg...) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  * The PC Card Standard, Release 7, section 4.13.4, says that twIORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  * has a minimum value of 165ns. Section 4.13.5 says that twIOWR has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  * a minimum value of 165ns, as well. Section 4.7.2 (describing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  * common and attribute memory write timing) says that twWE has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  * minimum value of 150ns for a 250ns cycle time (for 5V operation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  * see section 4.7.4), or 300ns for a 600ns cycle time (for 3.3V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  * operation, also section 4.7.4). Section 4.7.3 says that taOE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  * has a maximum value of 150ns for a 300ns cycle time (for 5V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * operation), or 300ns for a 600ns cycle time (for 3.3V operation).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  * When configuring memory maps, Card Services appears to adopt the policy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  * that a memory access time of "0" means "use the default." The default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * PCMCIA I/O command width time is 165ns. The default PCMCIA 5V attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * and memory command width time is 150ns; the PCMCIA 3.3V attribute and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * memory command width time is 300ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SOC_PCMCIA_IO_ACCESS		(165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SOC_PCMCIA_5V_MEM_ACCESS	(150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SOC_PCMCIA_3V_MEM_ACCESS	(300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SOC_PCMCIA_ATTR_MEM_ACCESS	(300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * The socket driver actually works nicely in interrupt-driven form,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * so the (relatively infrequent) polling is "just to be sure."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SOC_PCMCIA_POLL_PERIOD    (2*HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* I/O pins replacing memory pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * These signals change meaning when going from memory-only to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * memory-or-I/O interface:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define iostschg bvd1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define iospkr   bvd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #endif