^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*======================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Device driver for the PCMCIA control functionality of StrongARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) SA-1100 microprocessors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) The contents of this file are subject to the Mozilla Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) License Version 1.1 (the "License"); you may not use this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) except in compliance with the License. You may obtain a copy of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) the License at http://www.mozilla.org/MPL/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Software distributed under the License is distributed on an "AS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) implied. See the License for the specific language governing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) rights and limitations under the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) The initial developer of the original code is John G. Dorsey
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) <john+@cs.cmu.edu>. Portions created by John G. Dorsey are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Copyright (C) 1999 John G. Dorsey. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Alternatively, the contents of this file may be used under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) terms of the GNU Public License version 2 (the "GPL"), in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) case the provisions of the GPL are applicable instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) above. If you wish to allow the use of your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) only under the terms of the GPL and not to allow others to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) your version of this file under the MPL, indicate your decision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) by deleting the provisions above and replace them with the notice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) and other provisions required by the GPL. If you do not delete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) the provisions above, a recipient may use your version of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) file under either the MPL or the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ======================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #if !defined(_PCMCIA_SA1100_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) # define _PCMCIA_SA1100_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* SA-1100 PCMCIA Memory and I/O timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * The SA-1110 Developer's Manual, section 10.2.5, says the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * "To calculate the recommended BS_xx value for each address space:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * divide the command width time (the greater of twIOWR and twIORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * or the greater of twWE and twOE) by processor cycle time; divide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * by 2; divide again by 3 (number of BCLK's per command assertion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * round up to the next whole number; and subtract 1."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* MECR: Expansion Memory Configuration Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * (SA-1100 Developers Manual, p.10-13; SA-1110 Developers Manual, p.10-24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * MECR layout is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * FAST1 BSM1<4:0> BSA1<4:0> BSIO1<4:0> FAST0 BSM0<4:0> BSA0<4:0> BSIO0<4:0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * (This layout is actually true only for the SA-1110; the FASTn bits are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * reserved on the SA-1100.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MECR_SOCKET_0_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MECR_SOCKET_1_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MECR_BS_MASK (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MECR_FAST_MODE_MASK (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MECR_BSIO_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MECR_BSA_SHIFT (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MECR_BSM_SHIFT (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MECR_FAST_SHIFT (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MECR_SET(mecr, sock, shift, mask, bs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ((mecr)=((mecr)&~(((mask)<<(shift))<<\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT)))|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (((bs)<<(shift))<<((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MECR_GET(mecr, sock, shift, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ((((mecr)>>(((sock)==0)?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT))>>\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) (shift))&(mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MECR_BSIO_SET(mecr, sock, bs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MECR_SET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK, (bs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MECR_BSIO_GET(mecr, sock) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MECR_GET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MECR_BSA_SET(mecr, sock, bs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MECR_SET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK, (bs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MECR_BSA_GET(mecr, sock) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MECR_GET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MECR_BSM_SET(mecr, sock, bs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MECR_SET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK, (bs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MECR_BSM_GET(mecr, sock) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MECR_GET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MECR_FAST_SET(mecr, sock, fast) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MECR_SET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK, (fast))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MECR_FAST_GET(mecr, sock) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MECR_GET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* This function implements the BS value calculation for setting the MECR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * using integer arithmetic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline unsigned int sa1100_pcmcia_mecr_bs(unsigned int pcmcia_cycle_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int cpu_clock_khz){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int t = ((pcmcia_cycle_ns * cpu_clock_khz) / 6) - 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return (t / 1000000) + (((t % 1000000) == 0) ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* This function returns the (approximate) command assertion period, in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * nanoseconds, for a given CPU clock frequency and MECR BS value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline unsigned int sa1100_pcmcia_cmd_time(unsigned int cpu_clock_khz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int pcmcia_mecr_bs){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return (((10000000 * 2) / cpu_clock_khz) * (3 * (pcmcia_mecr_bs + 1))) / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int sa11xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void sa11xx_drv_pcmcia_ops(struct pcmcia_low_level *ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) extern int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif /* !defined(_PCMCIA_SA1100_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags