^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*======================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Device driver for the PCMCIA control functionality of StrongARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) SA-1100 microprocessors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) The contents of this file are subject to the Mozilla Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) License Version 1.1 (the "License"); you may not use this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) except in compliance with the License. You may obtain a copy of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) the License at http://www.mozilla.org/MPL/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Software distributed under the License is distributed on an "AS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) implied. See the License for the specific language governing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) rights and limitations under the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) The initial developer of the original code is John G. Dorsey
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) <john+@cs.cmu.edu>. Portions created by John G. Dorsey are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Copyright (C) 1999 John G. Dorsey. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Alternatively, the contents of this file may be used under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) terms of the GNU Public License version 2 (the "GPL"), in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) case the provisions of the GPL are applicable instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) above. If you wish to allow the use of your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) only under the terms of the GPL and not to allow others to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) your version of this file under the MPL, indicate your decision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) by deleting the provisions above and replace them with the notice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) and other provisions required by the GPL. If you do not delete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) the provisions above, a recipient may use your version of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) file under either the MPL or the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ======================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "soc_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "sa11xx_base.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * sa1100_pcmcia_default_mecr_timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Calculate MECR clock wait states for given CPU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * speed and command wait state. This function can be over-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * written by a board specific version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * The default is to simply calculate the BS values as specified in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * the INTEL SA1100 development manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * "Expansion Memory (PCMCIA) Configuration Register (MECR)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * that's section 10.2.5 in _my_ version of the manual ;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) sa1100_pcmcia_default_mecr_timing(struct soc_pcmcia_socket *skt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int cpu_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int cmd_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return sa1100_pcmcia_mecr_bs(cmd_time, cpu_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* sa1100_pcmcia_set_mecr()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * ^^^^^^^^^^^^^^^^^^^^^^^^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * set MECR value for socket <sock> based on this sockets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * io, mem and attribute space access speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Call board specific BS value calculation to allow boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * to tweak the BS values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) sa1100_pcmcia_set_mecr(struct soc_pcmcia_socket *skt, unsigned int cpu_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct soc_pcmcia_timing timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 mecr, old_mecr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int bs_io, bs_mem, bs_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) soc_common_pcmcia_get_timing(skt, &timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) old_mecr = mecr = MECR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MECR_FAST_SET(mecr, skt->nr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MECR_BSIO_SET(mecr, skt->nr, bs_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MECR_BSA_SET(mecr, skt->nr, bs_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MECR_BSM_SET(mecr, skt->nr, bs_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (old_mecr != mecr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MECR = mecr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) debug(skt, 2, "FAST %X BSM %X BSA %X BSIO %X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MECR_FAST_GET(mecr, skt->nr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MECR_BSM_GET(mecr, skt->nr), MECR_BSA_GET(mecr, skt->nr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MECR_BSIO_GET(mecr, skt->nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sa1100_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct cpufreq_freqs *freqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case CPUFREQ_PRECHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (freqs->new > freqs->old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) sa1100_pcmcia_set_mecr(skt, freqs->new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case CPUFREQ_POSTCHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (freqs->new < freqs->old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) sa1100_pcmcia_set_mecr(skt, freqs->new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) sa1100_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long clk = clk_get_rate(skt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return sa1100_pcmcia_set_mecr(skt, clk / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) sa1100_pcmcia_show_timing(struct soc_pcmcia_socket *skt, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct soc_pcmcia_timing timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int clock = clk_get_rate(skt->clk) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long mecr = MECR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) char *p = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) soc_common_pcmcia_get_timing(skt, &timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) p+=sprintf(p, "I/O : %uns (%uns)\n", timing.io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) sa1100_pcmcia_cmd_time(clock, MECR_BSIO_GET(mecr, skt->nr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) p+=sprintf(p, "attribute: %uns (%uns)\n", timing.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) sa1100_pcmcia_cmd_time(clock, MECR_BSA_GET(mecr, skt->nr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) p+=sprintf(p, "common : %uns (%uns)\n", timing.mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) sa1100_pcmcia_cmd_time(clock, MECR_BSM_GET(mecr, skt->nr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return p - buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const char *skt_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "PCMCIA socket 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "PCMCIA socket 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SKT_DEV_INFO_SIZE(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int sa11xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) skt->res_skt.start = _PCMCIA(skt->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) skt->res_skt.name = skt_names[skt->nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) skt->res_skt.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) skt->res_io.start = _PCMCIAIO(skt->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) skt->res_io.name = "io";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) skt->res_mem.start = _PCMCIAMem(skt->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) skt->res_mem.name = "memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) skt->res_mem.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) skt->res_attr.start = _PCMCIAAttr(skt->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) skt->res_attr.name = "attribute";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) skt->res_attr.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return soc_pcmcia_add_one(skt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) EXPORT_SYMBOL(sa11xx_drv_pcmcia_add_one);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void sa11xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * set default MECR calculation if the board specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * code did not specify one...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!ops->get_timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ops->get_timing = sa1100_pcmcia_default_mecr_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Provide our SA11x0 specific timing routines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ops->set_timing = sa1100_pcmcia_set_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ops->show_timing = sa1100_pcmcia_show_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ops->frequency_change = sa1100_pcmcia_frequency_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) EXPORT_SYMBOL(sa11xx_drv_pcmcia_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int first, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct skt_dev_info *sinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct soc_pcmcia_socket *skt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) sa11xx_drv_pcmcia_ops(ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) sinfo = devm_kzalloc(dev, SKT_DEV_INFO_SIZE(nr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) sinfo->nskt = nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Initialize processor specific parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) for (i = 0; i < nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) skt = &sinfo->skt[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) skt->nr = first + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) skt->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) soc_pcmcia_init_one(skt, ops, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = sa11xx_drv_pcmcia_add_one(skt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) soc_pcmcia_remove_one(&sinfo->skt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_set_drvdata(dev, sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) EXPORT_SYMBOL(sa11xx_drv_pcmcia_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_AUTHOR("John Dorsey <john+@cs.cmu.edu>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MODULE_DESCRIPTION("Linux PCMCIA Card Services: SA-11xx core socket driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MODULE_LICENSE("Dual MPL/GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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