Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * ricoh.h 1.9 1999/10/25 20:03:34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * The contents of this file are subject to the Mozilla Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Version 1.1 (the "License"); you may not use this file except in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * compliance with the License. You may obtain a copy of the License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * at http://www.mozilla.org/MPL/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Software distributed under the License is distributed on an "AS IS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * the License for the specific language governing rights and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * limitations under the License. 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * The initial developer of the original code is David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Alternatively, the contents of this file may be used under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * terms of the GNU General Public License version 2 (the "GPL"), in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * case the provisions of the GPL are applicable instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * above.  If you wish to allow the use of your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * only under the terms of the GPL and not to allow others to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * your version of this file under the MPL, indicate your decision by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * deleting the provisions above and replace them with the notice and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * other provisions required by the GPL.  If you do not delete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * provisions above, a recipient may use your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * under either the MPL or the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #ifndef _LINUX_RICOH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define _LINUX_RICOH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RF5C_MODE_CTL		0x1f	/* Mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define RF5C_PWR_CTL		0x2f	/* Mixed voltage control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RF5C_CHIP_ID		0x3a	/* Chip identification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define RF5C_MODE_CTL_3		0x3b	/* Mode control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* I/O window address offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define RF5C_IO_OFF(w)		(0x36+((w)<<1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* Flags for RF5C_MODE_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RF5C_MODE_ATA		0x01	/* ATA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RF5C_MODE_LED_ENA	0x02	/* IRQ 12 is LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define RF5C_MODE_CA21		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define RF5C_MODE_CA22		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define RF5C_MODE_CA23		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define RF5C_MODE_CA24		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define RF5C_MODE_CA25		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define RF5C_MODE_3STATE_BIT7	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* Flags for RF5C_PWR_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define RF5C_PWR_VCC_3V		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define RF5C_PWR_IREQ_HIGH	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define RF5C_PWR_INPACK_ENA	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define RF5C_PWR_5V_DET		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define RF5C_PWR_TC_SEL		0x10	/* Terminal Count: irq 11 or 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define RF5C_PWR_DREQ_LOW	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define RF5C_PWR_DREQ_OFF	0x00	/* DREQ steering control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define RF5C_PWR_DREQ_INPACK	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define RF5C_PWR_DREQ_SPKR	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define RF5C_PWR_DREQ_IOIS16	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* Values for RF5C_CHIP_ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define RF5C_CHIP_RF5C296	0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define RF5C_CHIP_RF5C396	0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* Flags for RF5C_MODE_CTL_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define RF5C_MCTL3_DISABLE	0x01	/* Disable PCMCIA interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define RF5C_MCTL3_DMA_ENA	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* Register definitions for Ricoh PCI-to-CardBus bridges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* Extra bits in CB_BRIDGE_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define RL5C46X_BCR_3E0_ENA		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define RL5C46X_BCR_3E2_ENA		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* Bridge Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define RL5C4XX_CONFIG			0x80	/* 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define  RL5C4XX_CONFIG_IO_1_MODE	0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define  RL5C4XX_CONFIG_IO_0_MODE	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define  RL5C4XX_CONFIG_PREFETCH	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* Misc Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define RL5C4XX_MISC			0x0082	/* 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define  RL5C4XX_MISC_HW_SUSPEND_ENA	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define  RL5C4XX_MISC_VCCEN_POL		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define  RL5C4XX_MISC_VPPEN_POL		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define  RL5C46X_MISC_SUSPEND		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define  RL5C46X_MISC_PWR_SAVE_2	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define  RL5C46X_MISC_IFACE_BUSY	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define  RL5C46X_MISC_B_LOCK		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define  RL5C46X_MISC_A_LOCK		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define  RL5C46X_MISC_PCI_LOCK		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define  RL5C47X_MISC_IFACE_BUSY	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define  RL5C47X_MISC_PCI_INT_MASK	0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define  RL5C47X_MISC_PCI_INT_DIS	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define  RL5C47X_MISC_SUBSYS_WR		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define  RL5C47X_MISC_SRIRQ_ENA		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define  RL5C47X_MISC_5V_DISABLE	0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define  RL5C47X_MISC_LED_POL		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* 16-bit Interface Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RL5C4XX_16BIT_CTL		0x0084	/* 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define  RL5C4XX_16CTL_IO_TIMING	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define  RL5C4XX_16CTL_MEM_TIMING	0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define  RL5C46X_16CTL_LEVEL_1		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define  RL5C46X_16CTL_LEVEL_2		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* 16-bit IO and memory timing registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RL5C4XX_16BIT_IO_0		0x0088	/* 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RL5C4XX_16BIT_MEM_0		0x008a	/* 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define  RL5C4XX_SETUP_MASK		0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define  RL5C4XX_SETUP_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define  RL5C4XX_CMD_MASK		0x01f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define  RL5C4XX_CMD_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define  RL5C4XX_HOLD_MASK		0x1c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define  RL5C4XX_HOLD_SHIFT		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define  RL5C4XX_MISC_CONTROL           0x2F /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define  RL5C4XX_ZV_ENABLE              0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Misc Control 3 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RL5C4XX_MISC3			0x00A2 /* 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define  RL5C47X_MISC3_CB_CLKRUN_DIS	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #ifdef __YENTA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define rl_misc(socket)		((socket)->private[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define rl_ctl(socket)		((socket)->private[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define rl_io(socket)		((socket)->private[2])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define rl_mem(socket)		((socket)->private[3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define rl_config(socket)	((socket)->private[4])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void ricoh_zoom_video(struct pcmcia_socket *sock, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)         u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)         reg = config_readb(socket, RL5C4XX_MISC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)         if (onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)                 /* Zoom zoom, we will all go together, zoom zoom, zoom zoom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)                 reg |=  RL5C4XX_ZV_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)         else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)                 reg &= ~RL5C4XX_ZV_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)         config_writeb(socket, RL5C4XX_MISC_CONTROL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void ricoh_set_zv(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)         if(socket->dev->vendor == PCI_VENDOR_ID_RICOH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)         {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)                 switch(socket->dev->device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)                 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)                         /* There may be more .. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		case  PCI_DEVICE_ID_RICOH_RL5C478:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			socket->socket.zoom_video = ricoh_zoom_video;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			break;  
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)                 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)         }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void ricoh_set_clkrun(struct yenta_socket *socket, bool quiet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u16 misc3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 * RL5C475II likely has this setting, too, however no datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	 * is publicly available for this chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (socket->dev->device != PCI_DEVICE_ID_RICOH_RL5C476 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	    socket->dev->device != PCI_DEVICE_ID_RICOH_RL5C478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (socket->dev->revision < 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	misc3 = config_readw(socket, RL5C4XX_MISC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (misc3 & RL5C47X_MISC3_CB_CLKRUN_DIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		if (!quiet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			dev_dbg(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				"CLKRUN feature already disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	} else if (disable_clkrun) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		if (!quiet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				 "Disabling CLKRUN feature\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		misc3 |= RL5C47X_MISC3_CB_CLKRUN_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		config_writew(socket, RL5C4XX_MISC3, misc3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void ricoh_save_state(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	rl_misc(socket) = config_readw(socket, RL5C4XX_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	rl_ctl(socket) = config_readw(socket, RL5C4XX_16BIT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	rl_io(socket) = config_readw(socket, RL5C4XX_16BIT_IO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	rl_mem(socket) = config_readw(socket, RL5C4XX_16BIT_MEM_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	rl_config(socket) = config_readw(socket, RL5C4XX_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void ricoh_restore_state(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	config_writew(socket, RL5C4XX_MISC, rl_misc(socket));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	config_writew(socket, RL5C4XX_16BIT_CTL, rl_ctl(socket));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	config_writew(socket, RL5C4XX_16BIT_IO_0, rl_io(socket));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	config_writew(socket, RL5C4XX_16BIT_MEM_0, rl_mem(socket));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	config_writew(socket, RL5C4XX_CONFIG, rl_config(socket));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	ricoh_set_clkrun(socket, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * Magic Ricoh initialization code..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int ricoh_override(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	u16 config, ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	config = config_readw(socket, RL5C4XX_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* Set the default timings, don't trust the original values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	ctl = RL5C4XX_16CTL_IO_TIMING | RL5C4XX_16CTL_MEM_TIMING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if(socket->dev->device < PCI_DEVICE_ID_RICOH_RL5C475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		ctl |= RL5C46X_16CTL_LEVEL_1 | RL5C46X_16CTL_LEVEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		config |= RL5C4XX_CONFIG_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	config_writew(socket, RL5C4XX_16BIT_CTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	config_writew(socket, RL5C4XX_CONFIG, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ricoh_set_zv(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ricoh_set_clkrun(socket, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #endif /* CONFIG_CARDBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #endif /* _LINUX_RICOH_H */