Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*======================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)   Device driver for the PCMCIA control functionality of PXA2xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)   microprocessors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)     (c) Ian Molton (spyro@f2s.com) 2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)     (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)     derived from sa11xx_base.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)      Portions created by John G. Dorsey are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)      Copyright (C) 1999 John G. Dorsey.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)   ======================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <mach/smemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <mach/pxa2xx-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <pcmcia/ss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <pcmcia/cistpl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include "soc_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include "pxa2xx_base.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * Personal Computer Memory Card International Association (PCMCIA) sockets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]             */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]         */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]           */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]       */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]           */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]       */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define _PCMCIA(Nb)			/* PCMCIA [0..1]                   */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			(0x20000000 + (Nb) * PCMCIASp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define _PCMCIAIO(Nb)	_PCMCIA(Nb)	/* PCMCIA I/O [0..1]               */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]         */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			(_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]            */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			(_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define _PCMCIA0	_PCMCIA(0)	/* PCMCIA 0                        */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define _PCMCIA0IO	_PCMCIAIO(0)	/* PCMCIA 0 I/O                    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define _PCMCIA0Attr	_PCMCIAAttr(0)	/* PCMCIA 0 Attribute              */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define _PCMCIA0Mem	_PCMCIAMem(0)	/* PCMCIA 0 Memory                 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define _PCMCIA1	_PCMCIA(1)	/* PCMCIA 1                        */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define _PCMCIA1IO	_PCMCIAIO(1)	/* PCMCIA 1 I/O                    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define _PCMCIA1Attr	_PCMCIAAttr(1)	/* PCMCIA 1 Attribute              */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define _PCMCIA1Mem	_PCMCIAMem(1)	/* PCMCIA 1 Memory                 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MCXX_SETUP_MASK     (0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MCXX_ASST_MASK      (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MCXX_HOLD_MASK      (0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MCXX_SETUP_SHIFT    (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MCXX_ASST_SHIFT     (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define MCXX_HOLD_SHIFT     (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 				     u_int mem_clk_10khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				     u_int mem_clk_10khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				      u_int mem_clk_10khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* This function returns the (approximate) command assertion period, in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 					   u_int pcmcia_mcxx_asst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	val = ((pxa2xx_mcxx_setup(speed, clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		| ((pxa2xx_mcxx_asst(speed, clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		| ((pxa2xx_mcxx_hold(speed, clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	__raw_writel(val, MCMEM(sock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	val = ((pxa2xx_mcxx_setup(speed, clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		| ((pxa2xx_mcxx_asst(speed, clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		| ((pxa2xx_mcxx_hold(speed, clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	__raw_writel(val, MCIO(sock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	val = ((pxa2xx_mcxx_setup(speed, clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		| ((pxa2xx_mcxx_asst(speed, clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		| ((pxa2xx_mcxx_hold(speed, clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	__raw_writel(val, MCATT(sock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct soc_pcmcia_timing timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	int sock = skt->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	soc_common_pcmcia_get_timing(skt, &timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	unsigned long clk = clk_get_rate(skt->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			       unsigned long val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			       struct cpufreq_freqs *freqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	case CPUFREQ_PRECHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		if (freqs->new > freqs->old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			       "pre-updating\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			       freqs->new / 1000, (freqs->new / 100) % 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			       freqs->old / 1000, (freqs->old / 100) % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			pxa2xx_pcmcia_set_timing(skt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	case CPUFREQ_POSTCHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		if (freqs->new < freqs->old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			       "post-updating\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			       freqs->new / 1000, (freqs->new / 100) % 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			       freqs->old / 1000, (freqs->old / 100) % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			pxa2xx_pcmcia_set_timing(skt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void pxa2xx_configure_sockets(struct device *dev, struct pcmcia_low_level *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 * We have at least one socket, so set MECR:CIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * (Card Is There)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	uint32_t mecr = MECR_CIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/* Set MECR:NOS (Number Of Sockets) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if ((ops->first + ops->nr) > 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	    machine_is_viper() || machine_is_arcom_zeus())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		mecr |= MECR_NOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	__raw_writel(mecr, MECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) EXPORT_SYMBOL(pxa2xx_configure_sockets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const char *skt_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	"PCMCIA socket 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	"PCMCIA socket 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SKT_DEV_INFO_SIZE(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	(sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	skt->res_skt.start = _PCMCIA(skt->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	skt->res_skt.name = skt_names[skt->nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	skt->res_skt.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	skt->res_io.start = _PCMCIAIO(skt->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	skt->res_io.name = "io";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	skt->res_mem.start = _PCMCIAMem(skt->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	skt->res_mem.name = "memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	skt->res_mem.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	skt->res_attr.start = _PCMCIAAttr(skt->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	skt->res_attr.name = "attribute";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	skt->res_attr.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return soc_pcmcia_add_one(skt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/* Provide our PXA2xx specific timing routines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	ops->set_timing  = pxa2xx_pcmcia_set_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #ifdef CONFIG_CPU_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	ops->frequency_change = pxa2xx_pcmcia_frequency_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct pcmcia_low_level *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	struct skt_dev_info *sinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct soc_pcmcia_socket *skt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	ops = (struct pcmcia_low_level *)dev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (!ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (cpu_is_pxa320() && ops->nr > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	clk = devm_clk_get(&dev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	pxa2xx_drv_pcmcia_ops(ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	sinfo = devm_kzalloc(&dev->dev, SKT_DEV_INFO_SIZE(ops->nr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (!sinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	sinfo->nskt = ops->nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/* Initialize processor specific parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	for (i = 0; i < ops->nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		skt = &sinfo->skt[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		skt->nr = ops->first + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		skt->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		soc_pcmcia_init_one(skt, ops, &dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		ret = pxa2xx_drv_pcmcia_add_one(skt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	pxa2xx_configure_sockets(&dev->dev, ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	dev_set_drvdata(&dev->dev, sinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		soc_pcmcia_remove_one(&sinfo->skt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct skt_dev_info *sinfo = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	for (i = 0; i < sinfo->nskt; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		soc_pcmcia_remove_one(&sinfo->skt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int pxa2xx_drv_pcmcia_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct pcmcia_low_level *ops = (struct pcmcia_low_level *)dev->platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	pxa2xx_configure_sockets(dev, ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	.resume		= pxa2xx_drv_pcmcia_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct platform_driver pxa2xx_pcmcia_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	.probe		= pxa2xx_drv_pcmcia_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.remove		= pxa2xx_drv_pcmcia_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.name	= "pxa2xx-pcmcia",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		.pm	= &pxa2xx_drv_pcmcia_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int __init pxa2xx_pcmcia_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	return platform_driver_register(&pxa2xx_pcmcia_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void __exit pxa2xx_pcmcia_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	platform_driver_unregister(&pxa2xx_pcmcia_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) fs_initcall(pxa2xx_pcmcia_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) module_exit(pxa2xx_pcmcia_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MODULE_ALIAS("platform:pxa2xx-pcmcia");