Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * o2micro.h 1.13 1999/10/25 20:03:34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * The contents of this file are subject to the Mozilla Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Version 1.1 (the "License"); you may not use this file except in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * compliance with the License. You may obtain a copy of the License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * at http://www.mozilla.org/MPL/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Software distributed under the License is distributed on an "AS IS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * the License for the specific language governing rights and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * limitations under the License. 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * The initial developer of the original code is David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Alternatively, the contents of this file may be used under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * terms of the GNU General Public License version 2 (the "GPL"), in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * case the provisions of the GPL are applicable instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * above.  If you wish to allow the use of your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * only under the terms of the GPL and not to allow others to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * your version of this file under the MPL, indicate your decision by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * deleting the provisions above and replace them with the notice and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * other provisions required by the GPL.  If you do not delete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * provisions above, a recipient may use your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * under either the MPL or the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #ifndef _LINUX_O2MICRO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define _LINUX_O2MICRO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* Additional PCI configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define O2_MUX_CONTROL		0x90	/* 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define  O2_MUX_RING_OUT	0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define  O2_MUX_SKTB_ACTV	0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define  O2_MUX_SCTA_ACTV_ENA	0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define  O2_MUX_SCTB_ACTV_ENA	0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define  O2_MUX_SER_IRQ_ROUTE	0x0000e000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define  O2_MUX_SER_PCI		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define  O2_MUX_SKTA_TURBO	0x000c0000	/* for 6833, 6860 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define  O2_MUX_SKTB_TURBO	0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define  O2_MUX_AUX_VCC_3V	0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define  O2_MUX_PCI_VCC_5V	0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define  O2_MUX_PME_MUX		0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* Additional ExCA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define O2_MODE_A		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define O2_MODE_A_2		0x26	/* for 6833B, 6860C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define  O2_MODE_A_CD_PULSE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define  O2_MODE_A_SUSP_EDGE	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define  O2_MODE_A_HOST_SUSP	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define  O2_MODE_A_PWR_MASK	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define  O2_MODE_A_QUIET	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define O2_MODE_B		0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define O2_MODE_B_2		0x2e	/* for 6833B, 6860C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define  O2_MODE_B_IDENT	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define  O2_MODE_B_ID_BSTEP	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define  O2_MODE_B_ID_CSTEP	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define  O2_MODE_B_ID_O2	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define  O2_MODE_B_VS1		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define  O2_MODE_B_VS2		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define  O2_MODE_B_IRQ15_RI	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define O2_MODE_C		0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define  O2_MODE_C_DREQ_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define  O2_MODE_C_DREQ_INPACK	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define  O2_MODE_C_DREQ_WP	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define  O2_MODE_C_DREQ_BVD2	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define  O2_MODE_C_ZVIDEO	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define  O2_MODE_C_IREQ_SEL	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define  O2_MODE_C_MGMT_SEL	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define O2_MODE_D		0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define  O2_MODE_D_IRQ_MODE	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define  O2_MODE_D_PCI_CLKRUN	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define  O2_MODE_D_CB_CLKRUN	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define  O2_MODE_D_SKT_ACTV	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define  O2_MODE_D_PCI_FIFO	0x40	/* for OZ6729, OZ6730 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define  O2_MODE_D_W97_IRQ	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define  O2_MODE_D_ISA_IRQ	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define O2_MHPG_DMA		0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define  O2_MHPG_CHANNEL	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define  O2_MHPG_CINT_ENA	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define  O2_MHPG_CSC_ENA	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define O2_FIFO_ENA		0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define  O2_FIFO_ZVIDEO_3	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define  O2_FIFO_PCI_FIFO	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define  O2_FIFO_POSTWR		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define  O2_FIFO_BUFFER		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define O2_MODE_E		0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define  O2_MODE_E_MHPG_DMA	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define  O2_MODE_E_SPKR_OUT	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define  O2_MODE_E_LED_OUT	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define  O2_MODE_E_SKTA_ACTV	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define O2_RESERVED1		0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define O2_RESERVED2		0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define O2_RES_READ_PREFETCH	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define O2_RES_WRITE_BURST	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int o2micro_override(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 * 'reserved' register at 0x94/D4. allows setting read prefetch and write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 * bursting. read prefetching for example makes the RME Hammerfall DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	 * working. for some bridges it is at 0x94, for others at 0xD4. it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 * ok to write to both registers on all O2 bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 * from Eric Still, 02Micro.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u8 a, b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	bool use_speedup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (PCI_FUNC(socket->dev->devfn) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		a = config_readb(socket, O2_RESERVED1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		b = config_readb(socket, O2_RESERVED2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		dev_dbg(&socket->dev->dev, "O2: 0x94/0xD4: %02x/%02x\n", a, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		switch (socket->dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		 * older bridges have problems with both read prefetch and write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		 * bursting depending on the combination of the chipset, bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		 * and the cardbus card. so disable them to be on the safe side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		case PCI_DEVICE_ID_O2_6729:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		case PCI_DEVICE_ID_O2_6730:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		case PCI_DEVICE_ID_O2_6812:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		case PCI_DEVICE_ID_O2_6832:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		case PCI_DEVICE_ID_O2_6836:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		case PCI_DEVICE_ID_O2_6933:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			use_speedup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			use_speedup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		/* the user may override our decision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		if (strcasecmp(o2_speedup, "on") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			use_speedup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		else if (strcasecmp(o2_speedup, "off") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			use_speedup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		else if (strcasecmp(o2_speedup, "default") != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			dev_warn(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				"O2: Unknown parameter, using 'default'");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		if (use_speedup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 				"O2: enabling read prefetch/write burst. If you experience problems or performance issues, use the yenta_socket parameter 'o2_speedup=off'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			config_writeb(socket, O2_RESERVED1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 				      a | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			config_writeb(socket, O2_RESERVED2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				      b | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			dev_info(&socket->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				"O2: disabling read prefetch/write burst. If you experience problems or performance issues, use the yenta_socket parameter 'o2_speedup=on'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			config_writeb(socket, O2_RESERVED1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				      a & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			config_writeb(socket, O2_RESERVED2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				      b & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void o2micro_restore_state(struct yenta_socket *socket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 * as long as read prefetch is the only thing in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	 * o2micro_override, it's safe to call it from here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	o2micro_override(socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #endif /* _LINUX_O2MICRO_H */