^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * i82365.h 1.15 1999/10/25 20:03:34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * The contents of this file are subject to the Mozilla Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Version 1.1 (the "License"); you may not use this file except in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * compliance with the License. You may obtain a copy of the License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * at http://www.mozilla.org/MPL/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software distributed under the License is distributed on an "AS IS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the License for the specific language governing rights and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * limitations under the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * The initial developer of the original code is David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Alternatively, the contents of this file may be used under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * terms of the GNU General Public License version 2 (the "GPL"), in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * case the provisions of the GPL are applicable instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * above. If you wish to allow the use of your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * only under the terms of the GPL and not to allow others to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * your version of this file under the MPL, indicate your decision by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * deleting the provisions above and replace them with the notice and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * other provisions required by the GPL. If you do not delete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * provisions above, a recipient may use your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * under either the MPL or the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifndef _LINUX_I82365_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define _LINUX_I82365_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* register definitions for the Intel 82365SL PCMCIA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Offsets for PCIC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I365_IDENT 0x00 /* Identification and revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I365_STATUS 0x01 /* Interface status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I365_POWER 0x02 /* Power and RESETDRV control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I365_INTCTL 0x03 /* Interrupt and general control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I365_CSC 0x04 /* Card status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I365_CSCINT 0x05 /* Card status change interrupt control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I365_ADDRWIN 0x06 /* Address window enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I365_IOCTL 0x07 /* I/O control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I365_GENCTL 0x16 /* Card detect and general control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I365_GBLCTL 0x1E /* Global control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Offsets for I/O and memory window registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I365_IO(map) (0x08+((map)<<2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define I365_MEM(map) (0x10+((map)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I365_W_START 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I365_W_STOP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I365_W_OFF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Flags for I365_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I365_CS_BVD1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I365_CS_STSCHG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I365_CS_BVD2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I365_CS_SPKR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I365_CS_DETECT 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define I365_CS_WRPROT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I365_CS_READY 0x20 /* Inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I365_CS_POWERON 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I365_CS_GPI 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Flags for I365_POWER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define I365_PWR_OFF 0x00 /* Turn off the socket */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define I365_PWR_OUT 0x80 /* Output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* There are different layouts for B-step and DF-step chips: the B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) step has independent Vpp1/Vpp2 control, and the DF step has only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) Vpp1 control, plus 3V control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define I365_VCC_5V 0x10 /* Vcc = 5.0v */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define I365_VCC_3V 0x18 /* Vcc = 3.3v */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define I365_VPP1_5V 0x01 /* Vpp1 = 5.0v */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define I365_VPP1_12V 0x02 /* Vpp1 = 12.0v */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Flags for I365_INTCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define I365_RING_ENA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define I365_PC_RESET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define I365_PC_IOCARD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define I365_INTR_ENA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define I365_IRQ_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Flags for I365_CSC and I365_CSCINT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define I365_CSC_BVD1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define I365_CSC_STSCHG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define I365_CSC_BVD2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define I365_CSC_READY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define I365_CSC_DETECT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define I365_CSC_ANY 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define I365_CSC_GPI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define I365_CSC_IRQ_MASK 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Flags for I365_ADDRWIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define I365_ENA_IO(map) (0x40 << (map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define I365_ENA_MEM(map) (0x01 << (map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Flags for I365_IOCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define I365_IOCTL_MASK(map) (0x0F << (map<<2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define I365_IOCTL_WAIT(map) (0x08 << (map<<2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define I365_IOCTL_0WS(map) (0x04 << (map<<2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define I365_IOCTL_IOCS16(map) (0x02 << (map<<2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define I365_IOCTL_16BIT(map) (0x01 << (map<<2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Flags for I365_GENCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define I365_CTL_16DELAY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define I365_CTL_RESET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define I365_CTL_GPI_ENA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define I365_CTL_GPI_CTL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define I365_CTL_RESUME 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define I365_CTL_SW_IRQ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Flags for I365_GBLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define I365_GBL_PWRDOWN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define I365_GBL_CSC_LEV 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define I365_GBL_WRBACK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define I365_GBL_IRQ_0_LEV 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define I365_GBL_IRQ_1_LEV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Flags for memory window registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define I365_MEM_16BIT 0x8000 /* In memory start high byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define I365_MEM_0WS 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define I365_MEM_WS1 0x8000 /* In memory stop high byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define I365_MEM_WS0 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define I365_MEM_WRPROT 0x8000 /* In offset high byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define I365_MEM_REG 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define I365_REG(slot, reg) (((slot) << 6) + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #endif /* _LINUX_I82365_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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