^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Intel I82092AA PCI-PCMCIA bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) 2001 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Arjan Van De Ven <arjanv@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Loosly based on i82365.c from the pcmcia-cs package
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <pcmcia/ss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "i82092aa.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "i82365.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* PCI core routines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const struct pci_device_id i82092aa_pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82092AA_0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct pci_driver i82092aa_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .name = "i82092aa",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .id_table = i82092aa_pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .probe = i82092aa_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .remove = i82092aa_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* the pccard structure and its functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct pccard_operations i82092aa_operations = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .init = i82092aa_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .get_status = i82092aa_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .set_socket = i82092aa_set_socket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .set_io_map = i82092aa_set_io_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .set_mem_map = i82092aa_set_mem_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* The card can do up to 4 sockets, allocate a structure for each of them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct socket_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int card_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* 0 = no socket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 1 = empty socket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 2 = card but not initialized,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 3 = operational card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int io_base; /* base io address of the socket */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct pcmcia_socket socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct pci_dev *dev; /* The PCI device for the socket */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MAX_SOCKETS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct socket_info sockets[MAX_SOCKETS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int socket_count; /* shortcut */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int i82092aa_pci_probe(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned char configbyte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* PCI Configuration Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pci_read_config_byte(dev, 0x40, &configbyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) switch (configbyte&6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) socket_count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) socket_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) socket_count = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "Oops, you did something we didn't think of.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) goto err_out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dev_info(&dev->dev, "configured as a %d socket device.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) socket_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) goto err_out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) for (i = 0; i < socket_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) sockets[i].card_state = 1; /* 1 = present but empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sockets[i].io_base = pci_resource_start(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) sockets[i].dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) sockets[i].socket.features |= SS_CAP_PCCARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) sockets[i].socket.map_size = 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) sockets[i].socket.irq_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) sockets[i].socket.pci_irq = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) sockets[i].socket.cb_dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) sockets[i].socket.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) sockets[i].number = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (card_present(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) sockets[i].card_state = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev_dbg(&dev->dev, "slot %i is occupied\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev_dbg(&dev->dev, "slot %i is vacant\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Now, specifiy that all interrupts are to be done as PCI interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) configbyte = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* PCI Interrupt Routing Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pci_write_config_byte(dev, 0x50, configbyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Register the interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev_dbg(&dev->dev, "Requesting interrupt %i\n", dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "i82092aa", i82092aa_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(&dev->dev, "Failed to register IRQ %d, aborting\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) goto err_out_free_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) for (i = 0; i < socket_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sockets[i].socket.dev.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) sockets[i].socket.ops = &i82092aa_operations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) sockets[i].socket.resource_ops = &pccard_nonstatic_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = pcmcia_register_socket(&sockets[i].socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto err_out_free_sockets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) err_out_free_sockets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) for (i--; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pcmcia_unregister_socket(&sockets[i].socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) free_irq(dev->irq, i82092aa_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) err_out_free_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) release_region(pci_resource_start(dev, 0), 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) err_out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void i82092aa_pci_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) free_irq(dev->irq, i82092aa_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) for (i = 0; i < socket_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pcmcia_unregister_socket(&sockets[i].socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static DEFINE_SPINLOCK(port_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* basic value read/write functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static unsigned char indirect_read(int socket, unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned short int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) spin_lock_irqsave(&port_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) reg += socket * 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) port = sockets[socket].io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) outb(reg, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) val = inb(port+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spin_unlock_irqrestore(&port_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void indirect_write(int socket, unsigned short reg, unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned short int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) spin_lock_irqsave(&port_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) reg = reg + socket * 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) port = sockets[socket].io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) outb(reg, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) outb(value, port+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spin_unlock_irqrestore(&port_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void indirect_setbit(int socket, unsigned short reg, unsigned char mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned short int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spin_lock_irqsave(&port_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) reg = reg + socket * 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) port = sockets[socket].io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) outb(reg, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) val = inb(port+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) outb(reg, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) outb(val, port+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) spin_unlock_irqrestore(&port_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void indirect_resetbit(int socket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned short reg, unsigned char mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned short int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spin_lock_irqsave(&port_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) reg = reg + socket * 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) port = sockets[socket].io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) outb(reg, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) val = inb(port+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) outb(reg, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) outb(val, port+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) spin_unlock_irqrestore(&port_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void indirect_write16(int socket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned short reg, unsigned short value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned short int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) spin_lock_irqsave(&port_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) reg = reg + socket * 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) port = sockets[socket].io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) outb(reg, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) val = value & 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) outb(val, port+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) reg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) outb(reg, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) val = value>>8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) outb(val, port+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) spin_unlock_irqrestore(&port_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* simple helper functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int cycle_time = 120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int to_cycles(int ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (cycle_time != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ns/cycle_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Interrupt handler functionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static irqreturn_t i82092aa_interrupt(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int loopcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned int events, active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) loopcount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (loopcount > 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pr_err("i82092aa: infinite eventloop in interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) for (i = 0; i < socket_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int csc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Inactive socket, should not happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (sockets[i].card_state == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* card status change register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) csc = indirect_read(i, I365_CSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (csc == 0) /* no events on this socket */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (csc & I365_CSC_DETECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) events |= SS_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev_info(&sockets[i].dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "Card detected in socket %i!\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (indirect_read(i, I365_INTCTL) & I365_PC_IOCARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* For IO/CARDS, bit 0 means "read the card" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (csc & I365_CSC_STSCHG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) events |= SS_STSCHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Check for battery/ready events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (csc & I365_CSC_BVD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) events |= SS_BATDEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (csc & I365_CSC_BVD2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) events |= SS_BATWARN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (csc & I365_CSC_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) events |= SS_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pcmcia_parse_events(&sockets[i].socket, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) active |= events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (active == 0) /* no more events to handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* socket functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int card_present(int socketno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if ((socketno < 0) || (socketno >= MAX_SOCKETS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (sockets[socketno].io_base == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) val = indirect_read(socketno, 1); /* Interface status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if ((val&12) == 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void set_bridge_state(int sock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) indirect_write(sock, I365_GBLCTL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) indirect_write(sock, I365_GENCTL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) indirect_setbit(sock, I365_INTCTL, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int i82092aa_init(struct pcmcia_socket *sock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct resource res = { .start = 0, .end = 0x0fff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pccard_io_map io = { 0, 0, 0, 0, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pccard_mem_map mem = { .res = &res, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) io.map = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) i82092aa_set_io_map(sock, &io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) mem.map = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) i82092aa_set_mem_map(sock, &mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned int sock = container_of(socket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct socket_info, socket)->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Interface Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) status = indirect_read(sock, I365_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if ((status & I365_CS_DETECT) == I365_CS_DETECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) *value |= SS_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* IO cards have a different meaning of bits 0,1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Also notice the inverse-logic on the bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* IO card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!(status & I365_CS_STSCHG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) *value |= SS_STSCHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } else { /* non I/O card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (!(status & I365_CS_BVD1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *value |= SS_BATDEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!(status & I365_CS_BVD2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) *value |= SS_BATWARN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (status & I365_CS_WRPROT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) (*value) |= SS_WRPROT; /* card is write protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (status & I365_CS_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) (*value) |= SS_READY; /* card is not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (status & I365_CS_POWERON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) (*value) |= SS_POWERON; /* power is applied to the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int i82092aa_set_socket(struct pcmcia_socket *socket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) socket_state_t *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct socket_info *sock_info = container_of(socket, struct socket_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned int sock = sock_info->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* First, set the global controller options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) set_bridge_state(sock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Values for the IGENC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* The reset bit has "inverse" logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!(state->flags & SS_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) reg = reg | I365_PC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (state->flags & SS_IOCARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) reg = reg | I365_PC_IOCARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* IGENC, Interrupt and General Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) indirect_write(sock, I365_INTCTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Power registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (state->flags & SS_PWR_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev_info(&sock_info->dev->dev, "Auto power\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) reg |= I365_PWR_AUTO; /* automatic power mngmnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (state->flags & SS_OUTPUT_ENA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_info(&sock_info->dev->dev, "Power Enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) reg |= I365_PWR_OUT; /* enable power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) switch (state->Vcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_info(&sock_info->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "setting voltage to Vcc to 5V on socket %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) sock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) reg |= I365_VCC_5V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_err(&sock_info->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "%s called with invalid VCC power value: %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) __func__, state->Vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) switch (state->Vpp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_info(&sock_info->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) "not setting Vpp on socket %i\n", sock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_info(&sock_info->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) "setting Vpp to 5.0 for socket %i\n", sock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) reg |= I365_VPP1_5V | I365_VPP2_5V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case 120:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_info(&sock_info->dev->dev, "setting Vpp to 12.0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) reg |= I365_VPP1_12V | I365_VPP2_12V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_err(&sock_info->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) "%s called with invalid VPP power value: %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) __func__, state->Vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (reg != indirect_read(sock, I365_POWER)) /* only write if changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) indirect_write(sock, I365_POWER, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Enable specific interrupt events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) reg = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (state->csc_mask & SS_DETECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) reg |= I365_CSC_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (state->flags & SS_IOCARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (state->csc_mask & SS_STSCHG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) reg |= I365_CSC_STSCHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (state->csc_mask & SS_BATDEAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) reg |= I365_CSC_BVD1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (state->csc_mask & SS_BATWARN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) reg |= I365_CSC_BVD2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (state->csc_mask & SS_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) reg |= I365_CSC_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* now write the value and clear the (probably bogus) pending stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * by doing a dummy read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) indirect_write(sock, I365_CSCINT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) (void)indirect_read(sock, I365_CSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int i82092aa_set_io_map(struct pcmcia_socket *socket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct pccard_io_map *io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct socket_info *sock_info = container_of(socket, struct socket_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned int sock = sock_info->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned char map, ioctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) map = io->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Check error conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (map > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if ((io->start > 0xffff) || (io->stop > 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) || (io->stop < io->start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Turn off the window before changing anything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* write the new values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) indirect_write16(sock, I365_IO(map)+I365_W_START, io->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) indirect_write16(sock, I365_IO(map)+I365_W_STOP, io->stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ioctl = indirect_read(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (io->flags & (MAP_16BIT|MAP_AUTOSZ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ioctl |= I365_IOCTL_16BIT(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) indirect_write(sock, I365_IOCTL, ioctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Turn the window back on if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (io->flags & MAP_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) indirect_setbit(sock, I365_ADDRWIN, I365_ENA_IO(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int i82092aa_set_mem_map(struct pcmcia_socket *socket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct pccard_mem_map *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct socket_info *sock_info = container_of(socket, struct socket_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned int sock = sock_info->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned short base, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned char map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pcibios_resource_to_bus(sock_info->dev->bus, ®ion, mem->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) map = mem->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (map > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if ((mem->card_start > 0x3ffffff) || (region.start > region.end) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) (mem->speed > 1000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_err(&sock_info->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) "invalid mem map for socket %i: %llx to %llx with a start of %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) sock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) (unsigned long long)region.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) (unsigned long long)region.end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mem->card_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Turn off the window before changing anything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* write the start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) base = I365_MEM(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) i = (region.start >> 12) & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (mem->flags & MAP_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) i |= I365_MEM_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (mem->flags & MAP_0WS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) i |= I365_MEM_0WS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) indirect_write16(sock, base+I365_W_START, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* write the stop address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) i = (region.end >> 12) & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) switch (to_cycles(mem->speed)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) i |= I365_MEM_WS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) i |= I365_MEM_WS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) i |= I365_MEM_WS1 | I365_MEM_WS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) indirect_write16(sock, base+I365_W_STOP, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* card start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) i = ((mem->card_start - region.start) >> 12) & 0x3fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (mem->flags & MAP_WRPROT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) i |= I365_MEM_WRPROT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (mem->flags & MAP_ATTRIB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) i |= I365_MEM_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) indirect_write16(sock, base+I365_W_OFF, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* Enable the window if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (mem->flags & MAP_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int i82092aa_module_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return pci_register_driver(&i82092aa_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static void i82092aa_module_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) pci_unregister_driver(&i82092aa_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (sockets[0].io_base > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) release_region(sockets[0].io_base, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) module_init(i82092aa_module_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) module_exit(i82092aa_module_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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