^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * cirrus.h 1.4 1999/10/25 20:03:34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * The contents of this file are subject to the Mozilla Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Version 1.1 (the "License"); you may not use this file except in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * compliance with the License. You may obtain a copy of the License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * at http://www.mozilla.org/MPL/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software distributed under the License is distributed on an "AS IS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the License for the specific language governing rights and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * limitations under the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * The initial developer of the original code is David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Alternatively, the contents of this file may be used under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * terms of the GNU General Public License version 2 (the "GPL"), in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * case the provisions of the GPL are applicable instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * above. If you wish to allow the use of your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * only under the terms of the GPL and not to allow others to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * your version of this file under the MPL, indicate your decision by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * deleting the provisions above and replace them with the notice and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * other provisions required by the GPL. If you do not delete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * provisions above, a recipient may use your version of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * under either the MPL or the GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifndef _LINUX_CIRRUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define _LINUX_CIRRUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PD67_MISC_CTL_1 0x16 /* Misc control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PD67_FIFO_CTL 0x17 /* FIFO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PD67_MISC_CTL_2 0x1E /* Misc control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PD67_CHIP_INFO 0x1f /* Chip information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PD67_ATA_CTL 0x026 /* 6730: ATA control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PD67_EXT_INDEX 0x2e /* Extension index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PD67_EXT_DATA 0x2f /* Extension data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PD67_DATA_MASK0 0x01 /* Data mask 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PD67_DATA_MASK1 0x02 /* Data mask 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PD67_DMA_CTL 0x03 /* DMA control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PD67_EXT_CTL_1 0x03 /* Extension control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PD67_EXTERN_DATA 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PD67_MISC_CTL_3 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PD67_SMB_PWR_CTL 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* I/O window address offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PD67_IO_OFF(w) (0x36+((w)<<1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Timing register sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PD67_TIME_SETUP(n) (0x3a + 3*(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PD67_TIME_CMD(n) (0x3b + 3*(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PD67_TIME_RECOV(n) (0x3c + 3*(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Flags for PD67_MISC_CTL_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PD67_MC1_5V_DET 0x01 /* 5v detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PD67_MC1_PULSE_MGMT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PD67_MC1_PULSE_IRQ 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PD67_MC1_SPKR_ENA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PD67_MC1_INPACK_ENA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Flags for PD67_FIFO_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PD67_FIFO_EMPTY 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Flags for PD67_MISC_CTL_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PD67_MC2_FREQ_BYPASS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PD67_MC2_DYNAMIC_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PD67_MC2_SUSPEND 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PD67_MC2_5V_CORE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PD67_MC2_DMA_MODE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Flags for PD67_CHIP_INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PD67_INFO_CHIP_ID 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PD67_INFO_REV 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Fields in PD67_TIME_* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PD67_TIME_SCALE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PD67_TIME_SCALE_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PD67_TIME_SCALE_16 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PD67_TIME_SCALE_256 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PD67_TIME_SCALE_4096 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PD67_TIME_MULT 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Fields in PD67_DMA_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PD67_DMA_MODE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PD67_DMA_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PD67_DMA_DREQ_INPACK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PD67_DMA_DREQ_WP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PD67_DMA_DREQ_BVD2 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Fields in PD67_EXT_CTL_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PD67_EC1_VCC_PWR_LOCK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PD67_EC1_AUTO_PWR_CLEAR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PD67_EC1_LED_ENA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PD67_EC1_INV_CARD_IRQ 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PD67_EC1_INV_MGMT_IRQ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PD67_EC1_PULLUP_CTL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Fields in PD67_MISC_CTL_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PD67_MC3_IRQ_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PD67_MC3_IRQ_PCPCI 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PD67_MC3_IRQ_EXTERN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PD67_MC3_IRQ_PCIWAY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PD67_MC3_IRQ_PCI 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PD67_MC3_PWR_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PD67_MC3_PWR_SERIAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PD67_MC3_PWR_TI2202 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PD67_MC3_PWR_SMB 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PD68_EXT_CTL_2 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PD68_PCI_SPACE 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PD68_PCCARD_SPACE 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PD68_WINDOW_TYPE 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PD68_EXT_CSC 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PD68_MISC_CTL_4 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PD68_MISC_CTL_5 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PD68_MISC_CTL_6 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Extra flags in PD67_MISC_CTL_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PD68_MC3_HW_SUSP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PD68_MC3_MM_EXPAND 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PD68_MC3_MM_ARM 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Bridge Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PD6832_BCR_MGMT_IRQ_ENA 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Socket Number Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif /* _LINUX_CIRRUS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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