^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCI Virtual Channel support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Red Hat, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Alex Williamson <alex.williamson@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * pci_vc_save_restore_dwords - Save or restore a series of dwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * @dev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * @pos: starting config space position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * @buf: buffer to save to or restore from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @dwords: number of dwords to save/restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @save: whether to save or restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static void pci_vc_save_restore_dwords(struct pci_dev *dev, int pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 *buf, int dwords, bool save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) for (i = 0; i < dwords; i++, buf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) pci_read_config_dword(dev, pos + (i * 4), buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) pci_write_config_dword(dev, pos + (i * 4), *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * pci_vc_load_arb_table - load and wait for VC arbitration table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @dev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @pos: starting position of VC capability (VC/VC9/MFVC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Set Load VC Arbitration Table bit requesting hardware to apply the VC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Arbitration Table (previously loaded). When the VC Arbitration Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Status clears, hardware has latched the table into VC arbitration logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void pci_vc_load_arb_table(struct pci_dev *dev, int pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pci_read_config_word(dev, pos + PCI_VC_PORT_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pci_write_config_word(dev, pos + PCI_VC_PORT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ctrl | PCI_VC_PORT_CTRL_LOAD_TABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (pci_wait_for_pending(dev, pos + PCI_VC_PORT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PCI_VC_PORT_STATUS_TABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pci_err(dev, "VC arbitration table failed to load\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * pci_vc_load_port_arb_table - Load and wait for VC port arbitration table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @dev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @pos: starting position of VC capability (VC/VC9/MFVC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @res: VC resource number, ie. VCn (0-7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Set Load Port Arbitration Table bit requesting hardware to apply the Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Arbitration Table (previously loaded). When the Port Arbitration Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Status clears, hardware has latched the table into port arbitration logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void pci_vc_load_port_arb_table(struct pci_dev *dev, int pos, int res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int ctrl_pos, status_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) status_pos = pos + PCI_VC_RES_STATUS + (res * PCI_CAP_VC_PER_VC_SIZEOF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pci_read_config_dword(dev, ctrl_pos, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pci_write_config_dword(dev, ctrl_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ctrl | PCI_VC_RES_CTRL_LOAD_TABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (pci_wait_for_pending(dev, status_pos, PCI_VC_RES_STATUS_TABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pci_err(dev, "VC%d port arbitration table failed to load\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * pci_vc_enable - Enable virtual channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @dev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @pos: starting position of VC capability (VC/VC9/MFVC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @res: VC res number, ie. VCn (0-7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * A VC is enabled by setting the enable bit in matching resource control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * registers on both sides of a link. We therefore need to find the opposite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * end of the link. To keep this simple we enable from the downstream device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * RC devices do not have an upstream device, nor does it seem that VC9 do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * (spec is unclear). Once we find the upstream device, match the VC ID to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * get the correct resource, disable and enable on both ends.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void pci_vc_enable(struct pci_dev *dev, int pos, int res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int ctrl_pos, status_pos, id, pos2, evcc, i, ctrl_pos2, status_pos2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 ctrl, header, cap1, ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct pci_dev *link = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Enable VCs from the downstream device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!pci_is_pcie(dev) || !pcie_downstream_port(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) status_pos = pos + PCI_VC_RES_STATUS + (res * PCI_CAP_VC_PER_VC_SIZEOF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pci_read_config_dword(dev, ctrl_pos, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) id = ctrl & PCI_VC_RES_CTRL_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pci_read_config_dword(dev, pos, &header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* If there is no opposite end of the link, skip to enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (PCI_EXT_CAP_ID(header) == PCI_EXT_CAP_ID_VC9 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pci_is_root_bus(dev->bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) goto enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pos2 = pci_find_ext_capability(dev->bus->self, PCI_EXT_CAP_ID_VC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (!pos2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) goto enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pci_read_config_dword(dev->bus->self, pos2 + PCI_VC_PORT_CAP1, &cap1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) evcc = cap1 & PCI_VC_CAP1_EVCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* VC0 is hardwired enabled, so we can start with 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) for (i = 1; i < evcc + 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ctrl_pos2 = pos2 + PCI_VC_RES_CTRL +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) (i * PCI_CAP_VC_PER_VC_SIZEOF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) status_pos2 = pos2 + PCI_VC_RES_STATUS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (i * PCI_CAP_VC_PER_VC_SIZEOF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pci_read_config_dword(dev->bus->self, ctrl_pos2, &ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if ((ctrl2 & PCI_VC_RES_CTRL_ID) == id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) link = dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Disable if enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ctrl2 & PCI_VC_RES_CTRL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ctrl2 &= ~PCI_VC_RES_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pci_write_config_dword(link, ctrl_pos2, ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Enable on both ends */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ctrl2 |= PCI_VC_RES_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pci_write_config_dword(link, ctrl_pos2, ctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ctrl |= PCI_VC_RES_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pci_write_config_dword(dev, ctrl_pos, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (!pci_wait_for_pending(dev, status_pos, PCI_VC_RES_STATUS_NEGO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pci_err(dev, "VC%d negotiation stuck pending\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (link && !pci_wait_for_pending(link, status_pos2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PCI_VC_RES_STATUS_NEGO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pci_err(link, "VC%d negotiation stuck pending\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * pci_vc_do_save_buffer - Size, save, or restore VC state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @dev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @pos: starting position of VC capability (VC/VC9/MFVC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @save_state: buffer for save/restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @save: if provided a buffer, this indicates what to do with it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Walking Virtual Channel config space to size, save, or restore it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * is complicated, so we do it all from one function to reduce code and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * guarantee ordering matches in the buffer. When called with NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @save_state, return the size of the necessary save buffer. When called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * with a non-NULL @save_state, @save determines whether we save to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * buffer or restore from it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int pci_vc_do_save_buffer(struct pci_dev *dev, int pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct pci_cap_saved_state *save_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bool save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 cap1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) char evcc, lpevcc, parb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int i, len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u8 *buf = save_state ? (u8 *)save_state->cap.data : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Sanity check buffer size for save/restore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (buf && save_state->cap.size !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pci_vc_do_save_buffer(dev, pos, NULL, save)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pci_err(dev, "VC save buffer size does not match @0x%x\n", pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pci_read_config_dword(dev, pos + PCI_VC_PORT_CAP1, &cap1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Extended VC Count (not counting VC0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) evcc = cap1 & PCI_VC_CAP1_EVCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Low Priority Extended VC Count (not counting VC0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) lpevcc = (cap1 & PCI_VC_CAP1_LPEVCC) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Port Arbitration Table Entry Size (bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) parb_size = 1 << ((cap1 & PCI_VC_CAP1_ARB_SIZE) >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Port VC Control Register contains VC Arbitration Select, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * cannot be modified when more than one LPVC is in operation. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * therefore save/restore it first, as only VC0 should be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * after device reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pci_read_config_word(dev, pos + PCI_VC_PORT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) (u16 *)buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pci_write_config_word(dev, pos + PCI_VC_PORT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *(u16 *)buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) buf += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) len += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * If we have any Low Priority VCs and a VC Arbitration Table Offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * in Port VC Capability Register 2 then save/restore it next.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (lpevcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 cap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int vcarb_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pci_read_config_dword(dev, pos + PCI_VC_PORT_CAP2, &cap2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) vcarb_offset = ((cap2 & PCI_VC_CAP2_ARB_OFF) >> 24) * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (vcarb_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int size, vcarb_phases = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (cap2 & PCI_VC_CAP2_128_PHASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) vcarb_phases = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) else if (cap2 & PCI_VC_CAP2_64_PHASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) vcarb_phases = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) else if (cap2 & PCI_VC_CAP2_32_PHASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) vcarb_phases = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Fixed 4 bits per phase per lpevcc (plus VC0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) size = ((lpevcc + 1) * vcarb_phases * 4) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (size && buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pci_vc_save_restore_dwords(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pos + vcarb_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (u32 *)buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) size / 4, save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * On restore, we need to signal hardware to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * re-load the VC Arbitration Table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pci_vc_load_arb_table(dev, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) buf += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) len += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * In addition to each VC Resource Control Register, we may have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Port Arbitration Table attached to each VC. The Port Arbitration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Table Offset in each VC Resource Capability Register tells us if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * it exists. The entry size is global from the Port VC Capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Register1 above. The number of phases is determined per VC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) for (i = 0; i < evcc + 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int parb_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pci_read_config_dword(dev, pos + PCI_VC_RES_CAP +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (i * PCI_CAP_VC_PER_VC_SIZEOF), &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) parb_offset = ((cap & PCI_VC_RES_CAP_ARB_OFF) >> 24) * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (parb_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int size, parb_phases = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (cap & PCI_VC_RES_CAP_256_PHASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) parb_phases = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) else if (cap & (PCI_VC_RES_CAP_128_PHASE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PCI_VC_RES_CAP_128_PHASE_TB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) parb_phases = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) else if (cap & PCI_VC_RES_CAP_64_PHASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) parb_phases = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) else if (cap & PCI_VC_RES_CAP_32_PHASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) parb_phases = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) size = (parb_size * parb_phases) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (size && buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pci_vc_save_restore_dwords(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pos + parb_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (u32 *)buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) size / 4, save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) buf += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) len += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* VC Resource Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int ctrl_pos = pos + PCI_VC_RES_CTRL +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) (i * PCI_CAP_VC_PER_VC_SIZEOF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pci_read_config_dword(dev, ctrl_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) (u32 *)buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 tmp, ctrl = *(u32 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * For an FLR case, the VC config may remain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * Preserve enable bit, restore the rest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pci_read_config_dword(dev, ctrl_pos, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) tmp &= PCI_VC_RES_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) tmp |= ctrl & ~PCI_VC_RES_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pci_write_config_dword(dev, ctrl_pos, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Load port arbitration table if used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ctrl & PCI_VC_RES_CTRL_ARB_SELECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pci_vc_load_port_arb_table(dev, pos, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Re-enable if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if ((ctrl ^ tmp) & PCI_VC_RES_CTRL_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pci_vc_enable(dev, pos, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) buf += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) len += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return buf ? 0 : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) } vc_caps[] = { { PCI_EXT_CAP_ID_MFVC, "MFVC" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { PCI_EXT_CAP_ID_VC, "VC" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { PCI_EXT_CAP_ID_VC9, "VC9" } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * pci_save_vc_state - Save VC state to pre-allocate save buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @dev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * For each type of VC capability, VC/VC9/MFVC, find the capability and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * save it to the pre-allocated save buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int pci_save_vc_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (i = 0; i < ARRAY_SIZE(vc_caps); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int pos, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct pci_cap_saved_state *save_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pos = pci_find_ext_capability(dev, vc_caps[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) save_state = pci_find_saved_ext_cap(dev, vc_caps[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!save_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pci_err(dev, "%s buffer not found in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) vc_caps[i].name, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = pci_vc_do_save_buffer(dev, pos, save_state, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pci_err(dev, "%s save unsuccessful %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) vc_caps[i].name, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * pci_restore_vc_state - Restore VC state from save buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * @dev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * For each type of VC capability, VC/VC9/MFVC, find the capability and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * restore it from the previously saved buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) void pci_restore_vc_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) for (i = 0; i < ARRAY_SIZE(vc_caps); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct pci_cap_saved_state *save_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pos = pci_find_ext_capability(dev, vc_caps[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) save_state = pci_find_saved_ext_cap(dev, vc_caps[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (!save_state || !pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pci_vc_do_save_buffer(dev, pos, save_state, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * pci_allocate_vc_save_buffers - Allocate save buffers for VC caps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * @dev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * For each type of VC capability, VC/VC9/MFVC, find the capability, size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * it, and allocate a buffer for save/restore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) void pci_allocate_vc_save_buffers(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) for (i = 0; i < ARRAY_SIZE(vc_caps); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int len, pos = pci_find_ext_capability(dev, vc_caps[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) len = pci_vc_do_save_buffer(dev, pos, NULL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (pci_add_ext_cap_save_buffer(dev, vc_caps[i].id, len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pci_err(dev, "unable to preallocate %s save buffer\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) vc_caps[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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