^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support routines for initializing a PCI subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Extruded from code written by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Dave Rusling (david.rusling@reo.mts.dec.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * David Mosberger (davidm@cs.arizona.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * David Miller (davem@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * PCI-PCI bridges cleanup, sorted resource allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Converted to allocation in 3 passes, which gives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * tighter packing. Prefetchable range support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned int pci_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) EXPORT_SYMBOL_GPL(pci_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct pci_dev_resource {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) resource_size_t start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) resource_size_t end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) resource_size_t add_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) resource_size_t min_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void free_list(struct list_head *head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct pci_dev_resource *dev_res, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) list_for_each_entry_safe(dev_res, tmp, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) list_del(&dev_res->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) kfree(dev_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * add_to_list() - Add a new resource tracker to the list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @head: Head of the list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @dev: Device to which the resource belongs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @res: Resource to be tracked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @add_size: Additional size to be optionally added to the resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @min_align: Minimum memory window alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int add_to_list(struct list_head *head, struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct resource *res, resource_size_t add_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) resource_size_t min_align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct pci_dev_resource *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) tmp->res = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) tmp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) tmp->start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) tmp->end = res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) tmp->flags = res->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) tmp->add_size = add_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) tmp->min_align = min_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) list_add(&tmp->list, head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void remove_from_list(struct list_head *head, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct pci_dev_resource *dev_res, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) list_for_each_entry_safe(dev_res, tmp, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (dev_res->res == res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) list_del(&dev_res->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) kfree(dev_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct pci_dev_resource *dev_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) list_for_each_entry(dev_res, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (dev_res->res == res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return dev_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static resource_size_t get_res_add_size(struct list_head *head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct pci_dev_resource *dev_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_res = res_to_dev_res(head, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return dev_res ? dev_res->add_size : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static resource_size_t get_res_add_align(struct list_head *head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct pci_dev_resource *dev_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_res = res_to_dev_res(head, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return dev_res ? dev_res->min_align : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Sort resources by alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) for (i = 0; i < PCI_NUM_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pci_dev_resource *dev_res, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) resource_size_t r_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct list_head *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) r = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (r->flags & IORESOURCE_PCI_FIXED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!(r->flags) || r->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) r_align = pci_resource_alignment(dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!r_align) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) i, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) panic("%s: kzalloc() failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tmp->res = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tmp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Fallback is smallest one or list is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) n = head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) list_for_each_entry(dev_res, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) resource_size_t align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) align = pci_resource_alignment(dev_res->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_res->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (r_align > align) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) n = &dev_res->list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Insert it just before n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) list_add_tail(&tmp->list, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u16 class = dev->class >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Don't touch classless devices or host bridges or IOAPICs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Don't touch IOAPIC devices already enabled by firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (class == PCI_CLASS_SYSTEM_PIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pci_read_config_word(dev, PCI_COMMAND, &command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pdev_sort_resources(dev, head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline void reset_resource(struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) res->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) res->end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) res->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * reassign_resources_sorted() - Satisfy any additional resource requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @realloc_head: Head of the list tracking requests requiring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * additional resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @head: Head of the list tracking requests with allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * Walk through each element of the realloc_head and try to procure additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * resources for the element, provided the element is in the head list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void reassign_resources_sorted(struct list_head *realloc_head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct list_head *head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct pci_dev_resource *add_res, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct pci_dev_resource *dev_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) resource_size_t add_size, align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) bool found_match = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) res = add_res->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Skip resource that has been reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!res->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Skip this resource if not found in head list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) list_for_each_entry(dev_res, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (dev_res->res == res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) found_match = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!found_match) /* Just skip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) idx = res - &add_res->dev->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) add_size = add_res->add_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) align = add_res->min_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!resource_size(res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) res->start = align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) res->end = res->start + add_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (pci_assign_resource(add_res->dev, idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) reset_resource(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) res->flags |= add_res->flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (pci_reassign_resource(add_res->dev, idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) add_size, align))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pci_info(add_res->dev, "failed to add %llx res[%d]=%pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) (unsigned long long) add_size, idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) list_del(&add_res->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) kfree(add_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * assign_requested_resources_sorted() - Satisfy resource requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * @head: Head of the list tracking requests for resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @fail_head: Head of the list tracking requests that could not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Satisfy resource requests of each element in the list. Add requests that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * could not be satisfied to the failed_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void assign_requested_resources_sorted(struct list_head *head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct list_head *fail_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct pci_dev_resource *dev_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) list_for_each_entry(dev_res, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) res = dev_res->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) idx = res - &dev_res->dev->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (resource_size(res) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pci_assign_resource(dev_res->dev, idx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (fail_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * If the failed resource is a ROM BAR and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * it will be enabled later, don't add it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * to the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!((idx == PCI_ROM_RESOURCE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) (!(res->flags & IORESOURCE_ROM_ENABLE))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) add_to_list(fail_head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_res->dev, res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0 /* don't care */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0 /* don't care */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) reset_resource(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct pci_dev_resource *fail_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned long mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Check failed type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) list_for_each_entry(fail_res, fail_head, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mask |= fail_res->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * One pref failed resource will set IORESOURCE_MEM, as we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * allocate pref in non-pref range. Will release all assigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * non-pref sibling resources according to that bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static bool pci_need_to_release(unsigned long mask, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (res->flags & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return !!(mask & IORESOURCE_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Check pref at first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (res->flags & IORESOURCE_PREFETCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (mask & IORESOURCE_PREFETCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Count pref if its parent is non-pref */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) else if ((mask & IORESOURCE_MEM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) !(res->parent->flags & IORESOURCE_PREFETCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (res->flags & IORESOURCE_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return !!(mask & IORESOURCE_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return false; /* Should not get here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static void __assign_resources_sorted(struct list_head *head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct list_head *realloc_head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct list_head *fail_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Should not assign requested resources at first. They could be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * adjacent, so later reassign can not reallocate them one by one in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * parent resource window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Try to assign requested + add_size at beginning. If could do that,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * could get out early. If could not do that, we still try to assign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * requested at first, then try to reassign add_size for some resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Separate three resource type checking if we need to release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * assigned resource after requested + add_size try.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * 1. If IO port assignment fails, will release assigned IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * 2. If pref MMIO assignment fails, release assigned pref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * MMIO. If assigned pref MMIO's parent is non-pref MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * and non-pref MMIO assignment fails, will release that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * assigned pref MMIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * 3. If non-pref MMIO assignment fails or pref MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * assignment fails, will release assigned non-pref MMIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) LIST_HEAD(save_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) LIST_HEAD(local_fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct pci_dev_resource *save_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned long fail_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) resource_size_t add_align, align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Check if optional add_size is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!realloc_head || list_empty(realloc_head))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) goto requested_and_reassign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Save original start, end, flags etc at first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) list_for_each_entry(dev_res, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) free_list(&save_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) goto requested_and_reassign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Update res in head list with add_size in realloc_head list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) list_for_each_entry_safe(dev_res, tmp_res, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_res->res->end += get_res_add_size(realloc_head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_res->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * There are two kinds of additional resources in the list:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * 1. bridge resource -- IORESOURCE_STARTALIGN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Here just fix the additional alignment for bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) add_align = get_res_add_align(realloc_head, dev_res->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * The "head" list is sorted by alignment so resources with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * bigger alignment will be assigned first. After we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * change the alignment of a dev_res in "head" list, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * need to reorder the list by alignment to make it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * consistent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (add_align > dev_res->res->start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) resource_size_t r_size = resource_size(dev_res->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_res->res->start = add_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_res->res->end = add_align + r_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) list_for_each_entry(dev_res2, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) align = pci_resource_alignment(dev_res2->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_res2->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (add_align > align) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) list_move_tail(&dev_res->list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) &dev_res2->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Try updated head list with add_size added */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) assign_requested_resources_sorted(head, &local_fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* All assigned with add_size? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (list_empty(&local_fail_head)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Remove head list from realloc_head list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) list_for_each_entry(dev_res, head, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) remove_from_list(realloc_head, dev_res->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) free_list(&save_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) free_list(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Check failed type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) fail_type = pci_fail_res_type_mask(&local_fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Remove not need to be released assigned res from head list etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) list_for_each_entry_safe(dev_res, tmp_res, head, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (dev_res->res->parent &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) !pci_need_to_release(fail_type, dev_res->res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Remove it from realloc_head list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) remove_from_list(realloc_head, dev_res->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) remove_from_list(&save_head, dev_res->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) list_del(&dev_res->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) kfree(dev_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) free_list(&local_fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Release assigned resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) list_for_each_entry(dev_res, head, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (dev_res->res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) release_resource(dev_res->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Restore start/end/flags from saved list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) list_for_each_entry(save_res, &save_head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct resource *res = save_res->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) res->start = save_res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) res->end = save_res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) res->flags = save_res->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) free_list(&save_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) requested_and_reassign:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Satisfy the must-have resource requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) assign_requested_resources_sorted(head, fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Try to satisfy any additional optional resource requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (realloc_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) reassign_resources_sorted(realloc_head, head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) free_list(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static void pdev_assign_resources_sorted(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct list_head *add_head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct list_head *fail_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) __dev_sort_resources(dev, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) __assign_resources_sorted(&head, add_head, fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void pbus_assign_resources_sorted(const struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct list_head *realloc_head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct list_head *fail_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) list_for_each_entry(dev, &bus->devices, bus_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __dev_sort_resources(dev, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) __assign_resources_sorted(&head, realloc_head, fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) void pci_setup_cardbus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct pci_dev *bridge = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pci_info(bridge, "CardBus bridge to %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) &bus->busn_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) res = bus->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pcibios_resource_to_bus(bridge->bus, ®ion, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (res->flags & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * The IO resource is allocated a range twice as large as it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * would normally need. This allows us to set both IO regs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) pci_info(bridge, " bridge window %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) region.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) region.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) res = bus->resource[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pcibios_resource_to_bus(bridge->bus, ®ion, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (res->flags & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pci_info(bridge, " bridge window %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) region.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) region.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) res = bus->resource[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pcibios_resource_to_bus(bridge->bus, ®ion, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (res->flags & IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pci_info(bridge, " bridge window %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) region.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) region.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) res = bus->resource[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pcibios_resource_to_bus(bridge->bus, ®ion, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (res->flags & IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pci_info(bridge, " bridge window %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) region.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) region.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) EXPORT_SYMBOL(pci_setup_cardbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * Initialize bridges with base/limit values we have collected. PCI-to-PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * Bridge Architecture Specification rev. 1.1 (1998) requires that if there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * are no I/O ports or memory behind the bridge, the corresponding range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * must be turned off by writing base value greater than limit to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * bridge's base/limit registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * Note: care must be taken when updating I/O base/limit registers of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * bridges which support 32-bit I/O. This update requires two config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * writes, so it's quite possible that an I/O window of the bridge will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * have some undesirable address (e.g. 0) after the first write. Ditto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * 64-bit prefetchable MMIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void pci_setup_bridge_io(struct pci_dev *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned long io_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u8 io_base_lo, io_limit_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u16 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u32 io_upper16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) io_mask = PCI_IO_RANGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (bridge->io_window_1k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) io_mask = PCI_IO_1K_RANGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Set up the top and bottom of the PCI I/O segment for this bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pcibios_resource_to_bus(bridge->bus, ®ion, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (res->flags & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pci_read_config_word(bridge, PCI_IO_BASE, &l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) io_base_lo = (region.start >> 8) & io_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) io_limit_lo = (region.end >> 8) & io_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) l = ((u16) io_limit_lo << 8) | io_base_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Set up upper 16 bits of I/O base/limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) pci_info(bridge, " bridge window %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Clear upper 16 bits of I/O base/limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) io_upper16 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) l = 0x00f0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Temporarily disable the I/O range before updating PCI_IO_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Update lower 16 bits of I/O base/limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) pci_write_config_word(bridge, PCI_IO_BASE, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Update upper 16 bits of I/O base/limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static void pci_setup_bridge_mmio(struct pci_dev *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Set up the top and bottom of the PCI Memory segment for this bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pcibios_resource_to_bus(bridge->bus, ®ion, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (res->flags & IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) l = (region.start >> 16) & 0xfff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) l |= region.end & 0xfff00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) pci_info(bridge, " bridge window %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) l = 0x0000fff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u32 l, bu, lu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * Clear out the upper 32 bits of PREF limit. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * PREF range, which is ok.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Set up PREF base/limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) bu = lu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pcibios_resource_to_bus(bridge->bus, ®ion, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (res->flags & IORESOURCE_PREFETCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) l = (region.start >> 16) & 0xfff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) l |= region.end & 0xfff00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (res->flags & IORESOURCE_MEM_64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) bu = upper_32_bits(region.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) lu = upper_32_bits(region.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) pci_info(bridge, " bridge window %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) l = 0x0000fff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Set the upper 32 bits of PREF base & limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct pci_dev *bridge = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pci_info(bridge, "PCI bridge to %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) &bus->busn_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (type & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pci_setup_bridge_io(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (type & IORESOURCE_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pci_setup_bridge_mmio(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (type & IORESOURCE_PREFETCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) pci_setup_bridge_mmio_pref(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) void pci_setup_bridge(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) IORESOURCE_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pcibios_setup_bridge(bus, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) __pci_setup_bridge(bus, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (pci_claim_resource(bridge, i) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return 0; /* Claimed the window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (!pci_bus_clip_resource(bridge, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return -EINVAL; /* Clipping didn't change anything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) case PCI_BRIDGE_IO_WINDOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pci_setup_bridge_io(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) case PCI_BRIDGE_MEM_WINDOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) pci_setup_bridge_mmio(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) case PCI_BRIDGE_PREF_MEM_WINDOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) pci_setup_bridge_mmio_pref(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (pci_claim_resource(bridge, i) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return 0; /* Claimed a smaller window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * Check whether the bridge supports optional I/O and prefetchable memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * ranges. If not, the respective base/limit registers must be read-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * and read as 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static void pci_bridge_check_ranges(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct pci_dev *bridge = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct resource *b_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) b_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) b_res->flags |= IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (bridge->io_window) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) b_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) b_res->flags |= IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (bridge->pref_window) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) b_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (bridge->pref_64_window) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) b_res->flags |= IORESOURCE_MEM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PCI_PREF_RANGE_TYPE_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * Helper function for sizing routines. Assigned resources have non-NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * parent resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * Return first unassigned resource of the correct type. If there is none,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * return first assigned resource of the correct type. If none of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * above, return NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * Returning an assigned resource of the correct type allows the caller to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * distinguish between already assigned and no resource of the correct type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static struct resource *find_bus_resource_of_type(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) unsigned long type_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) unsigned long type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct resource *r, *r_assigned = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) pci_bus_for_each_resource(bus, r, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (r == &ioport_resource || r == &iomem_resource)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (r && (r->flags & type_mask) == type && !r->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (r && (r->flags & type_mask) == type && !r_assigned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) r_assigned = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return r_assigned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static resource_size_t calculate_iosize(resource_size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) resource_size_t min_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) resource_size_t size1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) resource_size_t add_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) resource_size_t children_add_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) resource_size_t old_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) resource_size_t align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (size < min_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) size = min_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (old_size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) old_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * struct pci_bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) size = (size & 0xff) + ((size & ~0xffUL) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) size = size + size1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (size < old_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) size = old_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) size = ALIGN(max(size, add_size) + children_add_size, align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static resource_size_t calculate_memsize(resource_size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) resource_size_t min_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) resource_size_t add_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) resource_size_t children_add_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) resource_size_t old_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) resource_size_t align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (size < min_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) size = min_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (old_size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) old_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (size < old_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) size = old_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) size = ALIGN(max(size, add_size) + children_add_size, align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) unsigned long type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) resource_size_t align = 1, arch_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (type & IORESOURCE_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) align = PCI_P2P_DEFAULT_MEM_ALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) else if (type & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * Per spec, I/O windows are 4K-aligned, but some bridges have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * an extension to support 1K alignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (bus->self && bus->self->io_window_1k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) align = PCI_P2P_DEFAULT_IO_ALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) arch_align = pcibios_window_alignment(bus, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return max(align, arch_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * pbus_size_io() - Size the I/O window of a given bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * @bus: The bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * @min_size: The minimum I/O window that must be allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * @add_size: Additional optional I/O window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * @realloc_head: Track the additional I/O window on this list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * devices are limited to 256 bytes. We must be careful with the ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * aliasing though.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) resource_size_t add_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct list_head *realloc_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct resource *b_res = find_bus_resource_of_type(bus, IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) IORESOURCE_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) resource_size_t size = 0, size0 = 0, size1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) resource_size_t children_add_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) resource_size_t min_align, align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (!b_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* If resource is already assigned, nothing more to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (b_res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) min_align = window_alignment(bus, IORESOURCE_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) for (i = 0; i < PCI_NUM_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct resource *r = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) unsigned long r_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (r->parent || !(r->flags & IORESOURCE_IO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) r_size = resource_size(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (r_size < 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Might be re-aligned for ISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) size += r_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) size1 += r_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) align = pci_resource_alignment(dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (align > min_align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) min_align = align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (realloc_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) children_add_size += get_res_add_size(realloc_head, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) size0 = calculate_iosize(size, min_size, size1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) resource_size(b_res), min_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) calculate_iosize(size, min_size, size1, add_size, children_add_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) resource_size(b_res), min_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (!size0 && !size1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (bus->self && (b_res->start || b_res->end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) b_res, &bus->busn_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) b_res->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) b_res->start = min_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) b_res->end = b_res->start + size0 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) b_res->flags |= IORESOURCE_STARTALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (bus->self && size1 > size0 && realloc_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) add_to_list(realloc_head, bus->self, b_res, size1-size0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) min_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) b_res, &bus->busn_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) (unsigned long long) size1 - size0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) int max_order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) resource_size_t align = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) resource_size_t min_align = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) for (order = 0; order <= max_order; order++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) resource_size_t align1 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) align1 <<= (order + 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (!align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) min_align = align1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) else if (ALIGN(align + min_align, min_align) < align1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) min_align = align1 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) align += aligns[order];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return min_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * pbus_size_mem() - Size the memory window of a given bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * @bus: The bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * @mask: Mask the resource flag, then compare it with type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * @type: The type of free resource from bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * @type2: Second match type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * @type3: Third match type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * @min_size: The minimum memory window that must be allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * @add_size: Additional optional memory window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * @realloc_head: Track the additional memory window on this list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * Calculate the size of the bus and minimal alignment which guarantees
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * that all child resources fit in this size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * Return -ENOSPC if there's no available bus resource of the desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * type. Otherwise, set the bus resource start/end to indicate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * required size, add things to realloc_head (if supplied), and return 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) unsigned long type, unsigned long type2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) unsigned long type3, resource_size_t min_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) resource_size_t add_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct list_head *realloc_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) resource_size_t min_align, align, size, size0, size1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) int order, max_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct resource *b_res = find_bus_resource_of_type(bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) mask | IORESOURCE_PREFETCH, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) resource_size_t children_add_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) resource_size_t children_add_align = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) resource_size_t add_align = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (!b_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* If resource is already assigned, nothing more to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (b_res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) memset(aligns, 0, sizeof(aligns));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) max_order = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) for (i = 0; i < PCI_NUM_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct resource *r = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) resource_size_t r_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ((r->flags & mask) != type &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) (r->flags & mask) != type2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) (r->flags & mask) != type3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) r_size = resource_size(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #ifdef CONFIG_PCI_IOV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* Put SRIOV requested res to the optional list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (realloc_head && i >= PCI_IOV_RESOURCES &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) i <= PCI_IOV_RESOURCE_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) add_align = max(pci_resource_alignment(dev, r), add_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) r->end = r->start - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) children_add_size += r_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * aligns[0] is for 1MB (since bridge memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * windows are always at least 1MB aligned), so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * keep "order" from being negative for smaller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) align = pci_resource_alignment(dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) order = __ffs(align) - 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (order < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) order = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (order >= ARRAY_SIZE(aligns)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) i, r, (unsigned long long) align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) r->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) size += max(r_size, align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * Exclude ranges with size > align from calculation of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * the alignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (r_size <= align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) aligns[order] += align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (order > max_order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) max_order = order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (realloc_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) children_add_size += get_res_add_size(realloc_head, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) children_add_align = get_res_add_align(realloc_head, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) add_align = max(add_align, children_add_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) min_align = calculate_mem_align(aligns, max_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) min_align = max(min_align, window_alignment(bus, b_res->flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) add_align = max(min_align, add_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) calculate_memsize(size, min_size, add_size, children_add_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) resource_size(b_res), add_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (!size0 && !size1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (bus->self && (b_res->start || b_res->end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) b_res, &bus->busn_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) b_res->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) b_res->start = min_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) b_res->end = size0 + min_align - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) b_res->flags |= IORESOURCE_STARTALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (bus->self && size1 > size0 && realloc_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) b_res, &bus->busn_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) (unsigned long long) (size1 - size0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) (unsigned long long) add_align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) unsigned long pci_cardbus_resource_alignment(struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (res->flags & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return pci_cardbus_io_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (res->flags & IORESOURCE_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return pci_cardbus_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static void pci_bus_size_cardbus(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct list_head *realloc_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct pci_dev *bridge = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct resource *b_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (b_res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) goto handle_b_res_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * Reserve some resources for CardBus. We reserve a fixed amount
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * of bus space for CardBus bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) b_res->start = pci_cardbus_io_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) b_res->end = b_res->start + pci_cardbus_io_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (realloc_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) b_res->end -= pci_cardbus_io_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) pci_cardbus_io_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) handle_b_res_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (b_res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) goto handle_b_res_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) b_res->start = pci_cardbus_io_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) b_res->end = b_res->start + pci_cardbus_io_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (realloc_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) b_res->end -= pci_cardbus_io_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) pci_cardbus_io_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) handle_b_res_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* MEM1 must not be pref MMIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* Check whether prefetchable memory is supported by this bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (b_res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) goto handle_b_res_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * If we have prefetchable memory support, allocate two regions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * Otherwise, allocate one region of twice the size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) b_res->start = pci_cardbus_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) b_res->end = b_res->start + pci_cardbus_mem_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) IORESOURCE_STARTALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (realloc_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) b_res->end -= pci_cardbus_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) add_to_list(realloc_head, bridge, b_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) pci_cardbus_mem_size, pci_cardbus_mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* Reduce that to half */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) b_res_3_size = pci_cardbus_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) handle_b_res_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (b_res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) goto handle_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) b_res->start = pci_cardbus_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) b_res->end = b_res->start + b_res_3_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (realloc_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) b_res->end -= b_res_3_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) add_to_list(realloc_head, bridge, b_res, b_res_3_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) pci_cardbus_mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) handle_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) unsigned long mask, prefmask, type2 = 0, type3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) resource_size_t additional_io_size = 0, additional_mmio_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) additional_mmio_pref_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct resource *pref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct pci_host_bridge *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) int hdr_type, i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct pci_bus *b = dev->subordinate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (!b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) switch (dev->hdr_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) case PCI_HEADER_TYPE_CARDBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) pci_bus_size_cardbus(b, realloc_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) case PCI_HEADER_TYPE_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) __pci_bus_size_bridges(b, realloc_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* The root bus? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (pci_is_root_bus(bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) host = to_pci_host_bridge(bus->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (!host->size_windows)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) pci_bus_for_each_resource(bus, pref, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (pref && (pref->flags & IORESOURCE_PREFETCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) hdr_type = -1; /* Intentionally invalid - not a PCI device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) pref = &bus->self->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) hdr_type = bus->self->hdr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) switch (hdr_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) case PCI_HEADER_TYPE_CARDBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* Don't size CardBuses yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) case PCI_HEADER_TYPE_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) pci_bridge_check_ranges(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (bus->self->is_hotplug_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) additional_io_size = pci_hotplug_io_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) additional_mmio_size = pci_hotplug_mmio_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) additional_mmio_pref_size = pci_hotplug_mmio_pref_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) additional_io_size, realloc_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * If there's a 64-bit prefetchable MMIO window, compute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * the size required to put all 64-bit prefetchable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * resources in it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) mask = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (pref && (pref->flags & IORESOURCE_MEM_64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) prefmask |= IORESOURCE_MEM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ret = pbus_size_mem(bus, prefmask, prefmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) prefmask, prefmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) realloc_head ? 0 : additional_mmio_pref_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) additional_mmio_pref_size, realloc_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * If successful, all non-prefetchable resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * and any 32-bit prefetchable resources will go in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * the non-prefetchable window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) mask = prefmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) type2 = prefmask & ~IORESOURCE_MEM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) type3 = prefmask & ~IORESOURCE_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * If there is no 64-bit prefetchable window, compute the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * size required to put all prefetchable resources in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * 32-bit prefetchable window (if there is one).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (!type2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) prefmask &= ~IORESOURCE_MEM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ret = pbus_size_mem(bus, prefmask, prefmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) prefmask, prefmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) realloc_head ? 0 : additional_mmio_pref_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) additional_mmio_pref_size, realloc_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * If successful, only non-prefetchable resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * will go in the non-prefetchable window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) mask = prefmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) additional_mmio_size += additional_mmio_pref_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) type2 = type3 = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * Compute the size required to put everything else in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * non-prefetchable window. This includes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * - all non-prefetchable resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * - 32-bit prefetchable resources if there's a 64-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * prefetchable window or no prefetchable window at all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * - 64-bit prefetchable resources if there's no prefetchable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * window at all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * Note that the strategy in __pci_assign_resource() must match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * that used here. Specifically, we cannot put a 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * prefetchable resource in a 64-bit prefetchable window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) realloc_head ? 0 : additional_mmio_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) additional_mmio_size, realloc_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) void pci_bus_size_bridges(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) __pci_bus_size_bridges(bus, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) EXPORT_SYMBOL(pci_bus_size_bridges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) struct resource *parent_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) IORESOURCE_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) pci_bus_for_each_resource(b, parent_r, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (!parent_r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if ((r->flags & mask) == (parent_r->flags & mask) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) resource_contains(parent_r, r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) request_resource(parent_r, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) * skipped by pbus_assign_resources_sorted().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static void pdev_assign_fixed_resources(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) for (i = 0; i < PCI_NUM_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) struct pci_bus *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct resource *r = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) b = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) while (b && !r->parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) assign_fixed_resource_on_bus(b, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) b = b->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) void __pci_bus_assign_resources(const struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) struct list_head *realloc_head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct list_head *fail_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) struct pci_bus *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) pbus_assign_resources_sorted(bus, realloc_head, fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) pdev_assign_fixed_resources(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) b = dev->subordinate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (!b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) __pci_bus_assign_resources(b, realloc_head, fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) switch (dev->hdr_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) case PCI_HEADER_TYPE_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (!pci_is_enabled(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) pci_setup_bridge(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) case PCI_HEADER_TYPE_CARDBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) pci_setup_cardbus(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) pci_domain_nr(b), b->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) void pci_bus_assign_resources(const struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) __pci_bus_assign_resources(bus, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) EXPORT_SYMBOL(pci_bus_assign_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static void pci_claim_device_resources(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) struct resource *r = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (!r->flags || r->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) pci_claim_resource(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static void pci_claim_bridge_resources(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) struct resource *r = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (!r->flags || r->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) pci_claim_bridge_resource(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static void pci_bus_allocate_dev_resources(struct pci_bus *b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) struct pci_bus *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) list_for_each_entry(dev, &b->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) pci_claim_device_resources(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) child = dev->subordinate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) pci_bus_allocate_dev_resources(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static void pci_bus_allocate_resources(struct pci_bus *b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct pci_bus *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) * Carry out a depth-first search on the PCI bus tree to allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * bridge apertures. Read the programmed bridge bases and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * recursively claim the respective bridge resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (b->self) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) pci_read_bridge_bases(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) pci_claim_bridge_resources(b->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) list_for_each_entry(child, &b->children, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) pci_bus_allocate_resources(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) void pci_bus_claim_resources(struct pci_bus *b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) pci_bus_allocate_resources(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) pci_bus_allocate_dev_resources(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) EXPORT_SYMBOL(pci_bus_claim_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) struct list_head *add_head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct list_head *fail_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) struct pci_bus *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) pdev_assign_resources_sorted((struct pci_dev *)bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) add_head, fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) b = bridge->subordinate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (!b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) __pci_bus_assign_resources(b, add_head, fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) switch (bridge->class >> 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) case PCI_CLASS_BRIDGE_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) pci_setup_bridge(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) case PCI_CLASS_BRIDGE_CARDBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) pci_setup_cardbus(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) pci_domain_nr(b), b->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define PCI_RES_TYPE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) IORESOURCE_MEM_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static void pci_bridge_release_resources(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) unsigned long type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct pci_dev *dev = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) unsigned old_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) struct resource *b_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) int idx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) * 1. If IO port assignment fails, release bridge IO port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * 2. If non pref MMIO assignment fails, release bridge nonpref MMIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * release bridge pref MMIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) * 4. If pref MMIO assignment fails, and bridge pref is 32bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * release bridge pref MMIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * 5. If pref MMIO assignment fails, and bridge pref is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * assigned, release bridge nonpref MMIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (type & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) else if (!(type & IORESOURCE_PREFETCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) idx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) else if ((type & IORESOURCE_MEM_64) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) (b_res[2].flags & IORESOURCE_MEM_64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) idx = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) (b_res[2].flags & IORESOURCE_PREFETCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) idx = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) idx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) r = &b_res[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (!r->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* If there are children, release them all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) release_child_resources(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (!release_resource(r)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) type = old_flags = r->flags & PCI_RES_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) pci_info(dev, "resource %d %pR released\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) PCI_BRIDGE_RESOURCES + idx, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /* Keep the old size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) r->end = resource_size(r) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) r->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) r->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* Avoiding touch the one without PREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (type & IORESOURCE_PREFETCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) type = IORESOURCE_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) __pci_setup_bridge(bus, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) /* For next child res under same bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) r->flags = old_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) enum release_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) leaf_only,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) whole_subtree,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * Try to release PCI bridge resources from leaf bridge, so we can allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) * a larger window later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static void pci_bus_release_bridge_resources(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) unsigned long type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) enum release_type rel_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) bool is_leaf_bridge = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) struct pci_bus *b = dev->subordinate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (!b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) is_leaf_bridge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (rel_type == whole_subtree)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) pci_bus_release_bridge_resources(b, type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) whole_subtree);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if (pci_is_root_bus(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if ((rel_type == whole_subtree) || is_leaf_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) pci_bridge_release_resources(bus, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) static void pci_bus_dump_res(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) pci_bus_for_each_resource(bus, res, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (!res || !res->end || !res->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) dev_info(&bus->dev, "resource %d %pR\n", i, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) static void pci_bus_dump_resources(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) struct pci_bus *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) pci_bus_dump_res(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) b = dev->subordinate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (!b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) pci_bus_dump_resources(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) static int pci_bus_get_depth(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) int depth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) struct pci_bus *child_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) list_for_each_entry(child_bus, &bus->children, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) ret = pci_bus_get_depth(child_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (ret + 1 > depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) depth = ret + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) return depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) * -1: undefined, will auto detect later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * 0: disabled by user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * 1: disabled by auto detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) * 2: enabled by user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) * 3: enabled by auto detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) enum enable_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) undefined = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) user_disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) auto_disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) user_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) auto_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) static enum enable_type pci_realloc_enable = undefined;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) void __init pci_realloc_get_opt(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (!strncmp(str, "off", 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) pci_realloc_enable = user_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) else if (!strncmp(str, "on", 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) pci_realloc_enable = user_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static bool pci_realloc_enabled(enum enable_type enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) return enable >= user_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static int iov_resources_unassigned(struct pci_dev *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) bool *unassigned = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct resource *r = &dev->resource[i + PCI_IOV_RESOURCES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) /* Not assigned or rejected by kernel? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (!r->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) pcibios_resource_to_bus(dev->bus, ®ion, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (!region.start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) *unassigned = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) return 1; /* Return early from pci_walk_bus() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static enum enable_type pci_realloc_detect(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) enum enable_type enable_local)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) bool unassigned = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) struct pci_host_bridge *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (enable_local != undefined)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) return enable_local;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) host = pci_find_host_bridge(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (host->preserve_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) return auto_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if (unassigned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) return auto_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) return enable_local;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) static enum enable_type pci_realloc_detect(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) enum enable_type enable_local)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) return enable_local;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) * First try will not touch PCI bridge res.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) * Second and later try will clear small leaf bridge res.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * Will stop till to the max depth if can not find good one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) LIST_HEAD(realloc_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) /* List of resources that want additional resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) struct list_head *add_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) int tried_times = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) enum release_type rel_type = leaf_only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) LIST_HEAD(fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) struct pci_dev_resource *fail_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) int pci_try_num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) enum enable_type enable_local;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) /* Don't realloc if asked to do so */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) enable_local = pci_realloc_detect(bus, pci_realloc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (pci_realloc_enabled(enable_local)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) int max_depth = pci_bus_get_depth(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) pci_try_num = max_depth + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) max_depth, pci_try_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) * Last try will use add_list, otherwise will try good to have as must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) * have, so can realloc parent bridge resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) if (tried_times + 1 == pci_try_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) add_list = &realloc_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) * Depth first, calculate sizes and alignments of all subordinate buses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) __pci_bus_size_bridges(bus, add_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) /* Depth last, allocate resources and update the hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) __pci_bus_assign_resources(bus, add_list, &fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) if (add_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) BUG_ON(!list_empty(add_list));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) tried_times++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* Any device complain? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (list_empty(&fail_head))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) goto dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (tried_times >= pci_try_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (enable_local == undefined)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) else if (enable_local == auto_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) free_list(&fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) goto dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) dev_info(&bus->dev, "No. %d try to assign unassigned res\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) tried_times + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) /* Third times and later will not check if it is leaf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) if ((tried_times + 1) > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) rel_type = whole_subtree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) * Try to release leaf bridge's resources that doesn't fit resource of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) * child device under that bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) list_for_each_entry(fail_res, &fail_head, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) pci_bus_release_bridge_resources(fail_res->dev->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) fail_res->flags & PCI_RES_TYPE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) rel_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) /* Restore size and flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) list_for_each_entry(fail_res, &fail_head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) struct resource *res = fail_res->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) res->start = fail_res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) res->end = fail_res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) res->flags = fail_res->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (pci_is_bridge(fail_res->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) idx = res - &fail_res->dev->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (idx >= PCI_BRIDGE_RESOURCES &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) idx <= PCI_BRIDGE_RESOURCE_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) res->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) free_list(&fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) dump:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) /* Dump the resource on buses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) pci_bus_dump_resources(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) void __init pci_assign_unassigned_resources(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) struct pci_bus *root_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) list_for_each_entry(root_bus, &pci_root_buses, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) pci_assign_unassigned_root_bus_resources(root_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) /* Make sure the root bridge has a companion ACPI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (ACPI_HANDLE(root_bus->bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static void adjust_bridge_window(struct pci_dev *bridge, struct resource *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) struct list_head *add_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) resource_size_t new_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) resource_size_t add_size, size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (!new_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) if (new_size > size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) add_size = new_size - size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) &add_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) } else if (new_size < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) add_size = size - new_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) pci_dbg(bridge, "bridge window %pR shrunken by %pa\n", res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) &add_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) res->end = res->start + new_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) remove_from_list(add_list, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static void pci_bus_distribute_available_resources(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) struct list_head *add_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) struct resource io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) struct resource mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) struct resource mmio_pref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) unsigned int normal_bridges = 0, hotplug_bridges = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) struct resource *io_res, *mmio_res, *mmio_pref_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) struct pci_dev *dev, *bridge = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) resource_size_t io_per_hp, mmio_per_hp, mmio_pref_per_hp, align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) io_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) mmio_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) mmio_pref_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) * The alignment of this bridge is yet to be considered, hence it must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) * be done now before extending its bridge window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) align = pci_resource_alignment(bridge, io_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (!io_res->parent && align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) io.start = min(ALIGN(io.start, align), io.end + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) align = pci_resource_alignment(bridge, mmio_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) if (!mmio_res->parent && align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) mmio.start = min(ALIGN(mmio.start, align), mmio.end + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) align = pci_resource_alignment(bridge, mmio_pref_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (!mmio_pref_res->parent && align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) mmio_pref.start = min(ALIGN(mmio_pref.start, align),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) mmio_pref.end + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) * Now that we have adjusted for alignment, update the bridge window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) * resources to fill as much remaining resource space as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) adjust_bridge_window(bridge, io_res, add_list, resource_size(&io));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) adjust_bridge_window(bridge, mmio_res, add_list, resource_size(&mmio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) adjust_bridge_window(bridge, mmio_pref_res, add_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) resource_size(&mmio_pref));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) * Calculate how many hotplug bridges and normal bridges there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) * are on this bus. We will distribute the additional available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) * resources between hotplug bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) for_each_pci_bridge(dev, bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (dev->is_hotplug_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) hotplug_bridges++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) normal_bridges++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) * There is only one bridge on the bus so it gets all available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * resources which it can then distribute to the possible hotplug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) * bridges below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) if (hotplug_bridges + normal_bridges == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) dev = list_first_entry(&bus->devices, struct pci_dev, bus_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if (dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) pci_bus_distribute_available_resources(dev->subordinate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) add_list, io, mmio, mmio_pref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) if (hotplug_bridges == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) * Calculate the total amount of extra resource space we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) * pass to bridges below this one. This is basically the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) * extra space reduced by the minimal required space for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) * non-hotplug bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) for_each_pci_bridge(dev, bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) resource_size_t used_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if (dev->is_hotplug_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) * Reduce the available resource space by what the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) * bridge and devices below it occupy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) res = &dev->resource[PCI_BRIDGE_IO_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) align = pci_resource_alignment(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) align = align ? ALIGN(io.start, align) - io.start : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) used_size = align + resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if (!res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) io.start = min(io.start + used_size, io.end + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) res = &dev->resource[PCI_BRIDGE_MEM_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) align = pci_resource_alignment(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) align = align ? ALIGN(mmio.start, align) - mmio.start : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) used_size = align + resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) if (!res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) mmio.start = min(mmio.start + used_size, mmio.end + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) res = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) align = pci_resource_alignment(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) align = align ? ALIGN(mmio_pref.start, align) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) mmio_pref.start : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) used_size = align + resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) if (!res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) mmio_pref.start = min(mmio_pref.start + used_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) mmio_pref.end + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) io_per_hp = div64_ul(resource_size(&io), hotplug_bridges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) mmio_per_hp = div64_ul(resource_size(&mmio), hotplug_bridges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) mmio_pref_per_hp = div64_ul(resource_size(&mmio_pref),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) hotplug_bridges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) * Go over devices on this bus and distribute the remaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) * resource space between hotplug bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) for_each_pci_bridge(dev, bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) struct pci_bus *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) b = dev->subordinate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (!b || !dev->is_hotplug_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) * Distribute available extra resources equally between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) * hotplug-capable downstream ports taking alignment into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) * account.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) io.end = io.start + io_per_hp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) mmio.end = mmio.start + mmio_per_hp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) mmio_pref.end = mmio_pref.start + mmio_pref_per_hp - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) pci_bus_distribute_available_resources(b, add_list, io, mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) mmio_pref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) io.start += io_per_hp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) mmio.start += mmio_per_hp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) mmio_pref.start += mmio_pref_per_hp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) struct list_head *add_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) struct resource available_io, available_mmio, available_mmio_pref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (!bridge->is_hotplug_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) /* Take the initial extra resources from the hotplug port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) available_io = bridge->resource[PCI_BRIDGE_IO_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) available_mmio = bridge->resource[PCI_BRIDGE_MEM_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) available_mmio_pref = bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) pci_bus_distribute_available_resources(bridge->subordinate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) add_list, available_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) available_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) available_mmio_pref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) struct pci_bus *parent = bridge->subordinate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) /* List of resources that want additional resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) LIST_HEAD(add_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) int tried_times = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) LIST_HEAD(fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) struct pci_dev_resource *fail_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) __pci_bus_size_bridges(parent, &add_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * Distribute remaining resources (if any) equally between hotplug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) * bridges below. This makes it possible to extend the hierarchy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) * later without running out of resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) pci_bridge_distribute_available_resources(bridge, &add_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) BUG_ON(!list_empty(&add_list));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) tried_times++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (list_empty(&fail_head))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) goto enable_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if (tried_times >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) /* Still fail, don't need to try more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) free_list(&fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) goto enable_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) tried_times + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) * Try to release leaf bridge's resources that aren't big enough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) * to contain child device resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) list_for_each_entry(fail_res, &fail_head, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) pci_bus_release_bridge_resources(fail_res->dev->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) fail_res->flags & PCI_RES_TYPE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) whole_subtree);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) /* Restore size and flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) list_for_each_entry(fail_res, &fail_head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) struct resource *res = fail_res->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) res->start = fail_res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) res->end = fail_res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) res->flags = fail_res->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) if (pci_is_bridge(fail_res->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) idx = res - &fail_res->dev->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (idx >= PCI_BRIDGE_RESOURCES &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) idx <= PCI_BRIDGE_RESOURCE_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) res->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) free_list(&fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) enable_all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) retval = pci_reenable_device(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) pci_set_master(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) struct pci_dev_resource *dev_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) struct pci_dev *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) LIST_HEAD(saved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) LIST_HEAD(added);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) LIST_HEAD(failed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) down_read(&pci_bus_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) /* Walk to the root hub, releasing bridge BARs when possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) next = bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) bridge = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) struct resource *res = &bridge->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) /* Ignore BARs which are still in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) if (res->child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) ret = add_to_list(&saved, bridge, res, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) pci_info(bridge, "BAR %d: releasing %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) i, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) if (res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) release_resource(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) res->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) res->end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) if (i == PCI_BRIDGE_RESOURCE_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) next = bridge->bus ? bridge->bus->self : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) } while (next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) if (list_empty(&saved)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) up_read(&pci_bus_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) __pci_bus_size_bridges(bridge->subordinate, &added);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) __pci_bridge_assign_resources(bridge, &added, &failed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) BUG_ON(!list_empty(&added));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) if (!list_empty(&failed)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ret = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) list_for_each_entry(dev_res, &saved, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) /* Skip the bridge we just assigned resources for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (bridge == dev_res->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) bridge = dev_res->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) pci_setup_bridge(bridge->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) free_list(&saved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) up_read(&pci_bus_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) /* Restore size and flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) list_for_each_entry(dev_res, &failed, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) struct resource *res = dev_res->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) res->start = dev_res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) res->end = dev_res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) res->flags = dev_res->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) free_list(&failed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) /* Revert to the old configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) list_for_each_entry(dev_res, &saved, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) struct resource *res = dev_res->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) bridge = dev_res->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) i = res - bridge->resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) res->start = dev_res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) res->end = dev_res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) res->flags = dev_res->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) pci_claim_resource(bridge, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) pci_setup_bridge(bridge->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) free_list(&saved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) up_read(&pci_bus_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) /* List of resources that want additional resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) LIST_HEAD(add_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) down_read(&pci_bus_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) for_each_pci_bridge(dev, bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) if (pci_has_subordinate(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) __pci_bus_size_bridges(dev->subordinate, &add_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) up_read(&pci_bus_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) __pci_bus_assign_resources(bus, &add_list, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) BUG_ON(!list_empty(&add_list));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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