^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file contains work-arounds for many known PCI hardware bugs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Devices present only on certain architectures (host bridges et cetera)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * should be handled in arch-specific code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Init/reset quirks for USB host controllers should be in the USB quirks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * file, where their drivers can use them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/nvme.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_data/x86/apple.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/switchtec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/dma.h> /* isa_dma_bridge_buggy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static ktime_t fixup_debug_start(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void (*fn)(struct pci_dev *dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (initcall_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void (*fn)(struct pci_dev *dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ktime_t delta, rettime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long long duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) rettime = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) delta = ktime_sub(rettime, calltime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) duration = (unsigned long long) ktime_to_ns(delta) >> 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (initcall_debug || duration > 10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pci_info(dev, "%pS took %lld usecs\n", fn, duration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct pci_fixup *end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ktime_t calltime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) for (; f < end; f++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if ((f->class == (u32) (dev->class >> f->class_shift) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) f->class == (u32) PCI_ANY_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) (f->vendor == dev->vendor ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) f->vendor == (u16) PCI_ANY_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) (f->device == dev->device ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) f->device == (u16) PCI_ANY_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void (*hook)(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) hook = offset_to_ptr(&f->hook_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) hook = f->hook;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) calltime = fixup_debug_start(dev, hook);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) hook(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) fixup_debug_report(dev, calltime, hook);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) extern struct pci_fixup __start_pci_fixups_early[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) extern struct pci_fixup __end_pci_fixups_early[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) extern struct pci_fixup __start_pci_fixups_header[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) extern struct pci_fixup __end_pci_fixups_header[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern struct pci_fixup __start_pci_fixups_final[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) extern struct pci_fixup __end_pci_fixups_final[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) extern struct pci_fixup __start_pci_fixups_enable[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) extern struct pci_fixup __end_pci_fixups_enable[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) extern struct pci_fixup __start_pci_fixups_resume[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) extern struct pci_fixup __end_pci_fixups_resume[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) extern struct pci_fixup __start_pci_fixups_resume_early[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) extern struct pci_fixup __end_pci_fixups_resume_early[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) extern struct pci_fixup __start_pci_fixups_suspend[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) extern struct pci_fixup __end_pci_fixups_suspend[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) extern struct pci_fixup __start_pci_fixups_suspend_late[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) extern struct pci_fixup __end_pci_fixups_suspend_late[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static bool pci_apply_fixup_final_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct pci_fixup *start, *end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) switch (pass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case pci_fixup_early:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) start = __start_pci_fixups_early;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) end = __end_pci_fixups_early;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) case pci_fixup_header:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) start = __start_pci_fixups_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) end = __end_pci_fixups_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case pci_fixup_final:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!pci_apply_fixup_final_quirks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) start = __start_pci_fixups_final;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) end = __end_pci_fixups_final;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case pci_fixup_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) start = __start_pci_fixups_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) end = __end_pci_fixups_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case pci_fixup_resume:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) start = __start_pci_fixups_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) end = __end_pci_fixups_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case pci_fixup_resume_early:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) start = __start_pci_fixups_resume_early;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) end = __end_pci_fixups_resume_early;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case pci_fixup_suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) start = __start_pci_fixups_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) end = __end_pci_fixups_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case pci_fixup_suspend_late:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) start = __start_pci_fixups_suspend_late;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) end = __end_pci_fixups_suspend_late;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* stupid compiler warning, you would think with an enum... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pci_do_fixups(dev, start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EXPORT_SYMBOL(pci_fixup_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int __init pci_apply_final_quirks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct pci_dev *dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 cls = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (pci_cache_line_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pci_apply_fixup_final_quirks = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) for_each_pci_dev(dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pci_fixup_device(pci_fixup_final, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * If arch hasn't set it explicitly yet, use the CLS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * value shared by all PCI devices. If there's a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * mismatch, fall back to the default value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!pci_cache_line_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!cls)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) cls = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!tmp || cls == tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) cls << 2, tmp << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pci_dfl_cache_line_size << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pci_cache_line_size = pci_dfl_cache_line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (!pci_cache_line_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pci_dfl_cache_line_size << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) fs_initcall_sync(pci_apply_final_quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Decoding should be disabled for a PCI device during BAR sizing to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * conflict. But doing so may cause problems on host bridge and perhaps other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * key system devices. For devices that need to have mmio decoding always-on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * we need to set the dev->mmio_always_on bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void quirk_mmio_always_on(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev->mmio_always_on = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * The Mellanox Tavor device gives false positive parity errors. Mark this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * device with a broken_parity_status to allow PCI scanning code to "skip"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * this now blacklisted device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void quirk_mellanox_tavor(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev->broken_parity_status = 1; /* This device gives false positives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Deal with broken BIOSes that neglect to enable passive release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * which can cause problems in combination with the 82441FX/PPro MTRRs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void quirk_passive_release(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct pci_dev *d = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned char dlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * We have to make sure a particular bit is set in the PIIX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * ISA bridge, so we have to go out and find it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pci_read_config_byte(d, 0x82, &dlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!(dlc & 1<<1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pci_info(d, "PIIX3: Enabling Passive Release\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dlc |= 1<<1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pci_write_config_byte(d, 0x82, dlc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * workaround but VIA don't answer queries. If you happen to have good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * contacts at VIA ask them for me please -- Alan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * This appears to be BIOS not version dependent. So presumably there is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * chipset level fix.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void quirk_isa_dma_hangs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!isa_dma_bridge_buggy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) isa_dma_bridge_buggy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pci_info(dev, "Activating ISA DMA hang workarounds\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * It's not totally clear which chipsets are the problematic ones. We know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * 82C586 and 82C596 variants are affected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * for some HT machines to use C4 w/o hanging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 pmbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u16 pm1a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pci_read_config_dword(dev, 0x40, &pmbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pmbase = pmbase & 0xff80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pm1a = inw(pmbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (pm1a & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) outw(0x10, pmbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Chipsets where PCI->PCI transfers vanish or hang */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void quirk_nopcipci(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pci_info(dev, "Disabling direct PCI/PCI transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pci_pci_problems |= PCIPCI_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void quirk_nopciamd(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pci_read_config_byte(dev, 0x08, &rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (rev == 0x13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Erratum 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pci_pci_problems |= PCIAGP_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Triton requires workarounds to be used by the drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void quirk_triton(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pci_info(dev, "Limiting direct PCI/PCI transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pci_pci_problems |= PCIPCI_TRITON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * VIA Apollo KT133 needs PCI latency patch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Made according to a Windows driver-based patch by George E. Breese;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * which Mr Breese based his work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Updated based on further information from the site and also on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * information provided by VIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void quirk_vialatency(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct pci_dev *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u8 busarb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Ok, we have a potential problem chipset here. Now see if we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * a buggy southbridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (p != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * thanks Dan Hollis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Check for buggy part revisions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (p->revision < 0x40 || p->revision > 0x42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (p == NULL) /* No problem parts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Check for buggy part revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (p->revision < 0x10 || p->revision > 0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * Ok we have the problem. Now set the PCI master grant to occur
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * every master grant. The apparent bug is that under high PCI load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * (quite common in Linux of course) you can get data loss when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * CPU is held off the bus for 3 bus master requests. This happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * to include the IDE controllers....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * VIA only apply this fix when an SB Live! is present but under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * both Linux and Windows this isn't enough, and we have seen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * corruption without SB Live! but with things like 3 UDMA IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * controllers. So we ignore that bit of the VIA recommendation..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pci_read_config_byte(dev, 0x76, &busarb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * Set bit 4 and bit 5 of byte 76 to 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * "Master priority rotation on every PCI master grant"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) busarb &= ~(1<<5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) busarb |= (1<<4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pci_write_config_byte(dev, 0x76, busarb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pci_info(dev, "Applying VIA southbridge workaround\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) pci_dev_put(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Must restore this on a resume from RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* VIA Apollo VP3 needs ETBF on BT848/878 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void quirk_viaetbf(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pci_info(dev, "Limiting direct PCI/PCI transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pci_pci_problems |= PCIPCI_VIAETBF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static void quirk_vsfx(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pci_info(dev, "Limiting direct PCI/PCI transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pci_pci_problems |= PCIPCI_VSFX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * space. Latency must be set to 0xA and Triton workaround applied too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * [Info kindly provided by ALi]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void quirk_alimagik(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pci_info(dev, "Limiting direct PCI/PCI transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Natoma has some interesting boundary conditions with Zoran stuff at least */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void quirk_natoma(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pci_info(dev, "Limiting direct PCI/PCI transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pci_pci_problems |= PCIPCI_NATOMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * This chip can cause PCI parity errors if config register 0xA0 is read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * while DMAs are occurring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static void quirk_citrine(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev->cfg_size = 0xA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * This chip can cause bus lockups if config addresses above 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * are read or written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static void quirk_nfp6000(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev->cfg_size = 0x600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static void quirk_extend_bar_to_page(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) for (i = 0; i < PCI_STD_NUM_BARS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct resource *r = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) r->end = PAGE_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) r->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) r->flags |= IORESOURCE_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pci_info(dev, "expanded BAR %d to page size: %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) i, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * If it's needed, re-allocate the region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void quirk_s3_64M(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct resource *r = &dev->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) r->flags |= IORESOURCE_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) r->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) r->end = 0x3ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct pci_bus_region bus_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct resource *res = dev->resource + pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (!region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) res->name = pci_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) res->flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) region &= ~(size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Convert from PCI bus to resource space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) bus_region.start = region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) bus_region.end = region + size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pcibios_bus_to_resource(dev->bus, res, &bus_region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * BAR0 should be 8 bytes; instead, it may be set to something like 8k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * (which conflicts w/ BAR1's memory range).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * CS553x's ISA PCI BARs may also be read-only (ref:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static void quirk_cs5536_vsa(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static char *name = "CS5536 ISA bridge";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (pci_resource_len(dev, 0) != 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) quirk_io(dev, 0, 8, name); /* SMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) quirk_io(dev, 1, 256, name); /* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) quirk_io(dev, 2, 64, name); /* MFGPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static void quirk_io_region(struct pci_dev *dev, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned size, int nr, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u16 region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct pci_bus_region bus_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct resource *res = dev->resource + nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) pci_read_config_word(dev, port, ®ion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) region &= ~(size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) res->name = pci_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) res->flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Convert from PCI bus to resource space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) bus_region.start = region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) bus_region.end = region + size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pcibios_bus_to_resource(dev->bus, res, &bus_region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (!pci_claim_resource(dev, nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * ATI Northbridge setups MCE the processor if you even read somewhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * between 0x3b0->0x3bb or read 0x3d3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static void quirk_ati_exploding_mce(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) request_region(0x3b0, 0x0C, "RadeonIGP");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) request_region(0x3d3, 0x01, "RadeonIGP");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * In the AMD NL platform, this device ([1022:7912]) has a class code of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * claim it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * But the dwc3 driver is a more specific driver for this device, and we'd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * prefer to use it instead of xhci. To prevent xhci from claiming the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * defines as "USB device (not host controller)". The dwc3 driver can then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * claim it based on its Vendor and Device ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static void quirk_amd_nl_class(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u32 class = pdev->class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Use "USB Device (not host controller)" class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) class, pdev->class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) quirk_amd_nl_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Synopsys USB 3.x host HAPS platform has a class code of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * devices should use dwc3-haps driver. Change these devices' class code to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static void quirk_synopsys_haps(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u32 class = pdev->class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) class, pdev->class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PCI_CLASS_SERIAL_USB_XHCI, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) quirk_synopsys_haps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * Let's make the southbridge information explicit instead of having to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * worry about people probing the ACPI areas, for example.. (Yes, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * happens, and if you read the wrong ACPI register it will put the machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * to sleep with no way of waking it up again. Bummer).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * ALI M7101: Two IO regions pointed to by words at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * 0xE0 (64 bytes of ACPI registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * 0xE2 (32 bytes of SMB registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static void quirk_ali7101_acpi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u32 devres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 mask, size, base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) pci_read_config_dword(dev, port, &devres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if ((devres & enable) != enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) mask = (devres >> 16) & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) base = devres & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) size = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned bit = size >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if ((bit & mask) == bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) size = bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * For now we only print it out. Eventually we'll want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * reserve it (at least if it's in the 0x1000+ range), but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * let's get enough confirmation reports first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) base &= -size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u32 devres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u32 mask, size, base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pci_read_config_dword(dev, port, &devres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if ((devres & enable) != enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) base = devres & 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) mask = (devres & 0x3f) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) size = 128 << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) unsigned bit = size >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if ((bit & mask) == bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) size = bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * For now we only print it out. Eventually we'll want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * reserve it, but let's get enough confirmation reports first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) base &= -size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * PIIX4 ACPI: Two IO regions pointed to by longwords at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * 0x40 (64 bytes of ACPI registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * 0x90 (16 bytes of SMB registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * and a few strange programmable PIIX4 device resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static void quirk_piix4_acpi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u32 res_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Device resource A has enables for some of the other ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) pci_read_config_dword(dev, 0x5c, &res_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Device resource D is just bitfields for static resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Device 12 enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (res_a & (1 << 29)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* Device 13 enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (res_a & (1 << 30)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define ICH_PMBASE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define ICH_ACPI_CNTL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define ICH4_ACPI_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define ICH6_ACPI_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define ICH4_GPIOBASE 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define ICH4_GPIO_CNTL 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define ICH4_GPIO_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define ICH6_GPIOBASE 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define ICH6_GPIO_CNTL 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define ICH6_GPIO_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * 0x58 (64 bytes of GPIO I/O space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u8 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * with low legacy (and fixed) ports. We don't know the decoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * priority and can't tell whether the legacy device or the one created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * here is really at that address. This happens on boards with broken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * BIOSes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (enable & ICH4_ACPI_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) "ICH4 ACPI/GPIO/TCO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (enable & ICH4_GPIO_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) "ICH4 GPIO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u8 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (enable & ICH6_ACPI_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "ICH6 ACPI/GPIO/TCO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (enable & ICH6_GPIO_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) "ICH6 GPIO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) const char *name, int dynsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u32 size, base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) pci_read_config_dword(dev, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* Enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (!(val & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) base = val & 0xfffc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (dynsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * This is not correct. It is 16, 32 or 64 bytes depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * register D31:F0:ADh bits 5:4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * But this gets us at least _part_ of it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) size = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) size = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) base &= ~(size-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * Just print it out for now. We should reserve it after more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * debugging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static void quirk_ich6_lpc(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Shared ACPI/GPIO decode with all ICH6+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ich6_lpc_acpi_gpio(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* ICH6-specific generic IO decode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) u32 mask, base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) pci_read_config_dword(dev, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* Enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (!(val & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) base = val & 0xfffc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) mask = (val >> 16) & 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) mask |= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * Just print it out for now. We should reserve it after more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * debugging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* ICH7-10 has the same common LPC generic IO decode registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static void quirk_ich7_lpc(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* We share the common ACPI/GPIO decode with ICH6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ich6_lpc_acpi_gpio(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* And have 4 ICH7+ generic decodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * VIA ACPI: One IO region pointed to by longword at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * 0x48 or 0x20 (256 bytes of ACPI registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static void quirk_vt82c586_acpi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (dev->revision & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) "vt82c586 ACPI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * 0x48 (256 bytes of ACPI registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * 0x70 (128 bytes of hardware monitoring register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * 0x90 (16 bytes of SMB registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static void quirk_vt82c686_acpi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) quirk_vt82c586_acpi(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) "vt82c686 HW-mon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * 0x88 (128 bytes of power management registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * 0xd0 (16 bytes of SMB registers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static void quirk_vt8235_acpi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * back-to-back: Disable fast back-to-back on the secondary bus segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static void quirk_xio2000a(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) u16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) pci_read_config_word(pdev, PCI_COMMAND, &command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (command & PCI_COMMAND_FAST_BACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) quirk_xio2000a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #ifdef CONFIG_X86_IO_APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #include <asm/io_apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * devices to the external APIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * TODO: When we have device-specific interrupt routers, this code will go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * away from quirks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static void quirk_via_ioapic(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (nr_ioapics < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) tmp = 0; /* nothing routed to external APIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) pci_info(dev, "%sbling VIA external APIC routing\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) tmp == 0 ? "Disa" : "Ena");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* Offset 0x58: External APIC IRQ output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) pci_write_config_byte(dev, 0x58, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * This leads to doubled level interrupt rates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * Set this bit to get rid of cycle wastage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * Otherwise uncritical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u8 misc_control2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define BYPASS_APIC_DEASSERT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) pci_read_config_byte(dev, 0x5B, &misc_control2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * We check all revs >= B0 (yet not in the pre production!) as the bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * is currently marked NoFix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * We have multiple reports of hangs with this chipset that went away with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * noapic specified. For the moment we assume it's the erratum. We may be wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * of course. However the advice is demonstrably good even if so.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static void quirk_amd_ioapic(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (dev->revision >= 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) pci_warn(dev, " : booting with the \"noapic\" option\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #endif /* CONFIG_X86_IO_APIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (dev->subsystem_device == 0xa118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) dev->sriov->link = dev->devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * Some settings of MMRBC can lead to data corruption so block changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (dev->subordinate && dev->revision <= 0x12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * at all. Therefore it seems like setting the pci_dev's IRQ to the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * of the ACPI SCI interrupt is only done for convenience.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * -jgarzik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static void quirk_via_acpi(struct pci_dev *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u8 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) pci_read_config_byte(d, 0x42, &irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) irq &= 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (irq && (irq != 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) d->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* VIA bridges which have VLink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static void quirk_via_bridge(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* See what bridge we have and find the device ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) case PCI_DEVICE_ID_VIA_82C686:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * The VT82C686 is special; it attaches to PCI and can have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * any device number. All its subdevices are functions of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * that single device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) via_vlink_dev_lo = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) via_vlink_dev_hi = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) case PCI_DEVICE_ID_VIA_8237:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) case PCI_DEVICE_ID_VIA_8237A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) via_vlink_dev_lo = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) case PCI_DEVICE_ID_VIA_8235:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) via_vlink_dev_lo = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) case PCI_DEVICE_ID_VIA_8231:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) case PCI_DEVICE_ID_VIA_8233_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) case PCI_DEVICE_ID_VIA_8233A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) case PCI_DEVICE_ID_VIA_8233C_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) via_vlink_dev_lo = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * quirk_via_vlink - VIA VLink IRQ number update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * If the device we are dealing with is on a PIC IRQ we need to ensure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * the IRQ line register which usually is not relevant for PCI cards, is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * actually written so that interrupts get sent to the right place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * We only do this on systems where a VIA south bridge was detected, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * only for VIA devices on the motherboard (see quirk_via_bridge above).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static void quirk_via_vlink(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) u8 irq, new_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* Check if we have VLink at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (via_vlink_dev_lo == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) new_irq = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* Don't quirk interrupts outside the legacy IRQ range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (!new_irq || new_irq > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /* Internal device ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * This is an internal VLink device on a PIC interrupt. The BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * ought to have set this but may not have, so we redo it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (new_irq != irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) irq, new_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) udelay(15); /* unknown if delay really needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * of VT82C597 for backward compatibility. We need to switch it off to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * able to recognize the real type of the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static void quirk_vt82c598_id(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) pci_write_config_byte(dev, 0xfc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * CardBus controllers have a legacy base address that enables them to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * respond as i82365 pcmcia controllers. We don't want them to do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * even if the Linux CardBus driver is not loaded, because the Linux i82365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * driver does not (and should not) handle CardBus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static void quirk_cardbus_legacy(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * Following the PCI ordering rules is optional on the AMD762. I'm not sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * what the designers were smoking but let's not inhale...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * To be fair to AMD, it follows the spec by default, it's BIOS people who
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * turn it off!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static void quirk_amd_ordering(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) u32 pcic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) pci_read_config_dword(dev, 0x4C, &pcic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if ((pcic & 6) != 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) pcic |= 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) pci_write_config_dword(dev, 0x4C, pcic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) pci_read_config_dword(dev, 0x84, &pcic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) pcic |= (1 << 23); /* Required in this mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) pci_write_config_dword(dev, 0x84, pcic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * DreamWorks-provided workaround for Dunord I-3000 problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * This card decodes and responds to addresses not apparently assigned to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * it. We force a larger allocation to ensure that nothing gets put too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * close to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static void quirk_dunord(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct resource *r = &dev->resource[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) r->flags |= IORESOURCE_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) r->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) r->end = 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * decoding (transparent), and does indicate this in the ProgIf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static void quirk_transparent_bridge(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) dev->transparent = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * found at http://www.national.com/analog for info on what these bits do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * <christer@weinigel.se>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static void quirk_mediagx_master(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) pci_read_config_byte(dev, 0x41, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (reg & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) reg &= ~2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) pci_write_config_byte(dev, 0x41, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * in the odd case it is not the results are corruption hence the presence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * of a Linux check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static void quirk_disable_pxb(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) u16 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (pdev->revision != 0x04) /* Only C0 requires this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) pci_read_config_word(pdev, 0x40, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (config & (1<<6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) config &= ~(1<<6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) pci_write_config_word(pdev, 0x40, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static void quirk_amd_ide_mode(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (tmp == 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) pci_read_config_byte(pdev, 0x40, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) pci_write_config_byte(pdev, 0x40, tmp|1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) pci_write_config_byte(pdev, 0x9, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) pci_write_config_byte(pdev, 0xa, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) pci_write_config_byte(pdev, 0x40, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) pci_info(pdev, "set SATA to AHCI mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* Serverworks CSB5 IDE does not fully support native mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static void quirk_svwks_csb5ide(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) u8 prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (prog & 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) prog &= ~5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) pdev->class &= ~5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* PCI layer will sort out resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static void quirk_ide_samemode(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) u8 prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) prog &= ~5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) pdev->class &= ~5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* Some ATA devices break if put into D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static void quirk_no_ata_d3(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* Quirk the legacy ATA devices only. The AHCI ones are ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* ALi loses some register settings that we cannot then restore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) occur when mode detecting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * This was originally an Alpha-specific thing, but it really fits here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static void quirk_eisa_bridge(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) dev->class = PCI_CLASS_BRIDGE_EISA << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * is not activated. The myth is that Asus said that they do not want the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * users to be irritated by just another PCI Device in the Win98 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * package 2.7.0 for details)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) * becomes necessary to do this tweak in two steps -- the chosen trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * is either the Host bridge (preferred) or on-board VGA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * Note that we used to unhide the SMBus that way on Toshiba laptops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * (Satellite A40 and Tecra M2) but then found that the thermal management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * was done by SMM code, which could cause unsynchronized concurrent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * accesses to the SMBus registers, with potentially bad effects. Thus you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * should be very careful when adding new entries: if SMM is accessing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * Intel SMBus, this is a very good reason to leave it hidden.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * Likewise, many recent laptops use ACPI for thermal management. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * ACPI DSDT code accesses the SMBus, then Linux should not access it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * natively, and keeping the SMBus hidden is the right thing to do. If you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * are about to add an entry in the table below, please first disassemble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * the DSDT and double-check that there is no code accessing the SMBus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static int asus_hides_smbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) case 0x8025: /* P4B-LX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) case 0x8070: /* P4B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) case 0x8088: /* P4B533 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) case 0x1626: /* L3C notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) case 0x80b1: /* P4GE-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) case 0x80b2: /* P4PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) case 0x8093: /* P4B533-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) case 0x8030: /* P4T533 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) case 0x8070: /* P4G8X Deluxe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) case 0x80c9: /* PU-DLS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) case 0x1751: /* M2N notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) case 0x1821: /* M5N notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) case 0x1897: /* A6L notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) case 0x184b: /* W1N notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) case 0x186a: /* M6Ne notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) case 0x80f2: /* P4P800-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) case 0x1882: /* M6V notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) case 0x1977: /* A6VA notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) case 0x088C: /* HP Compaq nc8000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) case 0x0890: /* HP Compaq nc6000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) case 0x12bc: /* HP D330L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) case 0x12bd: /* HP D530 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) case 0x006a: /* HP Compaq nx9500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) case 0x12bf: /* HP xw4100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) case 0xC00C: /* Samsung P35 notebook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) case 0x0058: /* Compaq Evo N620c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* Motherboard doesn't have Host bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * subvendor/subdevice IDs, therefore checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) * its on-board VGA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) case 0x00b8: /* Compaq Evo D510 CMT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) case 0x00b9: /* Compaq Evo D510 SFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) case 0x00ba: /* Compaq Evo D510 USDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* Motherboard doesn't have Host bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) * subvendor/subdevice IDs and on-board VGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) * controller is disabled if an AGP card is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) * inserted, therefore checking USB UHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * Controller #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) switch (dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* Motherboard doesn't have host bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * subvendor/subdevice IDs, therefore checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) * its on-board VGA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) asus_hides_smbus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static void asus_hides_smbus_lpc(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (likely(!asus_hides_smbus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) pci_read_config_word(dev, 0xF2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (val & 0x8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) pci_write_config_word(dev, 0xF2, val & (~0x8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) pci_read_config_word(dev, 0xF2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (val & 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) pci_info(dev, "Enabled i801 SMBus device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* It appears we just have one such device. If not, we have a warning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static void __iomem *asus_rcba_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) u32 rcba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (likely(!asus_hides_smbus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) WARN_ON(asus_rcba_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) pci_read_config_dword(dev, 0xF0, &rcba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* use bits 31:14, 16 kB aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (asus_rcba_base == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (likely(!asus_hides_smbus || !asus_rcba_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /* read the Function Disable register, dword mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) val = readl(asus_rcba_base + 0x3418);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* enable the SMBus device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (likely(!asus_hides_smbus || !asus_rcba_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) iounmap(asus_rcba_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) asus_rcba_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) asus_hides_smbus_lpc_ich6_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) asus_hides_smbus_lpc_ich6_resume_early(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) asus_hides_smbus_lpc_ich6_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* SiS 96x south bridge: BIOS typically hides SMBus device... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static void quirk_sis_96x_smbus(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) pci_read_config_byte(dev, 0x77, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if (val & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) pci_info(dev, "Enabling SiS 96x SMBus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) pci_write_config_byte(dev, 0x77, val & ~0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) * ... This is further complicated by the fact that some SiS96x south
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) * bridges pretend to be 85C503/5513 instead. In that case see if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) * spotted a compatible north bridge to make sure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) * (pci_find_device() doesn't work yet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) * We can also enable the sis96x bit in the discovery register..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) #define SIS_DETECT_REGISTER 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) static void quirk_sis_503(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) u16 devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * it has already been processed. (Depends on link order, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) * apparently not guaranteed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) dev->device = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) quirk_sis_96x_smbus(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) * and MC97 modem controller are disabled when a second PCI soundcard is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * present. This patch, tweaking the VT8237 ISA bridge, enables them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * -- bjd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static void asus_hides_ac97_lpc(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) int asus_hides_ac97 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (dev->device == PCI_DEVICE_ID_VIA_8237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) asus_hides_ac97 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (!asus_hides_ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) pci_read_config_byte(dev, 0x50, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) if (val & 0xc0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) pci_write_config_byte(dev, 0x50, val & (~0xc0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) pci_read_config_byte(dev, 0x50, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (val & 0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) * If we are using libata we can drive this chip properly but must do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) * early on to make the additional device appear during the PCI scanning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static void quirk_jmicron_ata(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) u32 conf1, conf5, class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) u8 hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* Only poke fn 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (PCI_FUNC(pdev->devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) pci_read_config_dword(pdev, 0x40, &conf1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) pci_read_config_dword(pdev, 0x80, &conf5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) conf5 &= ~(1 << 24); /* Clear bit 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) /* The controller should be in single function ahci mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) case PCI_DEVICE_ID_JMICRON_JMB365:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) case PCI_DEVICE_ID_JMICRON_JMB366:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) /* Redirect IDE second PATA port to the right spot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) conf5 |= (1 << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) case PCI_DEVICE_ID_JMICRON_JMB361:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) case PCI_DEVICE_ID_JMICRON_JMB363:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) case PCI_DEVICE_ID_JMICRON_JMB369:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) /* Set the class codes correctly and then direct IDE 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) case PCI_DEVICE_ID_JMICRON_JMB368:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) /* The controller should be in single function IDE mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) conf1 |= 0x00C00000; /* Set 22, 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) pci_write_config_dword(pdev, 0x40, conf1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) pci_write_config_dword(pdev, 0x80, conf5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /* Update pdev accordingly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) pdev->hdr_type = hdr & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) pdev->multifunction = !!(hdr & 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) pdev->class = class >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static void quirk_jmicron_async_suspend(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if (dev->multifunction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) device_disable_async_suspend(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) #ifdef CONFIG_X86_IO_APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static void quirk_alder_ioapic(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if ((pdev->class >> 8) != 0xff00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) * The first BAR is the location of the IO-APIC... we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) * not touch this (and it's already covered by the fixmap), so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) * forcibly insert it into the resource tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) insert_resource(&iomem_resource, &pdev->resource[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) * The next five BARs all seem to be rubbish, so just clean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) * them out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) for (i = 1; i < PCI_STD_NUM_BARS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) static void quirk_no_msi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) pci_info(dev, "avoiding MSI to work around a hardware defect\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) dev->no_msi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) static void quirk_pcie_mch(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) pdev->no_msi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * It's possible for the MSI to get corrupted if SHPC and ACPI are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) * together on certain PXH-based systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) static void quirk_pcie_pxh(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) dev->no_msi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) * Some Intel PCI Express chipsets have trouble with downstream device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) * power management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) static void quirk_intel_pcie_pm(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) pci_pm_d3hot_delay = 120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) dev->no_d1d2 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (dev->d3hot_delay >= delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) dev->d3hot_delay = delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) dev->d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static void quirk_radeon_pm(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) dev->subsystem_device == 0x00e2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) quirk_d3hot_delay(dev, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) * https://bugzilla.kernel.org/show_bug.cgi?id=205587
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) * The kernel attempts to transition these devices to D3cold, but that seems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) * to be ineffective on the platforms in question; the PCI device appears to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) * remain on in D3hot state. The D3hot-to-D0 transition then requires an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) * extended delay in order to succeed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) quirk_d3hot_delay(dev, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) #ifdef CONFIG_X86_IO_APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) noioapicreroute = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static const struct dmi_system_id boot_interrupt_dmi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) * Systems to exclude from boot interrupt reroute quirks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .callback = dmi_disable_ioapicreroute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .ident = "ASUSTek Computer INC. M2N-LR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) * remap the original interrupt in the Linux kernel to the boot interrupt, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) * that a PCI device's interrupt handler is installed on the boot interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) * line instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) dmi_check_system(boot_interrupt_dmi_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (noioapicquirk || noioapicreroute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) dev->vendor, dev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) * On some chipsets we can disable the generation of legacy INTx boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) * 300641-004US, section 5.7.3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) * Core IO on Xeon E5 v2, see Intel order no 329188-003.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) * Core IO on Xeon E7 v2, see Intel order no 329595-002.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) * Core IO on Xeon E5 v3, see Intel order no 330784-003.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) * Core IO on Xeon D-1500, see Intel order no 332051-001.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) * Core IO on Xeon Scalable, see Intel order no 610950.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) u16 pci_config_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) u32 pci_config_dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) if (noioapicquirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) case PCI_DEVICE_ID_INTEL_ESB_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) &pci_config_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) pci_config_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) case 0x3c28: /* Xeon E5 1600/2600/4600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) case 0x0e28: /* Xeon E5/E7 V2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) case 0x2f28: /* Xeon E5/E7 V3,V4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) case 0x6f28: /* Xeon D-1500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) case 0x2034: /* Xeon Scalable Family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) &pci_config_dword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) pci_config_dword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) dev->vendor, dev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) * Device 29 Func 5 Device IDs of IO-APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) * containing ABAR—APIC1 Alternate Base Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) quirk_disable_intel_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) quirk_disable_intel_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) * Device 5 Func 0 Device IDs of Core IO modules/hubs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) * containing Coherent Interface Protocol Interrupt Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) * Device IDs obtained from volume 2 datasheets of commented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) * families above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) quirk_disable_intel_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) quirk_disable_intel_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) quirk_disable_intel_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) quirk_disable_intel_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) quirk_disable_intel_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) quirk_disable_intel_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) quirk_disable_intel_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) quirk_disable_intel_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) quirk_disable_intel_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) quirk_disable_intel_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) /* Disable boot interrupts on HT-1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) #define BC_HT1000_FEATURE_REG 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) #define BC_HT1000_MAP_IDX 0xC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) #define BC_HT1000_MAP_DATA 0xC01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) u32 pci_config_dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) u8 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) if (noioapicquirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) BC_HT1000_PIC_REGS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) for (irq = 0x10; irq < 0x10 + 32; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) outb(irq, BC_HT1000_MAP_IDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) outb(0x00, BC_HT1000_MAP_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) dev->vendor, dev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) /* Disable boot interrupts on AMD and ATI chipsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) * (due to an erratum).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) #define AMD_813X_MISC 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) #define AMD_813X_NOIOAMODE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) #define AMD_813X_REV_B1 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) #define AMD_813X_REV_B2 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) u32 pci_config_dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (noioapicquirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) if ((dev->revision == AMD_813X_REV_B1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) (dev->revision == AMD_813X_REV_B2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) pci_config_dword &= ~AMD_813X_NOIOAMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) dev->vendor, dev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) #define AMD_8111_PCI_IRQ_ROUTING 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) u16 pci_config_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if (noioapicquirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) if (!pci_config_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) dev->vendor, dev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) dev->vendor, dev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) #endif /* CONFIG_X86_IO_APIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) * Re-allocate the region if needed...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) static void quirk_tc86c001_ide(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) struct resource *r = &dev->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) if (r->start & 0x8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) r->flags |= IORESOURCE_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) r->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) r->end = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) quirk_tc86c001_ide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) * being read correctly if bit 7 of the base address is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) * Re-allocate the regions to a 256-byte boundary if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) static void quirk_plx_pci9050(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) unsigned int bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) /* Fixed in revision 2 (PCI 9052). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (dev->revision >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) for (bar = 0; bar <= 1; bar++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) if (pci_resource_len(dev, bar) == 0x80 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) (pci_resource_start(dev, bar) & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) struct resource *r = &dev->resource[bar];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) r->flags |= IORESOURCE_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) r->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) r->end = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) quirk_plx_pci9050);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) * driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static void quirk_netmos(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) unsigned int num_serial = dev->subsystem_device & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) * These Netmos parts are multiport serial devices with optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) * parallel ports. Even when parallel ports are present, they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) * are identified as class SERIAL, which means the serial driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) * will claim them. To prevent this, mark them as class OTHER.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) * These combo devices should be claimed by parport_serial.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) * The subdevice ID is of the form 0x00PS, where <P> is the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) * of parallel ports and <S> is the number of serial ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) case PCI_DEVICE_ID_NETMOS_9835:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) /* Well, this rule doesn't hold for the following 9835 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) dev->subsystem_device == 0x0299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) case PCI_DEVICE_ID_NETMOS_9735:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) case PCI_DEVICE_ID_NETMOS_9745:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) case PCI_DEVICE_ID_NETMOS_9845:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) case PCI_DEVICE_ID_NETMOS_9855:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) if (num_parallel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) dev->device, num_parallel, num_serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) (dev->class & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static void quirk_e100_interrupt(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) u16 command, pmcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) u8 __iomem *csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) u8 cmd_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) /* PCI IDs taken from drivers/net/e100.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) case 0x1029:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) case 0x1030 ... 0x1034:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) case 0x1038 ... 0x103E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) case 0x1050 ... 0x1057:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) case 0x1059:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) case 0x1064 ... 0x106B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) case 0x1091 ... 0x1095:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) case 0x1209:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) case 0x1229:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) case 0x2449:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) case 0x2459:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) case 0x245D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) case 0x27DC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) * Some firmware hands off the e100 with interrupts enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) * which can cause a flood of interrupts if packets are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) * received before the driver attaches to the device. So
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) * disable all e100 interrupts here. The driver will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) * re-enable them when it's ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) pci_read_config_word(dev, PCI_COMMAND, &command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) * Check that the device is in the D0 power state. If it's not,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) * there is no point to look any further.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) if (dev->pm_cap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) /* Convert from PCI bus to resource space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) csr = ioremap(pci_resource_start(dev, 0), 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) if (!csr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) pci_warn(dev, "Can't map e100 registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) cmd_hi = readb(csr + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) if (cmd_hi == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) writeb(1, csr + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) iounmap(csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) * The 82575 and 82598 may experience data corruption issues when transitioning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) * out of L0S. To prevent this we need to disable L0S on the PCIe link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) static void quirk_disable_aspm_l0s(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) pci_info(dev, "Disabling L0s\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) pci_info(dev, "Disabling ASPM L0s/L1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) * disable both L0s and L1 for now to be safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) * Link bit cleared after starting the link retrain process to allow this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) * process to finish.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) dev->clear_retrain_link = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) pci_info(dev, "Enable PCIe Retrain Link quirk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) static void fixup_rev1_53c810(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) u32 class = dev->class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) * rev 1 ncr53c810 chips don't set the class at all which means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) * they don't get their resources remapped. Fix that here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) if (class)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) dev->class = PCI_CLASS_STORAGE_SCSI << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) class, dev->class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) /* Enable 1k I/O space granularity on the Intel P64H2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) static void quirk_p64h2_1k_io(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) u16 en1k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) pci_read_config_word(dev, 0x40, &en1k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) if (en1k & 0x200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) pci_info(dev, "Enable I/O Space to 1KB granularity\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) dev->io_window_1k = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) * Under some circumstances, AER is not linked with extended capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) * Force it to be linked by setting the corresponding control bit in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) * config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) uint8_t b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) if (!(b & 0x20)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) pci_write_config_byte(dev, 0xf41, b | 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) pci_info(dev, "Linking AER extended capability\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) quirk_nvidia_ck804_pcie_aer_ext_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) quirk_nvidia_ck804_pcie_aer_ext_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) * Disable PCI Bus Parking and PCI Master read caching on CX700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) * which causes unspecified timing errors with a VT6212L on the PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) * bus leading to USB2.0 packet loss.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) * This quirk is only enabled if a second (on the external PCI bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) * VT6212L is found -- the CX700 core itself also contains a USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) * host controller with the same PCI ID as the VT6212L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) /* Count VT6212L instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) uint8_t b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) * p should contain the first (internal) VT6212L -- see if we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) * an external one by searching again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) pci_dev_put(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) if (pci_read_config_byte(dev, 0x76, &b) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) if (b & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) /* Turn off PCI Bus Parking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) pci_write_config_byte(dev, 0x76, b ^ 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) pci_info(dev, "Disabling VIA CX700 PCI parking\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) if (pci_read_config_byte(dev, 0x72, &b) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) if (b != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) /* Turn off PCI Master read caching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) pci_write_config_byte(dev, 0x72, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) /* Set PCI Master Bus time-out to "1x16 PCLK" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) pci_write_config_byte(dev, 0x75, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) /* Disable "Read FIFO Timer" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) pci_write_config_byte(dev, 0x77, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) pci_info(dev, "Disabling VIA CX700 PCI caching\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) u32 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) pci_read_config_dword(dev, 0xf4, &rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) /* Only CAP the MRRS if the device is a 5719 A0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) if (rev == 0x05719000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) int readrq = pcie_get_readrq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) if (readrq > 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) pcie_set_readrq(dev, 2048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) PCI_DEVICE_ID_TIGON3_5719,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) quirk_brcm_5719_limit_mrrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) * hide device 6 which configures the overflow device access containing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) * DRBs - this is where we expose device 6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) static void quirk_unhide_mch_dev6(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) pci_info(dev, "Enabling MCH 'Overflow' Device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) pci_write_config_byte(dev, 0xF4, reg | 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) quirk_unhide_mch_dev6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) quirk_unhide_mch_dev6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) * Some chipsets do not support MSI. We cannot easily rely on setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) * other buses controlled by the chipset even if Linux is not aware of it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) * Instead of setting the flag on all buses in the machine, simply disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) * MSI globally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) static void quirk_disable_all_msi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) pci_no_msi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) pci_warn(dev, "MSI quirk detected; MSI disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) /* Disable MSI on chipsets that are known to not support it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) static void quirk_disable_msi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) if (dev->subordinate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) * The APC bridge device in AMD 780 family northbridges has some random
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) * OEM subsystem ID in its vendor ID register (erratum 18), so instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) * we use the possible vendor/device IDs of the host bridge for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) * declared quirk, and search for the APC bridge by slot number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) struct pci_dev *apc_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) if (apc_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) if (apc_bridge->device == 0x9602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) quirk_disable_msi(apc_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) pci_dev_put(apc_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) * Go through the list of HyperTransport capabilities and return 1 if a HT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) * MSI capability is found and enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) static int msi_ht_cap_enabled(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) int pos, ttl = PCI_FIND_CAP_TTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) while (pos && ttl--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) &flags) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) pci_info(dev, "Found %s HT MSI Mapping\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) flags & HT_MSI_FLAGS_ENABLE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) return (flags & HT_MSI_FLAGS_ENABLE) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) pos = pci_find_next_ht_capability(dev, pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) HT_CAPTYPE_MSI_MAPPING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) static void quirk_msi_ht_cap(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) quirk_msi_ht_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) * if the MSI capability is set in any of these mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) if (!dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) * Check HT MSI cap on this chipset and the root one. A single one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) * having MSI is enough to be sure that MSI is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) pdev = pci_get_slot(dev->bus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) quirk_nvidia_ck804_msi_ht_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) /* Force enable MSI mapping capability on HT bridges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static void ht_enable_msi_mapping(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) int pos, ttl = PCI_FIND_CAP_TTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) while (pos && ttl--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) &flags) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) pci_info(dev, "Enabling HT MSI Mapping\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) flags | HT_MSI_FLAGS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) pos = pci_find_next_ht_capability(dev, pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) HT_CAPTYPE_MSI_MAPPING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) ht_enable_msi_mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) ht_enable_msi_mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) * The P5N32-SLI motherboards from Asus have a problem with MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) * for the MCP55 NIC. It is not yet determined whether the MSI problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) * also affects other devices. As for now, turn off MSI for this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) static void nvenet_msi_disable(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) if (board_name &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) (strstr(board_name, "P5N32-SLI PREMIUM") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) strstr(board_name, "P5N32-E SLI"))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) dev->no_msi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) PCI_DEVICE_ID_NVIDIA_NVENET_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) nvenet_msi_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) * generate MSI interrupts for PME and AER events instead only INTx interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) * for other events, since PCIe specificiation doesn't support using a mix of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) * service drivers registering their respective ISRs for MSIs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) dev->no_msi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) PCI_CLASS_BRIDGE_PCI, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) pci_quirk_nvidia_tegra_disable_rp_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) PCI_CLASS_BRIDGE_PCI, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) pci_quirk_nvidia_tegra_disable_rp_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) PCI_CLASS_BRIDGE_PCI, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) pci_quirk_nvidia_tegra_disable_rp_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) PCI_CLASS_BRIDGE_PCI, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) pci_quirk_nvidia_tegra_disable_rp_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) PCI_CLASS_BRIDGE_PCI, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) pci_quirk_nvidia_tegra_disable_rp_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) PCI_CLASS_BRIDGE_PCI, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) pci_quirk_nvidia_tegra_disable_rp_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) PCI_CLASS_BRIDGE_PCI, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) pci_quirk_nvidia_tegra_disable_rp_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) PCI_CLASS_BRIDGE_PCI, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) pci_quirk_nvidia_tegra_disable_rp_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) PCI_CLASS_BRIDGE_PCI, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) pci_quirk_nvidia_tegra_disable_rp_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) PCI_CLASS_BRIDGE_PCI, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) pci_quirk_nvidia_tegra_disable_rp_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) PCI_CLASS_BRIDGE_PCI, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) pci_quirk_nvidia_tegra_disable_rp_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) PCI_CLASS_BRIDGE_PCI, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) pci_quirk_nvidia_tegra_disable_rp_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) PCI_CLASS_BRIDGE_PCI, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) pci_quirk_nvidia_tegra_disable_rp_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) * config register. This register controls the routing of legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) * interrupts from devices that route through the MCP55. If this register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) * is misprogrammed, interrupts are only sent to the BSP, unlike
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) * conventional systems where the IRQ is broadcast to all online CPUs. Not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) * having this register set properly prevents kdump from booting up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) * properly, so let's make sure that we have it set correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) * Note that this is an undocumented register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) if (!pci_find_capability(dev, PCI_CAP_ID_HT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) pci_read_config_dword(dev, 0x74, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) if (cfg & ((1 << 2) | (1 << 15))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) pr_info("Rewriting IRQ routing register on MCP55\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) cfg &= ~((1 << 2) | (1 << 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) pci_write_config_dword(dev, 0x74, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) nvbridge_check_legacy_irq_routing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) nvbridge_check_legacy_irq_routing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) static int ht_check_msi_mapping(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) int pos, ttl = PCI_FIND_CAP_TTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) int found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) /* Check if there is HT MSI cap or enabled on this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) while (pos && ttl--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) if (found < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) &flags) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) if (flags & HT_MSI_FLAGS_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) if (found < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) found = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) pos = pci_find_next_ht_capability(dev, pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) HT_CAPTYPE_MSI_MAPPING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) return found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) static int host_bridge_with_leaf(struct pci_dev *host_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) int i, dev_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) int found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) dev_no = host_bridge->devfn >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) for (i = dev_no + 1; i < 0x20; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) /* found next host bridge? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) if (pos != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) pci_dev_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) if (ht_check_msi_mapping(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) pci_dev_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) pci_dev_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) return found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) static int is_end_of_ht_chain(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) int pos, ctrl_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) int end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) u16 flags, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) ctrl_off = ((flags >> 10) & 1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) pci_read_config_word(dev, pos + ctrl_off, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) if (ctrl & (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) end = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) return end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) struct pci_dev *host_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) int i, dev_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) int found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) dev_no = dev->devfn >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) for (i = dev_no; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) if (!host_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) if (pos != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) pci_dev_put(host_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) if (!found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) /* don't enable end_device/host_bridge with leaf directly here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) host_bridge_with_leaf(host_bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) /* root did that ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) if (msi_ht_cap_enabled(host_bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) ht_enable_msi_mapping(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) pci_dev_put(host_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) static void ht_disable_msi_mapping(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) int pos, ttl = PCI_FIND_CAP_TTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) while (pos && ttl--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) &flags) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) pci_info(dev, "Disabling HT MSI Mapping\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) flags & ~HT_MSI_FLAGS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) pos = pci_find_next_ht_capability(dev, pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) HT_CAPTYPE_MSI_MAPPING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) struct pci_dev *host_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) int found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) if (!pci_msi_enabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) /* check if there is HT MSI cap or enabled on this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) found = ht_check_msi_mapping(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) /* no HT MSI CAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) if (found == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) * HT MSI mapping should be disabled on devices that are below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) * a non-Hypertransport host bridge. Locate the host bridge...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) PCI_DEVFN(0, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) if (host_bridge == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) if (pos != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) /* Host bridge is to HT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) if (found == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) /* it is not enabled, try to enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) if (all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) ht_enable_msi_mapping(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) nv_ht_enable_msi_mapping(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) /* HT MSI is not enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) if (found == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) /* Host bridge is not to HT, disable HT MSI mapping on this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) ht_disable_msi_mapping(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) pci_dev_put(host_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) return __nv_msi_ht_cap_quirk(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) return __nv_msi_ht_cap_quirk(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) struct pci_dev *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) * SB700 MSI issue will be fixed at HW level from revision A21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) * we need check PCI REVISION ID of SMBus controller to get SB700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) * revision.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) if ((p->revision < 0x3B) && (p->revision >= 0x30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) pci_dev_put(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) if (dev->revision < 0x18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) PCI_DEVICE_ID_TIGON3_5780,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) PCI_DEVICE_ID_TIGON3_5780S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) PCI_DEVICE_ID_TIGON3_5714,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) PCI_DEVICE_ID_TIGON3_5714S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) PCI_DEVICE_ID_TIGON3_5715,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) PCI_DEVICE_ID_TIGON3_5715S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) quirk_msi_intx_disable_ati_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) quirk_msi_intx_disable_ati_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) quirk_msi_intx_disable_ati_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) quirk_msi_intx_disable_ati_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) quirk_msi_intx_disable_ati_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) quirk_msi_intx_disable_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) quirk_msi_intx_disable_qca_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) quirk_msi_intx_disable_qca_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) quirk_msi_intx_disable_qca_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) quirk_msi_intx_disable_qca_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) quirk_msi_intx_disable_qca_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) * should be disabled on platforms where the device (mistakenly) advertises it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) * Notice that this quirk also disables MSI (which may work, but hasn't been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) * tested), since currently there is no standard way to disable only MSI-X.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) * The 0031 device id is reused for other non Root Port device types,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) static void quirk_al_msi_disable(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) dev->no_msi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) pci_warn(dev, "Disabling MSI/MSI-X\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) #endif /* CONFIG_PCI_MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) * Allow manual resource allocation for PCI hotplug bridges via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) * allocate resources when hotplug device is inserted and PCI bus is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) * rescanned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) static void quirk_hotplug_bridge(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) dev->is_hotplug_bridge = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) * This is a quirk for the Ricoh MMC controller found as a part of some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) * multifunction chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) * This is very similar and based on the ricoh_mmc driver written by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) * Philip Langdale. Thank you for these magic sequences.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) * These chips implement the four main memory card controllers (SD, MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) * MS, xD) and one or both of CardBus or FireWire.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) * It happens that they implement SD and MMC support as separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) * controllers (and PCI functions). The Linux SDHCI driver supports MMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) * cards but the chip detects MMC cards in hardware and directs them to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) * MMC controller - so the SDHCI driver never sees them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) * To get around this, we must disable the useless MMC controller. At that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) * point, the SDHCI controller will start seeing them. It seems to be the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) * case that the relevant PCI registers to deactivate the MMC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) * live on PCI function 0, which might be the CardBus controller or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) * FireWire controller, depending on the particular chip in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) * This has to be done early, because as soon as we disable the MMC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) * other PCI functions shift up one level, e.g. function #2 becomes function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) * #1, and this will confuse the PCI core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) #ifdef CONFIG_MMC_RICOH_MMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) u8 write_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) u8 write_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) u8 disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) * Disable via CardBus interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) * This must be done via function #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) if (PCI_FUNC(dev->devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) pci_read_config_byte(dev, 0xB7, &disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) if (disable & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) pci_read_config_byte(dev, 0x8E, &write_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) pci_write_config_byte(dev, 0x8E, 0xAA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) pci_read_config_byte(dev, 0x8D, &write_target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) pci_write_config_byte(dev, 0x8D, 0xB7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) pci_write_config_byte(dev, 0xB7, disable | 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) pci_write_config_byte(dev, 0x8E, write_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) pci_write_config_byte(dev, 0x8D, write_target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) u8 write_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) u8 disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) * Disable via FireWire interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) * This must be done via function #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) if (PCI_FUNC(dev->devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) * certain types of SD/MMC cards. Lowering the SD base clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) * frequency from 200Mhz to 50Mhz fixes this issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) * 0x150 - SD2.0 mode enable for changing base clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) * frequency to 50Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) * 0xe1 - Base clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) * 0x32 - 50Mhz new clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) * 0xf9 - Key register for 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) * 0xfc - key register for 0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) pci_write_config_byte(dev, 0xf9, 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) pci_write_config_byte(dev, 0x150, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) pci_write_config_byte(dev, 0xf9, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) pci_write_config_byte(dev, 0xfc, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) pci_write_config_byte(dev, 0xe1, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) pci_write_config_byte(dev, 0xfc, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) pci_read_config_byte(dev, 0xCB, &disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) if (disable & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) pci_read_config_byte(dev, 0xCA, &write_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) pci_write_config_byte(dev, 0xCA, 0x57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) pci_write_config_byte(dev, 0xCB, disable | 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) pci_write_config_byte(dev, 0xCA, write_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) #endif /*CONFIG_MMC_RICOH_MMC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) #ifdef CONFIG_DMAR_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) #define VTUNCERRMSK_REG 0x1ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) #define VTD_MSK_SPEC_ERRORS (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) * This is a quirk for masking VT-d spec-defined errors to platform error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) * on the RAS config settings of the platform) when a VT-d fault happens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) * The resulting SMI caused the system to hang.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) * VT-d spec-related errors are already handled by the VT-d OS code, so no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) * need to report the same error through other channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) static void vtd_mask_spec_errors(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) u32 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) static void fixup_ti816x_class(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) u32 class = dev->class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) /* TI 816x devices do not have class code set when in PCIe boot mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) class, dev->class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) * Some PCIe devices do not work reliably with the claimed maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) * payload size supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) static void fixup_mpss_256(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) dev->pcie_mpss = 1; /* 256 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) * Intel 5000 and 5100 Memory controllers have an erratum with read completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) * Since there is no way of knowing what the PCIe MPS on each fabric will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) * until all of the devices are discovered and buses walked, read completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) * it is possible to hotplug a device with MPS of 256B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) static void quirk_intel_mc_errata(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) u16 rcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) pcie_bus_config == PCIE_BUS_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) * Intel erratum specifies bits to change but does not say what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) * they are. Keeping them magical until such time as the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) * and values can be explained.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) err = pci_read_config_word(dev, 0x48, &rcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) pci_err(dev, "Error attempting to read the read completion coalescing register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) if (!(rcc & (1 << 10)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) rcc &= ~(1 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) err = pci_write_config_word(dev, 0x48, rcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) pci_err(dev, "Error attempting to write the read completion coalescing register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) /* Intel 5000 series memory controllers and ports 2-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) /* Intel 5100 series memory controllers and ports 2-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) * To work around this, query the size it should be configured to by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) * device and modify the resource end to correspond to this new size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) static void quirk_intel_ntb(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) rc = pci_read_config_byte(dev, 0x00D0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) rc = pci_read_config_byte(dev, 0x00D1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) * Some BIOS implementations leave the Intel GPU interrupts enabled, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) * though no one is handling them (e.g., if the i915 driver is never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) * loaded). Additionally the interrupt destination is not set up properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) * and the interrupt ends up -somewhere-.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) * These spurious interrupts are "sticky" and the kernel disables the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) * (shared) interrupt line after 100,000+ generated interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) * Fix it by disabling the still enabled interrupts. This resolves crashes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) * often seen on monitor unplug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) #define I915_DEIER_REG 0x4400c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) static void disable_igfx_irq(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) void __iomem *regs = pci_iomap(dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) if (regs == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) /* Check if any interrupt line is still enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) if (readl(regs + I915_DEIER_REG) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) writel(0, regs + I915_DEIER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) pci_iounmap(dev, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) * PCI devices which are on Intel chips can skip the 10ms delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) * before entering D3 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) static void quirk_remove_d3hot_delay(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) dev->d3hot_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) /* C600 Series devices do not need 10ms d3hot_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) /* Intel Cherrytrail devices do not need 10ms d3hot_delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) * Some devices may pass our check in pci_intx_mask_supported() if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) * support this feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) static void quirk_broken_intx_masking(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) dev->broken_intx_masking = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) * DisINTx can be set but the interrupt status bit is non-functional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) static u16 mellanox_broken_intx_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) PCI_DEVICE_ID_MELLANOX_HERMON_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) PCI_DEVICE_ID_MELLANOX_CONNECTX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) PCI_DEVICE_ID_MELLANOX_CONNECTX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) #define CONNECTX_4_CURR_MAX_MINOR 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) #define CONNECTX_4_INTX_SUPPORT_MINOR 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) * If so, don't mark it as broken.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) * FW minor > 99 means older FW version format and no INTx masking support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) * FW minor < 14 means new FW version format and no INTx masking support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) __be32 __iomem *fw_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) u16 fw_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) u16 fw_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) u16 fw_subminor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) u32 fw_maj_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) u32 fw_sub_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) if (pdev->device == mellanox_broken_intx_devs[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) pdev->broken_intx_masking = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) * Getting here means Connect-IB cards and up. Connect-IB has no INTx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) * support so shouldn't be checked further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) if (pci_enable_device_mem(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) pci_warn(pdev, "Can't enable device memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) if (!fw_ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) /* Reading from resource space should be 32b aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) fw_maj_min = ioread32be(fw_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) fw_sub_min = ioread32be(fw_ver + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) fw_major = fw_maj_min & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) fw_minor = fw_maj_min >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) fw_subminor = fw_sub_min & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) fw_major, fw_minor, fw_subminor, pdev->device ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) pdev->broken_intx_masking = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) iounmap(fw_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) mellanox_check_broken_intx_masking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) static void quirk_no_bus_reset(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) * prevented for those affected devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) if ((dev->device & 0xffc0) == 0x2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) quirk_no_bus_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) quirk_nvidia_no_bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) * The device will throw a Link Down error on AER-capable systems and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) * regardless of AER, config space of the device is never accessible again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) * and typically causes the system to hang or reset when access is attempted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) * Root port on some Cavium CN8xxx chips do not successfully complete a bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) * reset when used with certain child devices. After the reset, config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) * accesses to the child may fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) * automatically disables LTSSM when Secondary Bus Reset is received and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) * the device stops working. Prevent bus reset for these devices. With
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) * this change, the device can be assigned to VMs with VFIO, but it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) * leak state between VMs. Reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) * https://e2e.ti.com/support/processors/f/791/t/954382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) static void quirk_no_pm_reset(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) * We can't do a bus reset on root bus devices, but an ineffective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) * PM reset may be better than nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) if (!pci_is_root_bus(dev->bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) * to have no effect on the device: it retains the framebuffer contents and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) * monitor sync. Advertising this support makes other layers, like VFIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) * assume pci_reset_function() is viable for this device. Mark it as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) * unavailable to skip it when testing reset methods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) * Thunderbolt controllers with broken MSI hotplug signaling:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) if (pdev->is_hotplug_bridge &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) pdev->revision <= 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) pdev->no_msi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) quirk_thunderbolt_hotplug_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) quirk_thunderbolt_hotplug_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) quirk_thunderbolt_hotplug_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) quirk_thunderbolt_hotplug_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) quirk_thunderbolt_hotplug_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) * Apple: Shutdown Cactus Ridge Thunderbolt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) * shutdown before suspend. Otherwise the native host interface (NHI) will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) * be present after resume if a device was plugged in before suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) * The Thunderbolt controller consists of a PCIe switch with downstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) * bridges leading to the NHI and to the tunnel PCI bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) * This quirk cuts power to the whole chip. Therefore we have to apply it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) * during suspend_noirq of the upstream bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) * Power is automagically restored before resume. No action is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) acpi_handle bridge, SXIO, SXFP, SXLV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) if (!x86_apple_machine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) * We don't know how to turn it back on again, but firmware does,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) * so we can only use SXIO/SXFP/SXLF if we're suspending via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) * firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) if (!pm_suspend_via_firmware())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) bridge = ACPI_HANDLE(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) * SXIO and SXLV are present only on machines requiring this quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) * Thunderbolt bridges in external devices might have the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) * device ID as those on the host, but they will not have the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) * associated ACPI methods. This implicitly checks that we are at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) * the right bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) /* magic sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) acpi_execute_simple_method(SXIO, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) acpi_execute_simple_method(SXFP, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) msleep(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) acpi_execute_simple_method(SXLV, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) acpi_execute_simple_method(SXIO, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) acpi_execute_simple_method(SXLV, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) quirk_apple_poweroff_thunderbolt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) * Following are device-specific reset methods which can be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) * reset a single function if other methods (e.g. FLR, PM D0->D3) are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) * not available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) * The 82599 supports FLR on VFs, but FLR support is reported only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) * Thus we must call pcie_flr() directly without first checking if it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) * supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) if (!probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) pcie_flr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) #define SOUTH_CHICKEN2 0xc2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) #define PCH_PP_STATUS 0xc7200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) #define PCH_PP_CONTROL 0xc7204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) #define MSG_CTL 0x45010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) #define NSDE_PWR_STATE 0xd0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) static int reset_ivb_igd(struct pci_dev *dev, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) if (probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) mmio_base = pci_iomap(dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) if (!mmio_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) iowrite32(0x00000002, mmio_base + MSG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) * Clobbering SOUTH_CHICKEN2 register is fine only if the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) * driver loaded sets the right bits. However, this's a reset and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) * the bits have been set by i915 previously, so we clobber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) * SOUTH_CHICKEN2 register directly here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) iowrite32(val, mmio_base + PCH_PP_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) val = ioread32(mmio_base + PCH_PP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) if ((val & 0xb0000000) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) goto reset_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) } while (time_before(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) pci_warn(dev, "timeout during reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) reset_complete:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) pci_iounmap(dev, mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) /* Device-specific reset method for Chelsio T4-based adapters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) u16 old_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) u16 msix_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) * that we have no device-specific reset method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) if ((dev->device & 0xf000) != 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) * If this is the "probe" phase, return 0 indicating that we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) * reset this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) if (probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) * T4 can wedge if there are DMAs in flight within the chip and Bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) * Master has been disabled. We need to have it on till the Function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) * Level Reset completes. (BUS_MASTER is disabled in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) * pci_reset_function()).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) pci_read_config_word(dev, PCI_COMMAND, &old_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) pci_write_config_word(dev, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) old_command | PCI_COMMAND_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) * Perform the actual device function reset, saving and restoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) * configuration information around the reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) pci_save_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) * are disabled when an MSI-X interrupt message needs to be delivered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) * So we briefly re-enable MSI-X interrupts for the duration of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) * FLR. The pci_restore_state() below will restore the original
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) * MSI-X state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) msix_flags |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) PCI_MSIX_FLAGS_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) PCI_MSIX_FLAGS_MASKALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) pcie_flr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) * Restore the configuration information (BAR values, etc.) including
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) * the original PCI Configuration Space Command word, and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) * success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) pci_restore_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) pci_write_config_word(dev, PCI_COMMAND, old_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) * FLR where config space reads from the device return -1. We seem to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) * able to avoid this condition if we disable the NVMe controller prior to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) * FLR. This quirk is generic for any NVMe class device requiring similar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) * assistance to quiesce the device prior to FLR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) * NVMe specification: https://nvmexpress.org/resources/specifications/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) * Revision 1.0e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) * Chapter 2: Required and optional PCI config registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) * Chapter 3: NVMe control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) * Chapter 7.3: Reset behavior
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) void __iomem *bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) if (probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) if (!bar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) pci_read_config_word(dev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) cfg = readl(bar + NVME_REG_CC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) /* Disable controller if enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) if (cfg & NVME_CC_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) u32 cap = readl(bar + NVME_REG_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) * Per nvme_disable_ctrl() skip shutdown notification as it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) * could complete commands to the admin queue. We only intend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) * to quiesce the device before reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) writel(cfg, bar + NVME_REG_CC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) * Some controllers require an additional delay here, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) * supported by this quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) /* Cap register provides max timeout in 500ms increments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) u32 status = readl(bar + NVME_REG_CSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) /* Ready status becomes zero on disable complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) if (!(status & NVME_CSTS_RDY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) pci_iounmap(dev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) pcie_flr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) * Intel DC P3700 NVMe controller will timeout waiting for ready status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) * to change after NVMe enable if the driver starts interacting with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) * device too soon after FLR. A 250ms delay after FLR has heuristically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) * proven to produce reliably working results for device assignment cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) if (!pcie_has_flr(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) if (probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) pcie_flr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) msleep(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) #define PCI_DEVICE_ID_HINIC_VF 0x375E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) #define HINIC_VF_FLR_TYPE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) #define HINIC_VF_FLR_CAP_BIT (1UL << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) #define HINIC_VF_OP 0xE80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) #define HINIC_VF_FLR_PROC_BIT (1UL << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) static int reset_hinic_vf_dev(struct pci_dev *pdev, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) void __iomem *bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) if (probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) bar = pci_iomap(pdev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) if (!bar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) /* Get and check firmware capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) val = ioread32be(bar + HINIC_VF_FLR_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) if (!(val & HINIC_VF_FLR_CAP_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) pci_iounmap(pdev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) val = ioread32be(bar + HINIC_VF_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) val = val | HINIC_VF_FLR_PROC_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) iowrite32be(val, bar + HINIC_VF_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) pcie_flr(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) * The device must recapture its Bus and Device Numbers after FLR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) * in order generate Completions. Issue a config write to let the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) * device capture this information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) pci_write_config_word(pdev, PCI_VENDOR_ID, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) val = ioread32be(bar + HINIC_VF_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) if (!(val & HINIC_VF_FLR_PROC_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) goto reset_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) } while (time_before(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) val = ioread32be(bar + HINIC_VF_OP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) if (!(val & HINIC_VF_FLR_PROC_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) goto reset_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) reset_complete:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) pci_iounmap(pdev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) reset_intel_82599_sfp_virtfn },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) reset_ivb_igd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) reset_ivb_igd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) reset_chelsio_generic_dev },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) reset_hinic_vf_dev },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) * These device-specific reset methods are here rather than in a driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) * because when a host assigns a device to a guest VM, the host may need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) * to reset the device but probably doesn't have a driver for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) int pci_dev_specific_reset(struct pci_dev *dev, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) const struct pci_dev_reset_methods *i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) for (i = pci_dev_reset_methods; i->reset; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) if ((i->vendor == dev->vendor ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) i->vendor == (u16)PCI_ANY_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) (i->device == dev->device ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) i->device == (u16)PCI_ANY_ID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) return i->reset(dev, probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) static void quirk_dma_func0_alias(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) if (PCI_FUNC(dev->devfn) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) * https://bugzilla.redhat.com/show_bug.cgi?id=605888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) static void quirk_dma_func1_alias(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) if (PCI_FUNC(dev->devfn) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) * SKUs function 1 is present and is a legacy IDE controller, in other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) * SKUs this function is not present, making this a ghost requester.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) * https://bugzilla.kernel.org/show_bug.cgi?id=42679
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) PCI_DEVICE_ID_JMICRON_JMB388_ESD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) quirk_dma_func1_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) * Some devices DMA with the wrong devfn, not just the wrong function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) * the alias is "fixed" and independent of the device devfn.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) * single device on the secondary bus. In reality, the single exposed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) * device at 0e.0 is the Address Translation Unit (ATU) of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) * that provides a bridge to the internal bus of the I/O processor. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) * controller supports private devices, which can be hidden from PCI config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) * space. In the case of the Adaptec 3405, a private device at 01.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) * appears to be the DMA engine, which therefore needs to become a DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) * alias for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) static const struct pci_device_id fixed_dma_alias_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) .driver_data = PCI_DEVFN(1, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) .driver_data = PCI_DEVFN(1, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) static void quirk_fixed_dma_alias(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) const struct pci_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) id = pci_match_id(fixed_dma_alias_tbl, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) if (id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) pci_add_dma_alias(dev, id->driver_data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) * using the wrong DMA alias for the device. Some of these devices can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) * used as either forward or reverse bridges, so we need to test whether the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) * device is operating in the correct mode. We could probably apply this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) if (!pci_is_root_bus(pdev->bus) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) quirk_use_pcie_bridge_dma_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) /* ITE 8893 has the same problem as the 8892 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) * be added as aliases to the DMA device in order to allow buffer access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) * when IOMMU is enabled. Following devfns have to match RIT-LUT table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) * programmed in the EEPROM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) * when IOMMU is enabled. These aliases allow computational unit access to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) * host memory. These aliases mark the whole VCA device as one IOMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) * group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) * All possible slot numbers (0x20) are used, since we are unable to tell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) * what slot is used on other side. This quirk is intended for both host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) * and computational unit sides. The VCA devices have up to five functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) * (four for DMA channels and one additional).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) static void quirk_pex_vca_alias(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) const unsigned int num_pci_slots = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) unsigned int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) for (slot = 0; slot < num_pci_slots; slot++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) * associated not at the root bus, but at a bridge below. This quirk avoids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) * generating invalid DMA aliases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) quirk_bridge_cavm_thrx2_pcie_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) quirk_bridge_cavm_thrx2_pcie_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) * class code. Fix it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) static void quirk_tw686x_class(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) u32 class = pdev->class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) /* Use "Multimedia controller" class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) class, pdev->class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) quirk_tw686x_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) quirk_tw686x_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) quirk_tw686x_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) quirk_tw686x_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) * Some devices have problems with Transaction Layer Packets with the Relaxed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) * Ordering Attribute set. Such devices should mark themselves and other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) * device drivers should check before sending TLPs with RO set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) static void quirk_relaxedordering_disable(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) * Complex have a Flow Control Credit issue which can cause performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) * where Upstream Transaction Layer Packets with the Relaxed Ordering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) * November 10, 2010). As a result, on this platform we can't use Relaxed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) * Ordering for Upstream TLPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) quirk_relaxedordering_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) * values for the Attribute as were supplied in the header of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) * corresponding Request, except as explicitly allowed when IDO is used."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) * If a non-compliant device generates a completion with a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) * attribute than the request, the receiver may accept it (which itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) * seems non-compliant based on sec 2.3.2), or it may handle it as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) * Malformed TLP or an Unexpected Completion, which will probably lead to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) * device access timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) * If the non-compliant device generates completions with zero attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) * (instead of copying the attributes from the request), we can work around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) * upstream devices so they always generate requests with zero attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) * This affects other devices under the same Root Port, but since these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) * attributes are performance hints, there should be no functional problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) * Note that Configuration Space accesses are never supposed to have TLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) * Attributes, so we're safe waiting till after any Configuration Space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) * accesses to do the Root Port fixup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) struct pci_dev *root_port = pcie_find_root_port(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) if (!root_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) PCI_EXP_DEVCTL_RELAX_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) * Completion it generates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) * This mask/compare operation selects for Physical Function 4 on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) * T5. We only need to fix up the Root Port once for any of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) * 0x54xx so we use that one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) if ((pdev->device & 0xff00) == 0x5400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) quirk_disable_root_port_attributes(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) quirk_chelsio_T5_disable_root_port_attributes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) * by a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) * @acs_ctrl_req: Bitmask of desired ACS controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) * the hardware design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) * in @acs_ctrl_ena, i.e., the device provides all the access controls the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) * caller desires. Return 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) * AMD has indicated that the devices below do not support peer-to-peer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) * in any system where they are found in the southbridge with an AMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) * IOMMU in the system. Multifunction devices that do not support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) * peer-to-peer between functions can claim to support a subset of ACS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) * Such devices effectively enable request redirect (RR) and completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) * redirect (CR) since all transactions are redirected to the upstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) * root complex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) * 1002:4385 SBx00 SMBus Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) * 1002:4383 SBx00 Azalia (Intel HDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) * 1002:4384 SBx00 PCI to PCI Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) * 1022:780f [AMD] FCH PCI Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) * 1022:7809 [AMD] FCH USB OHCI Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) struct acpi_table_header *header = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) /* Targeting multifunction devices on the SB (appears on root bus) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) if (!dev->multifunction || !pci_is_root_bus(dev->bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) /* The IVRS table describes the AMD IOMMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) status = acpi_get_table("IVRS", 0, &header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) if (ACPI_FAILURE(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) acpi_put_table(header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) /* Filter out flags not applicable to multifunction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) * Effectively selects all downstream ports for whole ThunderX1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) * (which represents 8 SoCs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) case 0xa000 ... 0xa7ff: /* ThunderX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) case 0xaf84: /* ThunderX2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) case 0xb884: /* ThunderX3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) if (!pci_quirk_cavium_acs_match(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) * Cavium Root Ports don't advertise an ACS capability. However,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) * the RTL internally implements similar protection as if ACS had
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) * Source Validation, Request Redirection, Completion Redirection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) * and Upstream Forwarding features enabled. Assert that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) * hardware implements and enables equivalent ACS functionality for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) * these flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) return pci_acs_ctrl_enabled(acs_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) * X-Gene Root Ports matching this quirk do not allow peer-to-peer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) * transactions with others, allowing masking out these bits as if they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) * were unimplemented in the ACS capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) return pci_acs_ctrl_enabled(acs_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) * But the implementation could block peer-to-peer transactions between them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) * and provide ACS-like functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) if (!pci_is_pcie(dev) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) case 0x0710 ... 0x071e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) case 0x0721:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) case 0x0723 ... 0x0732:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) return pci_acs_ctrl_enabled(acs_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) * Many Intel PCH Root Ports do provide ACS-like features to disable peer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) * transactions and validate bus numbers in requests, but do not provide an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) * actual PCIe ACS capability. This is the list of device IDs known to fall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) * into that category as provided by Intel in Red Hat bugzilla 1037684.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) static const u16 pci_quirk_intel_pch_acs_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) /* Ibexpeak PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) /* Cougarpoint PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) /* Pantherpoint PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) /* Lynxpoint-H PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) /* Lynxpoint-LP PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) /* Wildcat PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) /* Patsburg (X79) PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) /* Wellsburg (X99) PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) /* Lynx Point (9 series) PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) /* Filter out a few obvious non-matches first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) if (!pci_quirk_intel_pch_acs_match(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) return pci_acs_ctrl_enabled(acs_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) return pci_acs_ctrl_enabled(acs_flags, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) * These QCOM Root Ports do provide ACS-like features to disable peer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) * transactions and validate bus numbers in requests, but do not provide an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) * actual PCIe ACS capability. Hardware supports source validation but it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) * will report the issue as Completer Abort instead of ACS Violation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) * Hardware doesn't support peer-to-peer and each Root Port is a Root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) * Complex with unique segment numbers. It is not possible for one Root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) * Port to pass traffic to another Root Port. All PCIe transactions are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) * terminated inside the Root Port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) return pci_acs_ctrl_enabled(acs_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) * Each of these NXP Root Ports is in a Root Complex with a unique segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) * number and does provide isolation features to disable peer transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) * and validate bus numbers in requests, but does not provide an ACS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) * capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) return pci_acs_ctrl_enabled(acs_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) * Amazon's Annapurna Labs root ports don't include an ACS capability,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) * but do include ACS-like functionality. The hardware doesn't support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) * peer-to-peer transactions via the root port and each has a unique
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) * segment number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) * Additionally, the root ports cannot send traffic to each other.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) return acs_flags ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) * control registers whereas the PCIe spec packs them into words (Rev 3.0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) * 7.16 ACS Extended Capability). The bit definitions are correct, but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) * control register is at offset 8 instead of 6 and we should probably use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) * dword accesses to them. This applies to the following PCI Device IDs, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) * found in volume 1 of the datasheet[2]:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) * N.B. This doesn't fix what lspci shows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) * The 100 series chipset specification update includes this as errata #23[3].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) * The 200 series chipset (Union Point) has the same bug according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) * specification update (Intel 200 Series Chipset Family Platform Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) * chipset include:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) * 0xa290-0xa29f PCI Express Root port #{0-16}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) * Mobile chipsets are also affected, 7th & 8th Generation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) * Specification update confirms ACS errata 22, status no fix: (7th Generation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) * Processor Family I/O for U Quad Core Platforms Specification Update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) * August 2017, Revision 002, Document#: 334660-002)[6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) * 0x9d10-0x9d1b PCI Express Root port #{1-12}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) u32 cap, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) if (!pci_quirk_intel_spt_pch_acs_match(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) pos = dev->acs_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) /* see pci_acs_flags_enabled() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) acs_flags &= (cap | PCI_ACS_EC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) return pci_acs_ctrl_enabled(acs_flags, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) * SV, TB, and UF are not relevant to multifunction endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) * Multifunction devices are only required to implement RR, CR, and DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) * in their ACS capability if they support peer-to-peer transactions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) * Devices matching this quirk have been verified by the vendor to not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) * perform peer-to-peer with other functions, allowing us to mask out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) * these bits as if they were unimplemented in the ACS capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) return pci_acs_ctrl_enabled(acs_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) * Intel RCiEP's are required to allow p2p only on translated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) * "Root-Complex Peer to Peer Considerations".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) return pci_acs_ctrl_enabled(acs_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) * iProc PAXB Root Ports don't advertise an ACS capability, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) * they do not allow peer-to-peer transactions between Root Ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) * Allow each Root Port to be in a separate IOMMU group by masking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) * SV/RR/CR/UF bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) return pci_acs_ctrl_enabled(acs_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) static const struct pci_dev_acs_enabled {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) u16 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) } pci_dev_acs_enabled[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) /* 82580 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) /* 82576 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) /* 82575 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) /* I350 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) /* 82571 (Quads omitted due to non-ACS switch) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) /* I219 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) /* QCOM QDF2xxx root ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) /* Intel PCH root ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) /* Cavium ThunderX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) /* Cavium multi-function devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) /* APM X-Gene */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) /* Ampere Computing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) /* Broadcom multi-function device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) /* Amazon Annapurna Labs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) /* Zhaoxin multi-function devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) /* NXP root ports, xx=16, 12, or 08 cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) /* LX2xx0A : without security features + CAN-FD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) /* LX2xx0C : security features + CAN-FD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) /* LX2xx0E : security features + CAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) /* LX2xx0N : without security features + CAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) /* LX2xx2A : without security features + CAN-FD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) /* LX2xx2C : security features + CAN-FD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) /* LX2xx2E : security features + CAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) /* LX2xx2N : without security features + CAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) /* Zhaoxin Root/Downstream Ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) * pci_dev_specific_acs_enabled - check whether device provides ACS controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) * @acs_flags: Bitmask of desired ACS controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) * -ENOTTY: No quirk applies to this device; we can't tell whether the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) * device provides the desired controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) * 0: Device does not provide all the desired controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) * >0: Device provides all the controls in @acs_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) const struct pci_dev_acs_enabled *i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) * Allow devices that do not expose standard PCIe ACS capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) * or control to indicate their support here. Multi-function express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) * devices which do not allow internal peer-to-peer between functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) * but do not implement PCIe ACS may wish to return true here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) if ((i->vendor == dev->vendor ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) i->vendor == (u16)PCI_ANY_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) (i->device == dev->device ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) i->device == (u16)PCI_ANY_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) ret = i->acs_enabled(dev, acs_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) /* Config space offset of Root Complex Base Address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) #define INTEL_LPC_RCBA_REG 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) /* 31:14 RCBA address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) #define INTEL_LPC_RCBA_MASK 0xffffc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) /* RCBA Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) #define INTEL_LPC_RCBA_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) /* Backbone Scratch Pad Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) #define INTEL_BSPR_REG 0x1104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) /* Backbone Peer Non-Posted Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) #define INTEL_BSPR_REG_BPNPD (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) /* Backbone Peer Posted Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) #define INTEL_BSPR_REG_BPPD (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) /* Upstream Peer Decode Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) #define INTEL_UPDCR_REG 0x1014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) /* 5:0 Peer Decode Enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) #define INTEL_UPDCR_REG_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) u32 rcba, bspr, updcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) void __iomem *rcba_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) * Read the RCBA register from the LPC (D31:F0). PCH root ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) * are D28:F* and therefore get probed before LPC, thus we can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) * use pci_get_slot()/pci_read_config_dword() here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) INTEL_LPC_RCBA_REG, &rcba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) if (!(rcba & INTEL_LPC_RCBA_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) PAGE_ALIGN(INTEL_UPDCR_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) if (!rcba_mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) * The BSPR can disallow peer cycles, but it's set by soft strap and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) * therefore read-only. If both posted and non-posted peer cycles are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) * disallowed, we're ok. If either are allowed, then we need to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) * the UPDCR to disable peer decodes for each port. This provides the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) bspr = readl(rcba_mem + INTEL_BSPR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) updcr = readl(rcba_mem + INTEL_UPDCR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) if (updcr & INTEL_UPDCR_REG_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) pci_info(dev, "Disabling UPDCR peer decodes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) updcr &= ~INTEL_UPDCR_REG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) writel(updcr, rcba_mem + INTEL_UPDCR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) iounmap(rcba_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) /* Miscellaneous Port Configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) #define INTEL_MPC_REG 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) /* MPC: Invalid Receive Bus Number Check Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) #define INTEL_MPC_REG_IRBNCE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) u32 mpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) * When enabled, the IRBNCE bit of the MPC register enables the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) * ensures that requester IDs fall within the bus number range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) * of the bridge. Enable if not already.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) pci_info(dev, "Enabling MPC IRBNCE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) mpc |= INTEL_MPC_REG_IRBNCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) pci_write_config_word(dev, INTEL_MPC_REG, mpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) * Currently this quirk does the equivalent of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) * if dev->external_facing || dev->untrusted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) if (!pci_quirk_intel_pch_acs_match(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) if (pci_quirk_enable_intel_lpc_acs(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) pci_quirk_enable_intel_rp_mpc_acs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) u32 cap, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) if (!pci_quirk_intel_spt_pch_acs_match(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) pos = dev->acs_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) ctrl |= (cap & PCI_ACS_SV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) ctrl |= (cap & PCI_ACS_RR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) ctrl |= (cap & PCI_ACS_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) ctrl |= (cap & PCI_ACS_UF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) if (dev->external_facing || dev->untrusted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) ctrl |= (cap & PCI_ACS_TB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) u32 cap, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) if (!pci_quirk_intel_spt_pch_acs_match(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) pos = dev->acs_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) static const struct pci_dev_acs_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) u16 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) int (*enable_acs)(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) int (*disable_acs_redir)(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) } pci_dev_acs_ops[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) .enable_acs = pci_quirk_enable_intel_pch_acs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) int pci_dev_specific_enable_acs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) const struct pci_dev_acs_ops *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) p = &pci_dev_acs_ops[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) if ((p->vendor == dev->vendor ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) p->vendor == (u16)PCI_ANY_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) (p->device == dev->device ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) p->device == (u16)PCI_ANY_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) p->enable_acs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) ret = p->enable_acs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) const struct pci_dev_acs_ops *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) p = &pci_dev_acs_ops[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) if ((p->vendor == dev->vendor ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) p->vendor == (u16)PCI_ANY_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) (p->device == dev->device ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) p->device == (u16)PCI_ANY_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) p->disable_acs_redir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) ret = p->disable_acs_redir(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) * Next Capability pointer in the MSI Capability Structure should point to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) * the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) int pos, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) u8 next_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) u16 reg16, *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) struct pci_cap_saved_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) /* Bail if the hardware bug is fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) /* Bail if MSI Capability Structure is not found for some reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) * Bail if Next Capability pointer in the MSI Capability Structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) * is not the expected incorrect 0x00.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) pci_read_config_byte(pdev, pos + 1, &next_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) if (next_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) * PCIe Capability Structure is expected to be at 0x50 and should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) * terminate the list (Next Capability pointer is 0x00). Verify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) * Capability Id and Next Capability pointer is as expected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) * to correctly set kernel data structures which have already been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) * set incorrectly due to the hardware bug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) pos = 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) pci_read_config_word(pdev, pos, ®16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) #ifndef PCI_EXP_SAVE_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) #define PCI_EXP_SAVE_REGS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) int size = PCI_EXP_SAVE_REGS * sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) pdev->pcie_cap = pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) pdev->pcie_flags_reg = reg16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) pdev->cfg_size = PCI_CFG_SPACE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) /* Save PCIe cap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) state->cap.cap_nr = PCI_CAP_ID_EXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) state->cap.cap_extended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) state->cap.size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) cap = (u16 *)&state->cap.data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) hlist_add_head(&state->next, &pdev->saved_cap_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) * FLR may cause the following to devices to hang:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) * AMD Starship/Matisse HD Audio Controller 0x1487
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) * AMD Starship USB 3.0 Host Controller 0x148c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) * AMD Matisse USB 3.0 Host Controller 0x149c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) * Intel 82579LM Gigabit Ethernet Controller 0x1502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) * Intel 82579V Gigabit Ethernet Controller 0x1503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) static void quirk_no_flr(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) static void quirk_no_ext_tags(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) bridge->no_ext_tags = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) #ifdef CONFIG_PCI_ATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) * Some devices require additional driver setup to enable ATS. Don't use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) * ATS for those devices as ATS will be enabled before the driver has had a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) * chance to load and configure the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) if ((pdev->device == 0x7312 && pdev->revision != 0x00) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) (pdev->device == 0x7340 && pdev->revision != 0xc5) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) (pdev->device == 0x7341 && pdev->revision != 0x00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) pci_info(pdev, "disabling ATS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) pdev->ats_cap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) /* AMD Stoney platform GPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) /* AMD Iceland dGPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) /* AMD Navi10 dGPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) /* AMD Navi14 dGPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) #endif /* CONFIG_PCI_ATS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) /* Freescale PCIe doesn't support MSI in RC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) static void quirk_fsl_no_msi(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) pdev->no_msi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) * Although not allowed by the spec, some multi-function devices have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) * dependencies of one function (consumer) on another (supplier). For the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) * consumer to work in D0, the supplier must also be in D0. Create a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) * device link from the consumer to the supplier to enforce this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) * dependency. Runtime PM is allowed by default on the consumer to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) * it from permanently keeping the supplier awake.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) unsigned int supplier, unsigned int class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) unsigned int class_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) struct pci_dev *supplier_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) if (PCI_FUNC(pdev->devfn) != consumer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) pdev->bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) pci_dev_put(supplier_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) if (device_link_add(&pdev->dev, &supplier_pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) pci_info(pdev, "D0 power state depends on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) pci_name(supplier_pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) pci_err(pdev, "Cannot enforce power dependency on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) pci_name(supplier_pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) pm_runtime_allow(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) pci_dev_put(supplier_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) * Create device link for GPUs with integrated HDA controller for streaming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) * audio to attached displays.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) static void quirk_gpu_hda(struct pci_dev *hda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) * Create device link for GPUs with integrated USB xHCI Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) * controller to VGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) static void quirk_gpu_usb(struct pci_dev *usb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) * Create device link for GPUs with integrated Type-C UCSI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) * to VGA. Currently there is no class code defined for UCSI device over PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) * so using UNKNOWN class for now and it will be updated when UCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) * over PCI gets a class code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) PCI_CLASS_SERIAL_UNKNOWN, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) quirk_gpu_usb_typec_ucsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) PCI_CLASS_SERIAL_UNKNOWN, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) quirk_gpu_usb_typec_ucsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) * disabled. https://devtalk.nvidia.com/default/topic/1024022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) static void quirk_nvidia_hda(struct pci_dev *gpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) u8 hdr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) /* There was no integrated HDA controller before MCP89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) /* Bit 25 at offset 0x488 enables the HDA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) pci_read_config_dword(gpu, 0x488, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) if (val & BIT(25))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) pci_info(gpu, "Enabling HDA controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) pci_write_config_dword(gpu, 0x488, val | BIT(25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) /* The GPU becomes a multi-function device when the HDA is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) gpu->multifunction = !!(hdr_type & 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) * Some IDT switches incorrectly flag an ACS Source Validation error on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) * completions for config read requests even though PCIe r4.0, sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) * 6.12.1.1, says that completions are never affected by ACS Source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) * Item #36 - Downstream port applies ACS Source Validation to Completions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) * completions are never affected by ACS Source Validation. However,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) * completions received by a downstream port of the PCIe switch from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) * device that has not yet captured a PCIe bus number are incorrectly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) * dropped by ACS Source Validation by the switch downstream port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) * The workaround suggested by IDT is to issue a config write to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) * downstream device before issuing the first config read. This allows the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) * downstream device to capture its bus and device numbers (see PCIe r4.0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) * sec 2.2.9), thus avoiding the ACS error on the completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) * However, we don't know when the device is ready to accept the config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) * write, so we do config reads until we receive a non-Config Request Retry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) * Status, then do the config write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) * To avoid hitting the erratum when doing the config reads, we disable ACS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) * SV around this process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) u16 ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) bool found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) struct pci_dev *bridge = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) pos = bridge->acs_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) /* Disable ACS SV before initial config reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) if (pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) if (ctrl & PCI_ACS_SV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) ctrl & ~PCI_ACS_SV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) if (found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) /* Re-enable ACS_SV if it was previously enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) if (ctrl & PCI_ACS_SV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) return found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) * NT endpoints via the internal switch fabric. These IDs replace the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) * originating requestor ID TLPs which access host memory on peer NTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) * ports. Therefore, all proxy IDs must be aliased to the NTB device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) * to permit access when the IOMMU is turned on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) struct ntb_info_regs __iomem *mmio_ntb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) struct ntb_ctrl_regs __iomem *mmio_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) u64 partition_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) u8 partition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) int pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) if (pci_enable_device(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) pci_err(pdev, "Cannot enable Switchtec device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) mmio = pci_iomap(pdev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) if (mmio == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) pci_err(pdev, "Cannot iomap Switchtec device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) partition = ioread8(&mmio_ntb->partition_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) partition_map = ioread32(&mmio_ntb->ep_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) partition_map &= ~(1ULL << partition);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) u32 table_sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) int te;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) if (!(partition_map & (1ULL << pp)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) pci_dbg(pdev, "Processing partition %d\n", pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) mmio_peer_ctrl = &mmio_ctrl[pp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) if (!table_sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) pci_warn(pdev, "Partition %d table_sz 0\n", pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) if (table_sz > 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) pci_warn(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) "Invalid Switchtec partition %d table_sz %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) pp, table_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) for (te = 0; te < table_sz; te++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) u32 rid_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) u8 devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) devfn = (rid_entry >> 1) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) pci_dbg(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) "Aliasing Partition %d Proxy ID %02x.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) pci_add_dma_alias(pdev, devfn, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) pci_iounmap(pdev, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) #define SWITCHTEC_QUIRK(vid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) * These IDs are used to forward responses to the originator on the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) * side of the NTB. Alias all possible IDs to the NTB to permit access when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) * the IOMMU is turned on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) /* PLX NTB may use all 256 devfns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) pci_add_dma_alias(pdev, 0, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) * not always reset the secondary Nvidia GPU between reboots if the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) * is configured to use Hybrid Graphics mode. This results in the GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) * being left in whatever state it was in during the *previous* boot, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) * causes spurious interrupts from the GPU, which in turn causes us to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) * this also completely breaks nouveau.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) * clean state and fixes all these issues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) * When the machine is configured in Dedicated display mode, the issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) * mode, so we can detect that and avoid resetting it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) void __iomem *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) pdev->subsystem_device != 0x222e ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) !pdev->reset_fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) if (pci_enable_device_mem(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) * Based on nvkm_device_ctor() in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) map = pci_iomap(pdev, 0, 0x23000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) if (!map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) pci_err(pdev, "Can't map MMIO space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) * Make sure the GPU looks like it's been POSTed before resetting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) * it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) if (ioread32(map + 0x2240c) & 0x2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) ret = pci_reset_bus(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) pci_err(pdev, "Failed to reset GPU: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) iounmap(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) PCI_CLASS_DISPLAY_VGA, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) quirk_reset_lenovo_thinkpad_p50_nvgpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) * Device [1b21:2142]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) static void pci_fixup_no_d0_pme(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) pci_info(dev, "PME# does not work under D0, disabling it\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) * These devices advertise PME# support in all power states but don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) * reliably assert it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752) * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) * says "The MSI Function is not implemented on this device" in chapters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) * 7.3.27, 7.3.29-7.3.31.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) static void pci_fixup_no_msi_no_pme(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) pci_info(dev, "MSI is not implemented on this device, disabling it\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) dev->no_msi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) pci_info(dev, "PME# is unreliable, disabling it\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) dev->pme_support = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) static void apex_pci_fixup_class(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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