^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCI Express Precision Time Measurement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2016, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static void pci_ptm_info(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) char clock_desc[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) switch (dev->ptm_granularity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) snprintf(clock_desc, sizeof(clock_desc), "unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) case 255:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) snprintf(clock_desc, sizeof(clock_desc), ">254ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) snprintf(clock_desc, sizeof(clock_desc), "%uns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) dev->ptm_granularity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pci_info(dev, "PTM enabled%s, %s granularity\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) dev->ptm_root ? " (root)" : "", clock_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void pci_ptm_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 cap, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 local_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct pci_dev *ups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (!pci_is_pcie(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Enable PTM only on interior devices (root ports, switch ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * etc.) on the assumption that it causes no link traffic until an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * endpoint enables it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Switch Downstream Ports are not permitted to have a PTM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * capability; their PTM behavior is controlled by the Upstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Port (PCIe r5.0, sec 7.9.16).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ups = pci_upstream_bridge(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ups && ups->ptm_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dev->ptm_granularity = ups->ptm_granularity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev->ptm_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) local_clock = (cap & PCI_PTM_GRANULARITY_MASK) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * There's no point in enabling PTM unless it's enabled in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * upstream device or this device can be a PTM Root itself. Per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * the spec recommendation (PCIe r3.1, sec 7.32.3), select the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * furthest upstream Time Source as the PTM Root.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ups && ups->ptm_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ctrl = PCI_PTM_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (ups->ptm_granularity == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dev->ptm_granularity = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) else if (ups->ptm_granularity > local_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dev->ptm_granularity = ups->ptm_granularity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (cap & PCI_PTM_CAP_ROOT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev->ptm_root = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev->ptm_granularity = local_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ctrl |= dev->ptm_granularity << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev->ptm_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pci_ptm_info(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 cap, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct pci_dev *ups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (!pci_is_pcie(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!(cap & PCI_PTM_CAP_REQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * For a PCIe Endpoint, PTM is only useful if the endpoint can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * issue PTM requests to upstream devices that have PTM enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * For Root Complex Integrated Endpoints, there is no upstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * device, so there must be some implementation-specific way to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * associate the endpoint with a time source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ups = pci_upstream_bridge(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (!ups || !ups->ptm_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev->ptm_granularity = ups->ptm_granularity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dev->ptm_granularity = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ctrl = PCI_PTM_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ctrl |= dev->ptm_granularity << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dev->ptm_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pci_ptm_info(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (granularity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *granularity = dev->ptm_granularity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) EXPORT_SYMBOL(pci_enable_ptm);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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