^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Purpose: PCI Express Port Bus Driver's Internal Data Structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _PORTDRV_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _PORTDRV_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Service Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PCIE_PORT_SERVICE_PME_SHIFT 0 /* Power Management Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCIE_PORT_SERVICE_PME (1 << PCIE_PORT_SERVICE_PME_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCIE_PORT_SERVICE_AER_SHIFT 1 /* Advanced Error Reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCIE_PORT_SERVICE_AER (1 << PCIE_PORT_SERVICE_AER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCIE_PORT_SERVICE_HP_SHIFT 2 /* Native Hotplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCIE_PORT_SERVICE_HP (1 << PCIE_PORT_SERVICE_HP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCIE_PORT_SERVICE_DPC_SHIFT 3 /* Downstream Port Containment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCIE_PORT_SERVICE_BWNOTIF_SHIFT 4 /* Bandwidth notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCIE_PORT_SERVICE_BWNOTIF (1 << PCIE_PORT_SERVICE_BWNOTIF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCIE_PORT_DEVICE_MAXSERVICES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) extern bool pcie_ports_dpc_native;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifdef CONFIG_PCIEAER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int pcie_aer_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int pcie_aer_is_native(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline int pcie_aer_init(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifdef CONFIG_HOTPLUG_PCI_PCIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int pcie_hp_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline int pcie_hp_init(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #ifdef CONFIG_PCIE_PME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int pcie_pme_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static inline int pcie_pme_init(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #ifdef CONFIG_PCIE_DPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int pcie_dpc_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static inline int pcie_dpc_init(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Port Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCIE_ANY_PORT (~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct pcie_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int irq; /* Service IRQ/MSI/MSI-X Vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct pci_dev *port; /* Root/Upstream/Downstream Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 service; /* Port service this device represents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void *priv_data; /* Service Private Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct device device; /* Generic Device Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define to_pcie_device(d) container_of(d, struct pcie_device, device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static inline void set_service_data(struct pcie_device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) dev->priv_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline void *get_service_data(struct pcie_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return dev->priv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct pcie_port_service_driver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int (*probe)(struct pcie_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void (*remove)(struct pcie_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int (*suspend)(struct pcie_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int (*resume_noirq)(struct pcie_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int (*resume)(struct pcie_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int (*runtime_suspend)(struct pcie_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int (*runtime_resume)(struct pcie_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Device driver may resume normal operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void (*error_resume)(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int port_type; /* Type of the port this driver can handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 service; /* Port service this device represents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct device_driver driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define to_service_driver(d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) container_of(d, struct pcie_port_service_driver, driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int pcie_port_service_register(struct pcie_port_service_driver *new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void pcie_port_service_unregister(struct pcie_port_service_driver *new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * be one of the first 32 MSI-X entries. Per PCI r3.0, sec 6.8.3.1, MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * supports a maximum of 32 vectors per function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCIE_PORT_MAX_MSI_ENTRIES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define get_descriptor_id(type, service) (((type - 4) << 8) | service)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) extern struct bus_type pcie_port_bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int pcie_port_device_register(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int pcie_port_device_suspend(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int pcie_port_device_resume_noirq(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int pcie_port_device_resume(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int pcie_port_device_runtime_suspend(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int pcie_port_device_runtime_resume(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void pcie_port_device_remove(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int __must_check pcie_port_bus_register(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void pcie_port_bus_unregister(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #ifdef CONFIG_PCIE_PME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) extern bool pcie_pme_msi_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline void pcie_pme_disable_msi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pcie_pme_msi_disabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline bool pcie_pme_no_msi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return pcie_pme_msi_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #else /* !CONFIG_PCIE_PME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline void pcie_pme_disable_msi(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline bool pcie_pme_no_msi(void) { return false; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif /* !CONFIG_PCIE_PME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct device *pcie_port_find_device(struct pci_dev *dev, u32 service);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif /* _PORTDRV_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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