Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PCI Express Downstream Port Containment services driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Keith Busch <keith.busch@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2016 Intel Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define dev_fmt(fmt) "DPC: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/aer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "portdrv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static const char * const rp_pio_error_string[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	"Configuration Request received UR Completion",	 /* Bit Position 0  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	"Configuration Request received CA Completion",	 /* Bit Position 1  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	"Configuration Request Completion Timeout",	 /* Bit Position 2  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	"I/O Request received UR Completion",		 /* Bit Position 8  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	"I/O Request received CA Completion",		 /* Bit Position 9  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	"I/O Request Completion Timeout",		 /* Bit Position 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	"Memory Request received UR Completion",	 /* Bit Position 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	"Memory Request received CA Completion",	 /* Bit Position 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	"Memory Request Completion Timeout",		 /* Bit Position 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) void pci_save_dpc_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct pci_cap_saved_state *save_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u16 *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	if (!pci_is_pcie(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	if (!save_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	cap = (u16 *)&save_state->cap.data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	pci_read_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) void pci_restore_dpc_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct pci_cap_saved_state *save_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u16 *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (!pci_is_pcie(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (!save_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	cap = (u16 *)&save_state->cap.data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	pci_write_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, *cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static DECLARE_WAIT_QUEUE_HEAD(dpc_completed_waitqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #ifdef CONFIG_HOTPLUG_PCI_PCIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static bool dpc_completed(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if ((status != 0xffff) && (status & PCI_EXP_DPC_STATUS_TRIGGER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (test_bit(PCI_DPC_RECOVERING, &pdev->priv_flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  * pci_dpc_recovered - whether DPC triggered and has recovered successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * @pdev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * Return true if DPC was triggered for @pdev and has recovered successfully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * Wait for recovery if it hasn't completed yet.  Called from the PCIe hotplug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * driver to recognize and ignore Link Down/Up events caused by DPC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) bool pci_dpc_recovered(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct pci_host_bridge *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (!pdev->dpc_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * Synchronization between hotplug and DPC is not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 * if DPC is owned by firmware and EDR is not enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	host = pci_find_host_bridge(pdev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (!host->native_dpc && !IS_ENABLED(CONFIG_PCIE_EDR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 * Need a timeout in case DPC never completes due to failure of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 * dpc_wait_rp_inactive().  The spec doesn't mandate a time limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 * but reports indicate that DPC completes within 4 seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	wait_event_timeout(dpc_completed_waitqueue, dpc_completed(pdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			   msecs_to_jiffies(4000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return test_and_clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #endif /* CONFIG_HOTPLUG_PCI_PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int dpc_wait_rp_inactive(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned long timeout = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u16 cap = pdev->dpc_cap, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	while (status & PCI_EXP_DPC_RP_BUSY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 					!time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (status & PCI_EXP_DPC_RP_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		pci_warn(pdev, "root port still busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	pci_ers_result_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	u16 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	set_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * DPC disables the Link automatically in hardware, so it has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 * already been reset by the time we get here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	cap = pdev->dpc_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 * Wait until the Link is inactive, then clear DPC Trigger Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * to allow the Port to leave DPC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (!pcie_wait_for_link(pdev, false))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		ret = PCI_ERS_RESULT_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			      PCI_EXP_DPC_STATUS_TRIGGER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (!pcie_wait_for_link(pdev, true)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		pci_info(pdev, "Data Link Layer Link Active not set in 1000 msec\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		ret = PCI_ERS_RESULT_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		set_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		ret = PCI_ERS_RESULT_RECOVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	clear_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	wake_up_all(&dpc_completed_waitqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void dpc_process_rp_pio_error(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	u16 cap = pdev->dpc_cap, dpc_status, first_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		status, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		sev, syserr, exc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/* Get First Error Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	first_error = (dpc_status & 0x1f00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		if ((status & ~mask) & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				first_error == i ? " (First)" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (pdev->dpc_rp_log_size < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		goto clear_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			      &dw0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			      &dw1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			      &dw2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			      &dw3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		dw0, dw1, dw2, dw3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (pdev->dpc_rp_log_size < 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		goto clear_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		pci_read_config_dword(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  clear_status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int dpc_get_aer_uncorrect_severity(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 					  struct aer_err_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	int pos = dev->aer_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	u32 status, mask, sev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	status &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	status &= sev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		info->severity = AER_FATAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		info->severity = AER_NONFATAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void dpc_process_error(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	u16 cap = pdev->dpc_cap, status, source, reason, ext_reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct aer_err_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	pci_info(pdev, "containment event, status:%#06x source:%#06x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		 status, source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	pci_warn(pdev, "%s detected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		 (reason == 0) ? "unmasked uncorrectable error" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		 (reason == 1) ? "ERR_NONFATAL" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		 (reason == 2) ? "ERR_FATAL" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		 (ext_reason == 0) ? "RP PIO error" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		 (ext_reason == 1) ? "software trigger" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 				     "reserved error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/* show RP PIO error detail information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (pdev->dpc_rp_extensions && reason == 3 && ext_reason == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		dpc_process_rp_pio_error(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	else if (reason == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		 dpc_get_aer_uncorrect_severity(pdev, &info) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		 aer_get_device_error_info(pdev, &info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		aer_print_error(pdev, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		pci_aer_clear_nonfatal_status(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		pci_aer_clear_fatal_status(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static irqreturn_t dpc_handler(int irq, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct pci_dev *pdev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	dpc_process_error(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* We configure DPC so it only triggers on ERR_FATAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static irqreturn_t dpc_irq(int irq, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct pci_dev *pdev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	u16 cap = pdev->dpc_cap, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT) || status == (u16)(~0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			      PCI_EXP_DPC_STATUS_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (status & PCI_EXP_DPC_STATUS_TRIGGER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) void pci_dpc_init(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	u16 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (!pdev->dpc_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (!(cap & PCI_EXP_DPC_CAP_RP_EXT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	pdev->dpc_rp_extensions = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		pci_err(pdev, "RP PIO log size %u is invalid\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			pdev->dpc_rp_log_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		pdev->dpc_rp_log_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int dpc_probe(struct pcie_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct pci_dev *pdev = dev->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	struct device *device = &dev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	u16 ctl, cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 					   dpc_handler, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 					   "pcie-dpc", pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			 status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	pci_info(pdev, "enabled with IRQ %d\n", dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void dpc_remove(struct pcie_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	struct pci_dev *pdev = dev->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	u16 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct pcie_port_service_driver dpcdriver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	.name		= "dpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.port_type	= PCIE_ANY_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.service	= PCIE_PORT_SERVICE_DPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	.probe		= dpc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	.remove		= dpc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int __init pcie_dpc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	return pcie_port_service_register(&dpcdriver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }