^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe AER software error injection support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Debugging PCIe AER code is quite difficult because it is hard to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * trigger various real hardware errors. Software based error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * injection can fake almost all kinds of errors with the help of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * user space helper tool aer-inject, which can be gotten from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * https://www.kernel.org/pub/linux/utils/pci/aer-inject/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright 2009 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Huang Ying <ying.huang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define dev_fmt(fmt) "aer_inject: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/miscdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "portdrv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Override the existing corrected and uncorrected error masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static bool aer_mask_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) module_param(aer_mask_override, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct aer_error_inj {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 uncor_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 cor_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 header_log0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 header_log1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 header_log2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 header_log3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct aer_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int pos_cap_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 uncor_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 cor_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 header_log0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 header_log1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 header_log2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 header_log3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 root_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 source_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct pci_bus_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct pci_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static LIST_HEAD(einjected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static LIST_HEAD(pci_bus_ops_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Protect einjected and pci_bus_ops_list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static DEFINE_SPINLOCK(inject_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void aer_error_init(struct aer_error *err, u32 domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int pos_cap_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) INIT_LIST_HEAD(&err->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) err->domain = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) err->bus = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) err->devfn = devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) err->pos_cap_err = pos_cap_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* inject_lock must be held before calling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct aer_error *__find_aer_error(u32 domain, unsigned int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct aer_error *err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) list_for_each_entry(err, &einjected, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (domain == err->domain &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) bus == err->bus &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) devfn == err->devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* inject_lock must be held before calling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct aer_error *__find_aer_error_by_dev(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int domain = pci_domain_nr(dev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (domain < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return __find_aer_error(domain, dev->bus->number, dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* inject_lock must be held before calling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct pci_ops *__find_pci_bus_ops(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct pci_bus_ops *bus_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) list_for_each_entry(bus_ops, &pci_bus_ops_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (bus_ops->bus == bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return bus_ops->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct pci_bus_ops *pci_bus_ops_pop(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct pci_bus_ops *bus_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) spin_lock_irqsave(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) bus_ops = list_first_entry_or_null(&pci_bus_ops_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct pci_bus_ops, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (bus_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) list_del(&bus_ops->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) spin_unlock_irqrestore(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return bus_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static u32 *find_pci_config_dword(struct aer_error *err, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int *prw1cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int rw1cs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 *target = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (err->pos_cap_err == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) switch (where - err->pos_cap_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case PCI_ERR_UNCOR_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) target = &err->uncor_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) rw1cs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case PCI_ERR_COR_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) target = &err->cor_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) rw1cs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case PCI_ERR_HEADER_LOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) target = &err->header_log0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case PCI_ERR_HEADER_LOG+4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) target = &err->header_log1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case PCI_ERR_HEADER_LOG+8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) target = &err->header_log2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case PCI_ERR_HEADER_LOG+12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) target = &err->header_log3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case PCI_ERR_ROOT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) target = &err->root_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) rw1cs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case PCI_ERR_ROOT_ERR_SRC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) target = &err->source_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (prw1cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *prw1cs = rw1cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int aer_inj_read(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct pci_ops *ops, *my_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ops = __find_pci_bus_ops(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) my_ops = bus->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bus->ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rv = ops->read(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bus->ops = my_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int aer_inj_write(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct pci_ops *ops, *my_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ops = __find_pci_bus_ops(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) my_ops = bus->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bus->ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) rv = ops->write(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) bus->ops = my_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int aer_inj_read_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 *sim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct aer_error *err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) spin_lock_irqsave(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (size != sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) domain = pci_domain_nr(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (domain < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) err = __find_aer_error(domain, bus->number, devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) sim = find_pci_config_dword(err, where, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (sim) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *val = *sim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) spin_unlock_irqrestore(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) rv = aer_inj_read(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) spin_unlock_irqrestore(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int aer_inj_write_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 *sim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct aer_error *err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int rw1cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) spin_lock_irqsave(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (size != sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) domain = pci_domain_nr(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (domain < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) err = __find_aer_error(domain, bus->number, devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sim = find_pci_config_dword(err, where, &rw1cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (sim) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (rw1cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *sim ^= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *sim = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spin_unlock_irqrestore(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) rv = aer_inj_write(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) spin_unlock_irqrestore(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct pci_ops aer_inj_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .read = aer_inj_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .write = aer_inj_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void pci_bus_ops_init(struct pci_bus_ops *bus_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct pci_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) INIT_LIST_HEAD(&bus_ops->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) bus_ops->bus = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) bus_ops->ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int pci_bus_set_aer_ops(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct pci_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct pci_bus_ops *bus_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) bus_ops = kmalloc(sizeof(*bus_ops), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!bus_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ops = pci_bus_set_ops(bus, &aer_inj_pci_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) spin_lock_irqsave(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ops == &aer_inj_pci_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pci_bus_ops_init(bus_ops, bus, ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) list_add(&bus_ops->list, &pci_bus_ops_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) bus_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) spin_unlock_irqrestore(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) kfree(bus_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int aer_inject(struct aer_error_inj *einj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct aer_error *err, *rperr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct aer_error *err_alloc = NULL, *rperr_alloc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct pci_dev *dev, *rpdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct pcie_device *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct device *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int pos_cap_err, rp_pos_cap_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 sever, cor_mask, uncor_mask, cor_mask_orig = 0, uncor_mask_orig = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev = pci_get_domain_bus_and_slot(einj->domain, einj->bus, devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) rpdev = pcie_find_root_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!rpdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) pci_err(dev, "Root port not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pos_cap_err = dev->aer_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!pos_cap_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pci_err(dev, "Device doesn't support AER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = -EPROTONOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_SEVER, &sever);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pci_read_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK, &cor_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) &uncor_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) rp_pos_cap_err = rpdev->aer_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!rp_pos_cap_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pci_err(rpdev, "Root port doesn't support AER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = -EPROTONOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) err_alloc = kzalloc(sizeof(struct aer_error), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!err_alloc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) rperr_alloc = kzalloc(sizeof(struct aer_error), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (!rperr_alloc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (aer_mask_override) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) cor_mask_orig = cor_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) cor_mask &= !(einj->cor_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pci_write_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) cor_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) uncor_mask_orig = uncor_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) uncor_mask &= !(einj->uncor_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pci_write_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) uncor_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) spin_lock_irqsave(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) err = __find_aer_error_by_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) err = err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) err_alloc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) aer_error_init(err, einj->domain, einj->bus, devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) pos_cap_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) list_add(&err->list, &einjected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) err->uncor_status |= einj->uncor_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) err->cor_status |= einj->cor_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) err->header_log0 = einj->header_log0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) err->header_log1 = einj->header_log1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) err->header_log2 = einj->header_log2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) err->header_log3 = einj->header_log3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!aer_mask_override && einj->cor_status &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) !(einj->cor_status & ~cor_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pci_warn(dev, "The correctable error(s) is masked by device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) spin_unlock_irqrestore(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!aer_mask_override && einj->uncor_status &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) !(einj->uncor_status & ~uncor_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pci_warn(dev, "The uncorrectable error(s) is masked by device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) spin_unlock_irqrestore(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) rperr = __find_aer_error_by_dev(rpdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!rperr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) rperr = rperr_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) rperr_alloc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) aer_error_init(rperr, pci_domain_nr(rpdev->bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) rpdev->bus->number, rpdev->devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) rp_pos_cap_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) list_add(&rperr->list, &einjected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (einj->cor_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (rperr->root_status & PCI_ERR_ROOT_COR_RCV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) rperr->root_status |= PCI_ERR_ROOT_MULTI_COR_RCV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) rperr->root_status |= PCI_ERR_ROOT_COR_RCV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) rperr->source_id &= 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) rperr->source_id |= (einj->bus << 8) | devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (einj->uncor_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) rperr->root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (sever & einj->uncor_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) rperr->root_status |= PCI_ERR_ROOT_FATAL_RCV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!(rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) rperr->root_status |= PCI_ERR_ROOT_FIRST_FATAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) rperr->root_status |= PCI_ERR_ROOT_NONFATAL_RCV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) rperr->root_status |= PCI_ERR_ROOT_UNCOR_RCV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) rperr->source_id &= 0x0000ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) rperr->source_id |= ((einj->bus << 8) | devfn) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) spin_unlock_irqrestore(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (aer_mask_override) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pci_write_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) cor_mask_orig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) pci_write_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) uncor_mask_orig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = pci_bus_set_aer_ops(dev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ret = pci_bus_set_aer_ops(rpdev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) device = pcie_port_find_device(rpdev, PCIE_PORT_SERVICE_AER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) edev = to_pcie_device(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!get_service_data(edev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pci_warn(edev->port, "AER service is not initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = -EPROTONOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pci_info(edev->port, "Injecting errors %08x/%08x into device %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) einj->cor_status, einj->uncor_status, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = irq_inject_interrupt(edev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pci_err(rpdev, "AER device not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) out_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) kfree(err_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) kfree(rperr_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pci_dev_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static ssize_t aer_inject_write(struct file *filp, const char __user *ubuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) size_t usize, loff_t *off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct aer_error_inj einj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!capable(CAP_SYS_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (usize < offsetof(struct aer_error_inj, domain) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) usize > sizeof(einj))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) memset(&einj, 0, sizeof(einj));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (copy_from_user(&einj, ubuf, usize))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = aer_inject(&einj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return ret ? ret : usize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static const struct file_operations aer_inject_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .write = aer_inject_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .llseek = noop_llseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static struct miscdevice aer_inject_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .minor = MISC_DYNAMIC_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .name = "aer_inject",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .fops = &aer_inject_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int __init aer_inject_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return misc_register(&aer_inject_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static void __exit aer_inject_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct aer_error *err, *err_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct pci_bus_ops *bus_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) misc_deregister(&aer_inject_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) while ((bus_ops = pci_bus_ops_pop())) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pci_bus_set_ops(bus_ops->bus, bus_ops->ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) kfree(bus_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) spin_lock_irqsave(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) list_for_each_entry_safe(err, err_next, &einjected, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) list_del(&err->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) kfree(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) spin_unlock_irqrestore(&inject_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) module_init(aer_inject_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) module_exit(aer_inject_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MODULE_DESCRIPTION("PCIe AER software error injector");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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