^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef DRIVERS_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define DRIVERS_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/android_kabi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* Number of possible devfns: 0.0 to 1f.7 inclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define MAX_NR_DEVFNS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PCI_FIND_CAP_TTL 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) extern const unsigned char pcie_link_speed[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) extern bool pci_early_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) bool pcie_cap_has_rtctl(const struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Functions internal to the PCI core code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int pci_create_sysfs_dev_files(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { return; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { return; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void pci_create_firmware_label_files(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void pci_remove_firmware_label_files(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void pci_cleanup_rom(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum pci_mmap_api {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum pci_mmap_api mmap_api);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int pci_probe_reset_function(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int pci_bus_error_reset(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCI_PM_D3HOT_WAIT 10 /* msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCI_PM_D3COLD_WAIT 100 /* msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * struct pci_platform_pm_ops - Firmware PM callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @bridge_d3: Does the bridge allow entering into D3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @is_manageable: returns 'true' if given device is power manageable by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * platform firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @set_state: invokes the platform firmware to set the device's power state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @get_state: queries the platform firmware for a device's current power state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @refresh_state: asks the platform to refresh the device's power state data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @choose_state: returns PCI power state of given device preferred by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * platform; to be used during system-wide transitions from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * sleeping state to the working state and vice versa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @set_wakeup: enables/disables wakeup capability for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @need_resume: returns 'true' if the given device (which is currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * suspended) needs to be resumed to be configured for system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * wakeup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * If given platform is generally capable of power managing PCI devices, all of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * these callbacks are mandatory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct pci_platform_pm_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bool (*bridge_d3)(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) bool (*is_manageable)(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int (*set_state)(struct pci_dev *dev, pci_power_t state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pci_power_t (*get_state)(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void (*refresh_state)(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pci_power_t (*choose_state)(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int (*set_wakeup)(struct pci_dev *dev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) bool (*need_resume)(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void pci_refresh_power_state(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int pci_power_up(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void pci_disable_enabled_device(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int pci_finish_runtime_suspend(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void pcie_clear_device_status(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void pcie_clear_root_pme_status(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bool pci_check_pme_status(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void pci_pme_wakeup_bus(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void pci_pme_restore(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bool pci_dev_need_resume(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void pci_dev_adjust_pme(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void pci_dev_complete_resume(struct pci_dev *pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void pci_config_pm_runtime_get(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void pci_config_pm_runtime_put(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void pci_pm_init(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void pci_ea_init(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void pci_allocate_cap_save_buffers(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void pci_free_cap_save_buffers(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bool pci_bridge_d3_possible(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void pci_bridge_d3_update(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline void pci_wakeup_event(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Wait 100 ms before the system can be put into a sleep state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pm_wakeup_event(&dev->dev, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return !!(pci_dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline bool pci_power_manageable(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Currently we allow normal PCI devices and PCI bridges transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * into D3 if their bridge_d3 is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline bool pcie_downstream_port(const struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int type = pci_pcie_type(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return type == PCI_EXP_TYPE_ROOT_PORT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) type == PCI_EXP_TYPE_DOWNSTREAM ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) type == PCI_EXP_TYPE_PCIE_BRIDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int pci_vpd_init(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void pci_vpd_release(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* PCI Virtual Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int pci_save_vc_state(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void pci_restore_vc_state(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void pci_allocate_vc_save_buffers(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* PCI /proc functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int pci_proc_attach_device(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int pci_proc_detach_device(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int pci_proc_detach_bus(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Functions for PCI Hotplug drivers to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int pci_hp_add_bridge(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #ifdef HAVE_PCI_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void pci_create_legacy_files(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void pci_remove_legacy_files(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Lock for read/write access to pci device and bus lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) extern struct rw_semaphore pci_bus_sem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) extern struct mutex pci_slot_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) extern raw_spinlock_t pci_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) extern unsigned int pci_pm_d3hot_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void pci_no_msi(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static inline void pci_no_msi(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u16 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) control &= ~PCI_MSI_FLAGS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) control |= PCI_MSI_FLAGS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ctrl &= ~clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ctrl |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void pci_realloc_get_opt(char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline int pci_no_d1d2(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int parent_dstates = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (dev->bus->self)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) parent_dstates = dev->bus->self->no_d1d2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return (dev->no_d1d2 || parent_dstates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) extern const struct attribute_group *pci_dev_groups[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) extern const struct attribute_group *pcibus_groups[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) extern const struct device_type pci_dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) extern const struct attribute_group *pci_bus_groups[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) extern unsigned long pci_hotplug_io_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) extern unsigned long pci_hotplug_mmio_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) extern unsigned long pci_hotplug_mmio_pref_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) extern unsigned long pci_hotplug_bus_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * pci_match_one_device - Tell if a PCI device structure has a matching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * PCI device id structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @id: single PCI device id structure to match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @dev: the PCI device structure to match against
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Returns the matching pci_device_id structure or %NULL if there is no match.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static inline const struct pci_device_id *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) (id->device == PCI_ANY_ID || id->device == dev->device) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) !((id->class ^ dev->class) & id->class_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* PCI slot sysfs helper code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) extern struct kset *pci_slots_kset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct pci_slot_attribute {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct attribute attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ssize_t (*show)(struct pci_slot *, char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ssize_t (*store)(struct pci_slot *, const char *, size_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) enum pci_bar_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pci_bar_unknown, /* Standard PCI BAR probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pci_bar_io, /* An I/O port BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pci_bar_mem32, /* A 32-bit memory BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pci_bar_mem64, /* A 64-bit memory BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct device *pci_get_host_bridge_device(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) void pci_put_host_bridge_device(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int crs_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int crs_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int pci_setup_device(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct resource *res, unsigned int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) void pci_configure_ari(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void __pci_bus_size_bridges(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct list_head *realloc_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) void __pci_bus_assign_resources(const struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct list_head *realloc_head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct list_head *fail_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void pci_reassigndev_resource_alignment(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void pci_disable_bridge_window(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct pci_bus *pci_bus_get(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) void pci_bus_put(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* PCIe link information from Link Capabilities 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PCI_SPEED_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* PCIe speed to Mb/s reduced by encoding overhead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define PCIE_SPEED2MBS_ENC(speed) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const char *pci_speed_string(enum pci_bus_speed speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) enum pcie_link_width *width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void pcie_report_downtraining(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Single Root I/O Virtualization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct pci_sriov {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int pos; /* Capability position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int nres; /* Number of resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 cap; /* SR-IOV Capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u16 ctrl; /* SR-IOV Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u16 total_VFs; /* Total VFs associated with the PF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u16 initial_VFs; /* Initial VFs associated with the PF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u16 num_VFs; /* Number of VFs available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u16 offset; /* First VF Routing ID offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u16 stride; /* Following VF stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u16 vf_device; /* VF device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 pgsz; /* Page size for BAR alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u8 link; /* Function Dependency Link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u8 max_VF_buses; /* Max buses consumed by VFs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u16 driver_max_VFs; /* Max num VFs driver supports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct pci_dev *dev; /* Lowest numbered PF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct pci_dev *self; /* This PF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 class; /* VF device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u8 hdr_type; /* VF header type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u16 subsystem_vendor; /* VF subsystem vendor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u16 subsystem_device; /* VF subsystem device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) bool drivers_autoprobe; /* Auto probing of VFs by driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ANDROID_KABI_RESERVE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ANDROID_KABI_RESERVE(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ANDROID_KABI_RESERVE(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ANDROID_KABI_RESERVE(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * pci_dev_set_io_state - Set the new error state if possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * @dev - pci device to set new error_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * @new - the state we want dev to be in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Must be called with device_lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Returns true if state has been changed to the requested state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static inline bool pci_dev_set_io_state(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pci_channel_state_t new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) bool changed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) device_lock_assert(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) switch (new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case pci_channel_io_perm_failure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) switch (dev->error_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case pci_channel_io_frozen:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case pci_channel_io_normal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case pci_channel_io_perm_failure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case pci_channel_io_frozen:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) switch (dev->error_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case pci_channel_io_frozen:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case pci_channel_io_normal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case pci_channel_io_normal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) switch (dev->error_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case pci_channel_io_frozen:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case pci_channel_io_normal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev->error_state = new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) device_lock(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) device_unlock(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return dev->error_state == pci_channel_io_perm_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* pci_dev priv_flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PCI_DEV_ADDED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define PCI_DPC_RECOVERED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PCI_DPC_RECOVERING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static inline bool pci_dev_is_added(const struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #ifdef CONFIG_PCIEAER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #include <linux/aer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct aer_err_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int error_dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned int id:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int __pad1:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int multi_error_valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int first_error:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned int __pad2:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned int tlp_header_valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int status; /* COR/UNCOR Error Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned int mask; /* COR/UNCOR Error Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct aer_header_log_regs tlp; /* TLP Header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #endif /* CONFIG_PCIEAER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #ifdef CONFIG_PCIE_DPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) void pci_save_dpc_state(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) void pci_restore_dpc_state(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) void pci_dpc_init(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) void dpc_process_error(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) bool pci_dpc_recovered(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static inline void pci_save_dpc_state(struct pci_dev *dev) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static inline void pci_dpc_init(struct pci_dev *pdev) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #ifdef CONFIG_PCI_ATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Address Translation Service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) void pci_ats_init(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) void pci_restore_ats_state(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static inline void pci_ats_init(struct pci_dev *d) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static inline void pci_restore_ats_state(struct pci_dev *dev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #endif /* CONFIG_PCI_ATS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #ifdef CONFIG_PCI_PRI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) void pci_pri_init(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) void pci_restore_pri_state(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static inline void pci_pri_init(struct pci_dev *dev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #ifdef CONFIG_PCI_PASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) void pci_pasid_init(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) void pci_restore_pasid_state(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static inline void pci_pasid_init(struct pci_dev *dev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #ifdef CONFIG_PCI_IOV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int pci_iov_init(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) void pci_iov_release(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) void pci_iov_remove(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) void pci_iov_update_resource(struct pci_dev *dev, int resno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) void pci_restore_iov_state(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int pci_iov_bus_range(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) extern const struct attribute_group sriov_dev_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static inline int pci_iov_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static inline void pci_iov_release(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static inline void pci_iov_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static inline void pci_restore_iov_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static inline int pci_iov_bus_range(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #endif /* CONFIG_PCI_IOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned long pci_cardbus_resource_alignment(struct resource *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #ifdef CONFIG_PCI_IOV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int resno = res - dev->resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return pci_sriov_resource_alignment(dev, resno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return pci_cardbus_resource_alignment(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return resource_alignment(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) void pci_acs_init(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #ifdef CONFIG_PCI_QUIRKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int pci_dev_specific_enable_acs(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* PCI error reporting and recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pci_channel_state_t state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) pci_ers_result_t (*reset_link)(struct pci_dev *pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #ifdef CONFIG_PCIEASPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) void pcie_aspm_init_link_state(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) void pcie_aspm_exit_link_state(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) void pcie_aspm_pm_state_change(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #ifdef CONFIG_PCIE_ECRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) void pcie_set_ecrc_checking(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) void pcie_ecrc_get_policy(char *str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static inline void pcie_ecrc_get_policy(char *str) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #ifdef CONFIG_PCIE_PTM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) void pci_ptm_init(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static inline void pci_ptm_init(struct pci_dev *dev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { return -EINVAL; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct pci_dev_reset_methods {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u16 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int (*reset)(struct pci_dev *dev, int probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #ifdef CONFIG_PCI_QUIRKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int pci_dev_specific_reset(struct pci_dev *dev, int probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct resource *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u16 segment, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static inline u64 pci_rebar_size_to_bytes(int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 1ULL << (size + 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int of_get_pci_domain_nr(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int of_pci_get_max_link_speed(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) void pci_set_of_node(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) void pci_release_of_node(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) void pci_set_bus_of_node(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) void pci_release_bus_of_node(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) of_pci_parse_bus_range(struct device_node *node, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) of_get_pci_domain_nr(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) of_pci_get_max_link_speed(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static inline void pci_set_of_node(struct pci_dev *dev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static inline void pci_release_of_node(struct pci_dev *dev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #endif /* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #ifdef CONFIG_PCIEAER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) void pci_no_aer(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) void pci_aer_init(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) void pci_aer_exit(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) extern const struct attribute_group aer_stats_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) void pci_aer_clear_fatal_status(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int pci_aer_clear_status(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int pci_aer_raw_clear_status(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static inline void pci_no_aer(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static inline void pci_aer_init(struct pci_dev *d) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static inline void pci_aer_exit(struct pci_dev *d) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int pci_acpi_program_hp_params(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #ifdef CONFIG_PCIEASPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) extern const struct attribute_group aspm_ctrl_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #endif /* DRIVERS_PCI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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