^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCI Bus Services, see include/linux/pci.h for further explanation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * David Mosberger-Tang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/logic_pio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pm_wakeup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pci_hotplug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/aer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifndef __GENKSYMS__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <trace/hooks/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_MUTEX(pci_slot_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const char *pci_power_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) EXPORT_SYMBOL_GPL(pci_power_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int isa_dma_bridge_buggy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) EXPORT_SYMBOL(isa_dma_bridge_buggy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int pci_pci_problems;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) EXPORT_SYMBOL(pci_pci_problems);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int pci_pm_d3hot_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void pci_pme_list_scan(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static LIST_HEAD(pci_pme_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static DEFINE_MUTEX(pci_pme_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct pci_pme_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PME_TIMEOUT 1000 /* How long between PME checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void pci_dev_d3_sleep(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int delay = dev->d3hot_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int err = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (delay < pci_pm_d3hot_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) delay = pci_pm_d3hot_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) trace_android_rvh_pci_d3_sleep(dev, delay, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (err == -EOPNOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) msleep(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef CONFIG_PCI_DOMAINS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int pci_domains_supported = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DEFAULT_CARDBUS_IO_SIZE (256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* pci=cbmemsize=nnM,cbiosize=nn can override this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DEFAULT_HOTPLUG_IO_SIZE (256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* hpiosize=nn can override this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * pci=hpmemsize=nnM overrides both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DEFAULT_HOTPLUG_BUS_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifdef CONFIG_PCIE_BUS_TUNE_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #elif defined CONFIG_PCIE_BUS_SAFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #elif defined CONFIG_PCIE_BUS_PERFORMANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #elif defined CONFIG_PCIE_BUS_PEER2PEER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * The default CLS is used if arch didn't set CLS explicitly and not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * all pci devices agree on the same value. Arch can override either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * the dfl or actual value as it sees fit. Don't forget this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * measured in 32-bit words, not bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 pci_cache_line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * If we set up a device for bus mastering, we need to check the latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * timer as certain BIOSes forget to set it properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int pcibios_max_latency = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* If set, the PCIe ARI capability will not be used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static bool pcie_ari_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* If set, the PCIe ATS capability will not be used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static bool pcie_ats_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* If set, the PCI config space of each device is printed during boot. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) bool pci_early_dump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) bool pci_ats_disabled(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return pcie_ats_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) EXPORT_SYMBOL_GPL(pci_ats_disabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Disable bridge_d3 for all PCIe ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static bool pci_bridge_d3_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Force bridge_d3 for all PCIe ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static bool pci_bridge_d3_force;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int __init pcie_port_pm_setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!strcmp(str, "off"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pci_bridge_d3_disable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) else if (!strcmp(str, "force"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pci_bridge_d3_force = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __setup("pcie_port_pm=", pcie_port_pm_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Time to wait after a reset for device to become responsive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PCIE_RESET_READY_POLL_MS 60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @bus: pointer to PCI bus structure to search
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Given a PCI bus, returns the highest PCI bus number present in the set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * including the given PCI bus and its list of child PCI buses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned char pci_bus_max_busnr(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct pci_bus *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned char max, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) max = bus->busn_res.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) list_for_each_entry(tmp, &bus->children, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) n = pci_bus_max_busnr(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (n > max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) max = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @pdev: the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Returns error bits set in PCI_STATUS and clears them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int pci_status_get_and_clear_errors(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = pci_read_config_word(pdev, PCI_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret != PCIBIOS_SUCCESSFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) status &= PCI_STATUS_ERROR_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pci_write_config_word(pdev, PCI_STATUS, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #ifdef CONFIG_HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct resource *res = &pdev->resource[bar];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * Make sure the BAR is actually a memory resource, not an IO resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) EXPORT_SYMBOL_GPL(pci_ioremap_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Make sure the BAR is actually a memory resource, not an IO resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return ioremap_wc(pci_resource_start(pdev, bar),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pci_resource_len(pdev, bar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * pci_dev_str_match_path - test if a path string matches a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @dev: the PCI device to test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * @path: string to match the device against
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * @endptr: pointer to the string after the match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * Test if a string (typically from a kernel parameter) formatted as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * path of device/function addresses matches a PCI device. The string must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * be of the form:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * A path for a device can be obtained using 'lspci -t'. Using a path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * is more robust against bus renumbering than using only a single bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * device and function address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Returns 1 if the string matches the device, 0 if it does not and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * a negative error code if it fails to parse the string.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) const char **endptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int seg, bus, slot, func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) char *wpath, *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) char end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *endptr = strchrnul(path, ';');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!wpath)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) p = strrchr(wpath, '/');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto free_and_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (dev->devfn != PCI_DEVFN(slot, func)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) goto free_and_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Note: we don't need to get a reference to the upstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * bridge because we hold a reference to the top level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * device which should hold a reference to the bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * and so on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev = pci_upstream_bridge(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) goto free_and_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *p = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) &func, &end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ret != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) seg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) goto free_and_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = (seg == pci_domain_nr(dev->bus) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) bus == dev->bus->number &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev->devfn == PCI_DEVFN(slot, func));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) free_and_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) kfree(wpath);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * pci_dev_str_match - test if a string matches a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * @dev: the PCI device to test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * @p: string to match the device against
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * @endptr: pointer to the string after the match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * Test if a string (typically from a kernel parameter) matches a specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * PCI device. The string may be of one of the following formats:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * The first format specifies a PCI bus/device/function address which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * may change if new hardware is inserted, if motherboard firmware changes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * or due to changes caused in kernel parameters. If the domain is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * left unspecified, it is taken to be 0. In order to be robust against
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * bus renumbering issues, a path of PCI device/function numbers may be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * to address the specific device. The path for a device can be determined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * through the use of 'lspci -t'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * The second format matches devices using IDs in the configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * space which may match multiple devices in the system. A value of 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * for any field will match all devices. (Note: this differs from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * legacy reasons and convenience so users don't have to specify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * FFFFFFFFs on the command line.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * Returns 1 if the string matches the device, 0 if it does not and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * a negative error code if the string cannot be parsed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int pci_dev_str_match(struct pci_dev *dev, const char *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) const char **endptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned short vendor, device, subsystem_vendor, subsystem_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (strncmp(p, "pci:", 4) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* PCI vendor/device (subvendor/subdevice) IDs are specified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) p += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) &subsystem_vendor, &subsystem_device, &count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (ret != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) subsystem_vendor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) subsystem_device = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) p += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if ((!vendor || vendor == dev->vendor) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) (!device || device == dev->device) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (!subsystem_vendor ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) subsystem_vendor == dev->subsystem_vendor) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) (!subsystem_device ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) subsystem_device == dev->subsystem_device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * PCI Bus, Device, Function IDs are specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * (optionally, may include a path of devfns following it)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = pci_dev_str_match_path(dev, p, &p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) else if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *endptr = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *endptr = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u8 pos, int cap, int *ttl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u16 ent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pci_bus_read_config_byte(bus, devfn, pos, &pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) while ((*ttl)--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (pos < 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pos &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pci_bus_read_config_word(bus, devfn, pos, &ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) id = ent & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (id == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (id == cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pos = (ent >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u8 pos, int cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int ttl = PCI_FIND_CAP_TTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return __pci_find_next_cap(dev->bus, dev->devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pos + PCI_CAP_LIST_NEXT, cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) EXPORT_SYMBOL_GPL(pci_find_next_capability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int __pci_bus_find_cap_start(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned int devfn, u8 hdr_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (!(status & PCI_STATUS_CAP_LIST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) switch (hdr_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case PCI_HEADER_TYPE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case PCI_HEADER_TYPE_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return PCI_CAPABILITY_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case PCI_HEADER_TYPE_CARDBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return PCI_CB_CAPABILITY_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * pci_find_capability - query for devices' capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * @cap: capability code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * Tell if a device supports a given PCI capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * Returns the address of the requested capability structure within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * device's PCI configuration space or 0 in case the device does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * support it. Possible values for @cap include:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * %PCI_CAP_ID_PM Power Management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * %PCI_CAP_ID_AGP Accelerated Graphics Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * %PCI_CAP_ID_VPD Vital Product Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * %PCI_CAP_ID_SLOTID Slot Identification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * %PCI_CAP_ID_MSI Message Signalled Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * %PCI_CAP_ID_PCIX PCI-X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * %PCI_CAP_ID_EXP PCI Express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int pci_find_capability(struct pci_dev *dev, int cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) EXPORT_SYMBOL(pci_find_capability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * pci_bus_find_capability - query for devices' capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * @bus: the PCI bus to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * @devfn: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * @cap: capability code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * Like pci_find_capability() but works for PCI devices that do not have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * pci_dev structure set up yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * Returns the address of the requested capability structure within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * device's PCI configuration space or 0 in case the device does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * support it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u8 hdr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pos = __pci_find_next_cap(bus, devfn, pos, cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) EXPORT_SYMBOL(pci_bus_find_capability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * pci_find_next_ext_capability - Find an extended capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * @start: address at which to start looking (0 to start at beginning of list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * @cap: capability code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * Returns the address of the next matching extended capability structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * within the device's PCI configuration space or 0 if the device does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * not support it. Some capabilities can occur several times, e.g., the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * vendor-specific capability, and this provides a way to find them all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int ttl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int pos = PCI_CFG_SPACE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* minimum 8 bytes per capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pos = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * If we have no capabilities, this is indicated by cap ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * cap version and next pointer all being 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (header == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) while (ttl-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (PCI_EXT_CAP_ID(header) == cap && pos != start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) pos = PCI_EXT_CAP_NEXT(header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (pos < PCI_CFG_SPACE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * pci_find_ext_capability - Find an extended capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * @cap: capability code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Returns the address of the requested extended capability structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * within the device's PCI configuration space or 0 if the device does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * not support it. Possible values for @cap include:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * %PCI_EXT_CAP_ID_VC Virtual Channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * %PCI_EXT_CAP_ID_DSN Device Serial Number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * %PCI_EXT_CAP_ID_PWR Power Budgeting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int pci_find_ext_capability(struct pci_dev *dev, int cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return pci_find_next_ext_capability(dev, 0, cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) EXPORT_SYMBOL_GPL(pci_find_ext_capability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * pci_get_dsn - Read and return the 8-byte Device Serial Number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * Number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * Returns the DSN, or zero if the capability does not exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u64 pci_get_dsn(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u32 dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u64 dsn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * The Device Serial Number is two dwords offset 4 bytes from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * capability position. The specification says that the first dword is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * the lower half, and the second dword is the upper half.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) pos += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pci_read_config_dword(dev, pos, &dword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dsn = (u64)dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pci_read_config_dword(dev, pos + 4, &dword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dsn |= ((u64)dword) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return dsn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) EXPORT_SYMBOL_GPL(pci_get_dsn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int rc, ttl = PCI_FIND_CAP_TTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u8 cap, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) mask = HT_3BIT_CAP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) mask = HT_5BIT_CAP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PCI_CAP_ID_HT, &ttl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) while (pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) rc = pci_read_config_byte(dev, pos + 3, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (rc != PCIBIOS_SUCCESSFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if ((cap & mask) == ht_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) pos + PCI_CAP_LIST_NEXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PCI_CAP_ID_HT, &ttl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * pci_find_next_ht_capability - query a device's Hypertransport capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * @pos: Position from which to continue searching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * @ht_cap: Hypertransport capability code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * To be used in conjunction with pci_find_ht_capability() to search for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * all capabilities matching @ht_cap. @pos should always be a value returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * from pci_find_ht_capability().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * NB. To be 100% safe against broken PCI devices, the caller should take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * steps to avoid an infinite loop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * pci_find_ht_capability - query a device's Hypertransport capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * @ht_cap: Hypertransport capability code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * Tell if a device supports a given Hypertransport capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * Returns an address within the device's PCI configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * or 0 in case the device does not support the request capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * The address points to the PCI capability, of type PCI_CAP_ID_HT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * which has a Hypertransport capability matching @ht_cap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) EXPORT_SYMBOL_GPL(pci_find_ht_capability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * pci_find_parent_resource - return resource region of parent bus of given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * @dev: PCI device structure contains resources to be searched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * @res: child resource record for which parent is sought
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * For given resource region of given device, return the resource region of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * parent bus the given region is contained in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct resource *pci_find_parent_resource(const struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) const struct pci_bus *bus = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pci_bus_for_each_resource(bus, r, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (resource_contains(r, res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * If the window is prefetchable but the BAR is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * not, the allocator made a mistake.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (r->flags & IORESOURCE_PREFETCH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) !(res->flags & IORESOURCE_PREFETCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * If we're below a transparent bridge, there may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * be both a positively-decoded aperture and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * subtractively-decoded region that contain the BAR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * We want the positively-decoded one, so this depends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * on pci_bus_for_each_resource() giving us those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) EXPORT_SYMBOL(pci_find_parent_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * pci_find_resource - Return matching PCI device resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * @res: Resource to look for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * Goes over standard PCI resources (BARs) and checks if the given resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * is partially or fully contained in any of them. In that case the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * matching resource is returned, %NULL otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) for (i = 0; i < PCI_STD_NUM_BARS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct resource *r = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (r->start && resource_contains(r, res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) EXPORT_SYMBOL(pci_find_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * @dev: the PCI device to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * @pos: config space offset of status word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * @mask: mask of bit(s) to care about in status word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * Return 1 when mask bit(s) in status word clear, 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Wait for Transaction Pending bit clean */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) msleep((1 << (i - 1)) * 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) pci_read_config_word(dev, pos, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (!(status & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int pci_acs_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * pci_request_acs - ask for ACS to be enabled if supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) void pci_request_acs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pci_acs_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static const char *disable_acs_redir_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * pci_disable_acs_redir - disable ACS redirect capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * @dev: the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * For only devices specified in the disable_acs_redir parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static void pci_disable_acs_redir(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) const char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!disable_acs_redir_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) p = disable_acs_redir_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) while (*p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ret = pci_dev_str_match(dev, p, &p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) disable_acs_redir_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) } else if (ret == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* Found a match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (*p != ';' && *p != ',') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* End of param or invalid format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) p++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (!pci_dev_specific_disable_acs_redir(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) pos = dev->acs_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* P2P Request & Completion Redirect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) pci_info(dev, "disabled ACS redirect\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * @dev: the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static void pci_std_enable_acs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u16 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) pos = dev->acs_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* Source Validation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ctrl |= (cap & PCI_ACS_SV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* P2P Request Redirect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ctrl |= (cap & PCI_ACS_RR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* P2P Completion Redirect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ctrl |= (cap & PCI_ACS_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* Upstream Forwarding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ctrl |= (cap & PCI_ACS_UF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* Enable Translation Blocking for external devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (dev->external_facing || dev->untrusted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ctrl |= (cap & PCI_ACS_TB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * pci_enable_acs - enable ACS if hardware support it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * @dev: the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static void pci_enable_acs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (!pci_acs_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) goto disable_acs_redir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (!pci_dev_specific_enable_acs(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) goto disable_acs_redir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) pci_std_enable_acs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) disable_acs_redir:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * Note: pci_disable_acs_redir() must be called even if ACS was not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * enabled by the kernel because it may have been enabled by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * platform firmware. So if we are told to disable it, we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * always disable it after setting the kernel's default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * preferences.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) pci_disable_acs_redir(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * @dev: PCI device to have its BARs restored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * Restore the BAR values for a given device, so as to make it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * accessible by its driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static void pci_restore_bars(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) pci_update_resource(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static const struct pci_platform_pm_ops *pci_platform_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) pci_platform_pm = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static inline bool platform_pci_power_manageable(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static inline int platform_pci_set_power_state(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) pci_power_t t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (pci_platform_pm && pci_platform_pm->refresh_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) pci_platform_pm->refresh_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return pci_platform_pm ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return pci_platform_pm ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static inline bool platform_pci_need_resume(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (pci_platform_pm && pci_platform_pm->bridge_d3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return pci_platform_pm->bridge_d3(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * pci_raw_set_power_state - Use PCI PM registers to set the power state of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * given PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * @dev: PCI device to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * -EINVAL if the requested state is invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * -EIO if device does not support PCI PM or its PM capabilities register has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * wrong version, or device doesn't support the requested state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * 0 if device already is in the requested state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * 0 if device's power state has been successfully changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) u16 pmcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) bool need_restore = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* Check if we're already there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (dev->current_state == state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (!dev->pm_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (state < PCI_D0 || state > PCI_D3hot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * Validate transition: We can enter D0 from any state, but if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * we're already in a low-power state, we can only go deeper. E.g.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * we can go from D1 to D3, but we can't go directly from D3 to D1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * we'd have to go from D3 to D0, then to D1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (state != PCI_D0 && dev->current_state <= PCI_D3cold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) && dev->current_state > state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) pci_err(dev, "invalid power transition (from %s to %s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) pci_power_name(dev->current_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) pci_power_name(state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* Check if this device supports the desired state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if ((state == PCI_D1 && !dev->d1_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) || (state == PCI_D2 && !dev->d2_support))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (pmcsr == (u16) ~0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) pci_power_name(dev->current_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) pci_power_name(state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * If we're (effectively) in D3, force entire word to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * This doesn't affect PME_Status, disables PME_En, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * sets PowerState to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) switch (dev->current_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) case PCI_D0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) case PCI_D1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) case PCI_D2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) pmcsr |= state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) case PCI_D3hot:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) case PCI_D3cold:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) case PCI_UNKNOWN: /* Boot-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) need_restore = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) fallthrough; /* force to D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) pmcsr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* Enter specified state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * Mandatory power management transition delays; see PCI PM 1.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * 5.6.1 table 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) pci_dev_d3_sleep(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) else if (state == PCI_D2 || dev->current_state == PCI_D2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) udelay(PCI_PM_D2_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (dev->current_state != state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) pci_info_ratelimited(dev, "refused to change power state from %s to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) pci_power_name(dev->current_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) pci_power_name(state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * from D3hot to D0 _may_ perform an internal reset, thereby
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * going to "D0 Uninitialized" rather than "D0 Initialized".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * For example, at least some versions of the 3c905B and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * 3c556B exhibit this behaviour.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * devices in a D3hot state at boot. Consequently, we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * restore at least the BARs so that the device will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * accessible to its driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (need_restore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) pci_restore_bars(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (dev->bus->self)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) pcie_aspm_pm_state_change(dev->bus->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * pci_update_current_state - Read power state of given device and cache it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * @dev: PCI device to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * @state: State to cache in case the device doesn't have the PM capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * The power state is read from the PMCSR register, which however is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * inaccessible in D3cold. The platform firmware is therefore queried first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * to detect accessibility of the register. In case the platform firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * reports an incorrect state or the device isn't power manageable by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * platform at all, we try to detect D3cold by testing accessibility of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * vendor ID in config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (platform_pci_get_power_state(dev) == PCI_D3cold ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) !pci_device_is_present(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dev->current_state = PCI_D3cold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) } else if (dev->pm_cap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) u16 pmcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dev->current_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * pci_refresh_power_state - Refresh the given device's power state data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * @dev: Target PCI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * Ask the platform to refresh the devices power state information and invoke
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * pci_update_current_state() to update its current PCI power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) void pci_refresh_power_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (platform_pci_power_manageable(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) platform_pci_refresh_power_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) pci_update_current_state(dev, dev->current_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * pci_platform_power_transition - Use platform to change device power state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * @dev: PCI device to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * @state: State to put the device into.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (platform_pci_power_manageable(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) error = platform_pci_set_power_state(dev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (!error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) pci_update_current_state(dev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) error = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dev->current_state = PCI_D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) EXPORT_SYMBOL_GPL(pci_platform_power_transition);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * pci_wakeup - Wake up a PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * @pci_dev: Device to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * @ign: ignored parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) pci_wakeup_event(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) pm_request_resume(&pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * pci_wakeup_bus - Walk given bus and wake up devices on it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * @bus: Top bus of the subtree to walk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) void pci_wakeup_bus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) pci_walk_bus(bus, pci_wakeup, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) int delay = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * After reset, the device should not silently discard config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * requests, but it may still indicate that it needs more time by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * responding to them with CRS completions. The Root Port will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * generally synthesize ~0 data to complete the read (except when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * CRS SV is enabled and the read was for the Vendor ID; in that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * case it synthesizes 0x0001 data).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * Wait for the device to return a non-CRS completion. Read the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * Command register instead of Vendor ID so we don't have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * contend with the CRS SV value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) pci_read_config_dword(dev, PCI_COMMAND, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) while (id == ~0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (delay > timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) pci_warn(dev, "not ready %dms after %s; giving up\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) delay - 1, reset_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (delay > 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) pci_info(dev, "not ready %dms after %s; waiting\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) delay - 1, reset_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) msleep(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) delay *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) pci_read_config_dword(dev, PCI_COMMAND, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (delay > 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) pci_info(dev, "ready %dms after %s\n", delay - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) reset_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * pci_power_up - Put the given device into D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * @dev: PCI device to power up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) int pci_power_up(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) pci_platform_power_transition(dev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * Mandatory power management transition delays are handled in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * corresponding bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (dev->runtime_d3cold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * When powering on a bridge from D3cold, the whole hierarchy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * may be powered on into D0uninitialized state, resume them to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * give them a chance to suspend again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) pci_wakeup_bus(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return pci_raw_set_power_state(dev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * __pci_dev_set_current_state - Set current state of a PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * @dev: Device to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * @data: pointer to state to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) pci_power_t state = *(pci_power_t *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) dev->current_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * pci_bus_set_current_state - Walk given bus and set current state of devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * @bus: Top bus of the subtree to walk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * @state: state to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) pci_walk_bus(bus, __pci_dev_set_current_state, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * pci_set_power_state - Set the power state of a PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * @dev: PCI device to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * Transition a device to a new power state, using the platform firmware and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) * the device's PCI PM registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) * RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * -EINVAL if the requested state is invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) * -EIO if device does not support PCI PM or its PM capabilities register has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * wrong version, or device doesn't support the requested state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * 0 if device already is in the requested state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * 0 if the transition is to D3 but D3 is not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * 0 if device's power state has been successfully changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* Bound the state we're entering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (state > PCI_D3cold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) state = PCI_D3cold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) else if (state < PCI_D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) state = PCI_D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * If the device or the parent bridge do not support PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * PM, ignore the request if we're doing anything other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * than putting it into D0 (which would only happen on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * boot).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* Check if we're already there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (dev->current_state == state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (state == PCI_D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return pci_power_up(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * This device is quirked not to be put into D3, so don't put it in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * D3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * To put device in D3cold, we put device into D3hot in native
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * way, then put device into D3cold with platform ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) PCI_D3hot : state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (pci_platform_power_transition(dev, state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* Powering off a bridge may power off the whole hierarchy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (state == PCI_D3cold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) EXPORT_SYMBOL(pci_set_power_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * pci_choose_state - Choose the power state of a PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) * @dev: PCI device to be suspended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) * @state: target sleep state for the whole system. This is the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * that is passed to suspend() function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * Returns PCI power state suitable for given device and given system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) pci_power_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (!dev->pm_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return PCI_D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ret = platform_pci_choose_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (ret != PCI_POWER_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) switch (state.event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) case PM_EVENT_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return PCI_D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) case PM_EVENT_FREEZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) case PM_EVENT_PRETHAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* REVISIT both freeze and pre-thaw "should" use D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) case PM_EVENT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) case PM_EVENT_HIBERNATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return PCI_D3hot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) pci_info(dev, "unrecognized suspend event %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) state.event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) return PCI_D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) EXPORT_SYMBOL(pci_choose_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define PCI_EXP_SAVE_REGS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) u16 cap, bool extended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct pci_cap_saved_state *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return _pci_find_saved_cap(dev, cap, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) return _pci_find_saved_cap(dev, cap, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static int pci_save_pcie_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) struct pci_cap_saved_state *save_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) u16 *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (!pci_is_pcie(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (!save_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) pci_err(dev, "buffer not found in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) cap = (u16 *)&save_state->cap.data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static void pci_restore_pcie_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) struct pci_cap_saved_state *save_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) u16 *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (!save_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) cap = (u16 *)&save_state->cap.data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static int pci_save_pcix_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) struct pci_cap_saved_state *save_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (!save_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) pci_err(dev, "buffer not found in %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) pci_read_config_word(dev, pos + PCI_X_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) (u16 *)save_state->cap.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static void pci_restore_pcix_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) int i = 0, pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) struct pci_cap_saved_state *save_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) u16 *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (!save_state || !pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) cap = (u16 *)&save_state->cap.data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static void pci_save_ltr_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) int ltr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) struct pci_cap_saved_state *save_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) u16 *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (!pci_is_pcie(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (!ltr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (!save_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) cap = (u16 *)&save_state->cap.data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static void pci_restore_ltr_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) struct pci_cap_saved_state *save_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) int ltr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) u16 *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (!save_state || !ltr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) cap = (u16 *)&save_state->cap.data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * pci_save_state - save the PCI configuration space of a device before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * suspending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * @dev: PCI device that we're dealing with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) int pci_save_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /* XXX: 100% dword access ok here? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) i * 4, dev->saved_config_space[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dev->state_saved = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) i = pci_save_pcie_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (i != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) i = pci_save_pcix_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (i != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) pci_save_ltr_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) pci_save_dpc_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) pci_save_aer_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) return pci_save_vc_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) EXPORT_SYMBOL(pci_save_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) u32 saved_val, int retry, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) pci_read_config_dword(pdev, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (!force && val == saved_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) offset, val, saved_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) pci_write_config_dword(pdev, offset, saved_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (retry-- <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) pci_read_config_dword(pdev, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (val == saved_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static void pci_restore_config_space_range(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) int start, int end, int retry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) for (index = end; index >= start; index--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) pci_restore_config_dword(pdev, 4 * index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) pdev->saved_config_space[index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) retry, force);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static void pci_restore_config_space(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) pci_restore_config_space_range(pdev, 10, 15, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) /* Restore BARs before the command register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) pci_restore_config_space_range(pdev, 4, 9, 10, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) pci_restore_config_space_range(pdev, 0, 3, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) pci_restore_config_space_range(pdev, 12, 15, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * Force rewriting of prefetch registers to avoid S3 resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * issues on Intel PCI bridges that occur when these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * registers are not explicitly written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) pci_restore_config_space_range(pdev, 9, 11, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) pci_restore_config_space_range(pdev, 0, 8, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) pci_restore_config_space_range(pdev, 0, 15, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static void pci_restore_rebar_state(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) unsigned int pos, nbars, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) PCI_REBAR_CTRL_NBAR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) for (i = 0; i < nbars; i++, pos += 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) int bar_idx, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) res = pdev->resource + bar_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) size = ilog2(resource_size(res)) - 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) * pci_restore_state - Restore the saved state of a PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) * @dev: PCI device that we're dealing with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) void pci_restore_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (!dev->state_saved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) * Restore max latencies (in the LTR capability) before enabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) * LTR itself (in the PCIe capability).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) pci_restore_ltr_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) pci_restore_pcie_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) pci_restore_pasid_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) pci_restore_pri_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) pci_restore_ats_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) pci_restore_vc_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) pci_restore_rebar_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) pci_restore_dpc_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) pci_aer_clear_status(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) pci_restore_aer_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) pci_restore_config_space(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) pci_restore_pcix_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) pci_restore_msi_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) /* Restore ACS and IOV configuration state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) pci_enable_acs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) pci_restore_iov_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) dev->state_saved = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) EXPORT_SYMBOL(pci_restore_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct pci_saved_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) u32 config_space[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) struct pci_cap_saved_data cap[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) * pci_store_saved_state - Allocate and return an opaque struct containing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) * the device saved state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) * @dev: PCI device that we're dealing with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) * Return NULL if no state or error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) struct pci_saved_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) struct pci_cap_saved_state *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) struct pci_cap_saved_data *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (!dev->state_saved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) state = kzalloc(size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) memcpy(state->config_space, dev->saved_config_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) sizeof(state->config_space));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) cap = state->cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) memcpy(cap, &tmp->cap, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) /* Empty cap_save terminates list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) return state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) EXPORT_SYMBOL_GPL(pci_store_saved_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * pci_load_saved_state - Reload the provided save state into struct pci_dev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * @dev: PCI device that we're dealing with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * @state: Saved state returned from pci_store_saved_state()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) int pci_load_saved_state(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) struct pci_saved_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) struct pci_cap_saved_data *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) dev->state_saved = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) memcpy(dev->saved_config_space, state->config_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) sizeof(state->config_space));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) cap = state->cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) while (cap->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) struct pci_cap_saved_state *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if (!tmp || tmp->cap.size != cap->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) memcpy(tmp->cap.data, cap->data, tmp->cap.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) cap = (struct pci_cap_saved_data *)((u8 *)cap +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) sizeof(struct pci_cap_saved_data) + cap->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) dev->state_saved = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) EXPORT_SYMBOL_GPL(pci_load_saved_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * pci_load_and_free_saved_state - Reload the save state pointed to by state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) * and free the memory allocated for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) * @dev: PCI device that we're dealing with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) * @state: Pointer to saved state returned from pci_store_saved_state()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) int pci_load_and_free_saved_state(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) struct pci_saved_state **state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) int ret = pci_load_saved_state(dev, *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) kfree(*state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) return pci_enable_resources(dev, bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static int do_pci_enable_device(struct pci_dev *dev, int bars)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) u8 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) err = pci_set_power_state(dev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (err < 0 && err != -EIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) bridge = pci_upstream_bridge(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) pcie_aspm_powersave_config_link(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) err = pcibios_enable_device(dev, bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) pci_fixup_device(pci_fixup_enable, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (dev->msi_enabled || dev->msix_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) if (pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) pci_read_config_word(dev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) if (cmd & PCI_COMMAND_INTX_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) pci_write_config_word(dev, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) cmd & ~PCI_COMMAND_INTX_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * pci_reenable_device - Resume abandoned device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) * @dev: PCI device to be resumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) * NOTE: This function is a backend of pci_default_resume() and is not supposed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) * to be called by normal code, write proper resume handler and use it instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) int pci_reenable_device(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (pci_is_enabled(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) EXPORT_SYMBOL(pci_reenable_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) static void pci_enable_bridge(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) bridge = pci_upstream_bridge(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) if (bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) pci_enable_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) if (pci_is_enabled(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (!dev->is_busmaster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) retval = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) pci_err(dev, "Error enabling bridge (%d), continuing\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) int i, bars = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) * Power state could be unknown at this point, either due to a fresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) * boot or a device removal call. So get the current power state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) * so that things like MSI message writing will behave as expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) * (e.g. if the device really is in D0 at enable time).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) pci_update_current_state(dev, dev->current_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) if (atomic_inc_return(&dev->enable_cnt) > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) return 0; /* already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) bridge = pci_upstream_bridge(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) pci_enable_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) /* only skip sriov related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) for (i = 0; i <= PCI_ROM_RESOURCE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) if (dev->resource[i].flags & flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) bars |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (dev->resource[i].flags & flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) bars |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) err = do_pci_enable_device(dev, bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) atomic_dec(&dev->enable_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) * pci_enable_device_io - Initialize a device for use with IO space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) * @dev: PCI device to be initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) * Initialize device before it's used by a driver. Ask low-level code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) * to enable I/O resources. Wake up the device if it was suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) * Beware, this function can fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) int pci_enable_device_io(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) return pci_enable_device_flags(dev, IORESOURCE_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) EXPORT_SYMBOL(pci_enable_device_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) * pci_enable_device_mem - Initialize a device for use with Memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) * @dev: PCI device to be initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) * Initialize device before it's used by a driver. Ask low-level code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) * to enable Memory resources. Wake up the device if it was suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) * Beware, this function can fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) int pci_enable_device_mem(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) return pci_enable_device_flags(dev, IORESOURCE_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) EXPORT_SYMBOL(pci_enable_device_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * pci_enable_device - Initialize device before it's used by a driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) * @dev: PCI device to be initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) * Initialize device before it's used by a driver. Ask low-level code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) * to enable I/O and memory. Wake up the device if it was suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) * Beware, this function can fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) * Note we don't actually enable the device many times if we call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) * this function repeatedly (we just increment the count).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) int pci_enable_device(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) EXPORT_SYMBOL(pci_enable_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) * there's no need to track it separately. pci_devres is initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) * when a device is enabled using managed PCI device enable interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) struct pci_devres {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) unsigned int enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) unsigned int pinned:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) unsigned int orig_intx:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) unsigned int restore_intx:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) unsigned int mwi:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) u32 region_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) static void pcim_release(struct device *gendev, void *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) struct pci_dev *dev = to_pci_dev(gendev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) struct pci_devres *this = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (dev->msi_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) pci_disable_msi(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) if (dev->msix_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) pci_disable_msix(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (this->region_mask & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) pci_release_region(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (this->mwi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) pci_clear_mwi(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (this->restore_intx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) pci_intx(dev, this->orig_intx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (this->enabled && !this->pinned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) struct pci_devres *dr, *new_dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) if (dr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) return dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (!new_dr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) return devres_get(&pdev->dev, new_dr, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) if (pci_is_managed(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) return devres_find(&pdev->dev, pcim_release, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) * pcim_enable_device - Managed pci_enable_device()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) * @pdev: PCI device to be initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) * Managed pci_enable_device().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) int pcim_enable_device(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) struct pci_devres *dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) dr = get_pci_dr(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) if (unlikely(!dr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (dr->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) rc = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) pdev->is_managed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) dr->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) EXPORT_SYMBOL(pcim_enable_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) * pcim_pin_device - Pin managed PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) * @pdev: PCI device to pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) * Pin managed PCI device @pdev. Pinned device won't be disabled on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) * driver detach. @pdev must have been enabled with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) * pcim_enable_device().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) void pcim_pin_device(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) struct pci_devres *dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) dr = find_pci_dr(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) WARN_ON(!dr || !dr->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) if (dr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) dr->pinned = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) EXPORT_SYMBOL(pcim_pin_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * pcibios_add_device - provide arch specific hooks when adding device dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) * @dev: the PCI device being added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) * Permits the platform to provide architecture specific functionality when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) * devices are added. This is the default implementation. Architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) * implementations can override this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) int __weak pcibios_add_device(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) * pcibios_release_device - provide arch specific hooks when releasing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) * device dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) * @dev: the PCI device being released
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) * Permits the platform to provide architecture specific functionality when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) * devices are released. This is the default implementation. Architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) * implementations can override this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) void __weak pcibios_release_device(struct pci_dev *dev) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) * pcibios_disable_device - disable arch specific PCI resources for device dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) * @dev: the PCI device to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) * Disables architecture specific PCI resources for the device. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) * is the default implementation. Architecture implementations can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) * override this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) void __weak pcibios_disable_device(struct pci_dev *dev) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) * pcibios_penalize_isa_irq - penalize an ISA IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) * @irq: ISA IRQ to penalize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) * @active: IRQ active or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) * Permits the platform to provide architecture-specific functionality when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) * penalizing ISA IRQs. This is the default implementation. Architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) * implementations can override this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) void __weak pcibios_penalize_isa_irq(int irq, int active) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) static void do_pci_disable_device(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) u16 pci_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) pci_read_config_word(dev, PCI_COMMAND, &pci_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) if (pci_command & PCI_COMMAND_MASTER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) pci_command &= ~PCI_COMMAND_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) pci_write_config_word(dev, PCI_COMMAND, pci_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) pcibios_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) * pci_disable_enabled_device - Disable device without updating enable_cnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) * @dev: PCI device to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) * NOTE: This function is a backend of PCI power management routines and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) * not supposed to be called drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) void pci_disable_enabled_device(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) if (pci_is_enabled(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) do_pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) * pci_disable_device - Disable PCI device after use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) * @dev: PCI device to be disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) * Signal to the system that the PCI device is not in use by the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) * anymore. This only involves disabling PCI bus-mastering, if active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) * Note we don't actually disable the device until all callers of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) * pci_enable_device() have called pci_disable_device().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) void pci_disable_device(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) struct pci_devres *dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) dr = find_pci_dr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) if (dr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) dr->enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) "disabling already-disabled device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (atomic_dec_return(&dev->enable_cnt) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) do_pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) dev->is_busmaster = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) EXPORT_SYMBOL(pci_disable_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) * pcibios_set_pcie_reset_state - set reset state for device dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) * @dev: the PCIe device reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) * @state: Reset state to enter into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) * Set the PCIe reset state for the device. This is the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) * implementation. Architecture implementations can override this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) enum pcie_reset_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) * pci_set_pcie_reset_state - set reset state for device dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) * @dev: the PCIe device reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) * @state: Reset state to enter into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) * Sets the PCI reset state for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) return pcibios_set_pcie_reset_state(dev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) void pcie_clear_device_status(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) u16 sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) * pcie_clear_root_pme_status - Clear root port PME interrupt status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) * @dev: PCIe root port or event collector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) void pcie_clear_root_pme_status(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) * pci_check_pme_status - Check if given device has generated PME.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) * @dev: Device to check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) * Check the PME status of the device and if set, clear it and clear PME enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) * (if set). Return 'true' if PME status and PME enable were both set or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) * 'false' otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) bool pci_check_pme_status(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) int pmcsr_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) u16 pmcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) bool ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) if (!dev->pm_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) pci_read_config_word(dev, pmcsr_pos, &pmcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) /* Clear PME status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) pmcsr |= PCI_PM_CTRL_PME_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) /* Disable PME to avoid interrupt flood. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) pci_write_config_word(dev, pmcsr_pos, pmcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) * @dev: Device to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) * Check if @dev has generated PME and queue a resume request for it in that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) * case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) if (pme_poll_reset && dev->pme_poll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) dev->pme_poll = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) if (pci_check_pme_status(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) pci_wakeup_event(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) pm_request_resume(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) * @bus: Top bus of the subtree to walk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) void pci_pme_wakeup_bus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) if (bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) * pci_pme_capable - check the capability of PCI device to generate PME#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) * @dev: PCI device to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) * @state: PCI state from which device will issue PME#.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (!dev->pm_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) return !!(dev->pme_support & (1 << state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) EXPORT_SYMBOL(pci_pme_capable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) static void pci_pme_list_scan(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) struct pci_pme_device *pme_dev, *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) mutex_lock(&pci_pme_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) if (pme_dev->dev->pme_poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) bridge = pme_dev->dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) * If bridge is in low power state, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) * configuration space of subordinate devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) * may be not accessible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) if (bridge && bridge->current_state != PCI_D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) * If the device is in D3cold it should not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) * polled either.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) if (pme_dev->dev->current_state == PCI_D3cold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) pci_pme_wakeup(pme_dev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) list_del(&pme_dev->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) kfree(pme_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) if (!list_empty(&pci_pme_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) queue_delayed_work(system_freezable_wq, &pci_pme_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) msecs_to_jiffies(PME_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) mutex_unlock(&pci_pme_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) static void __pci_pme_active(struct pci_dev *dev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) u16 pmcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) if (!dev->pme_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) /* Clear PME_Status by writing 1 to it and enable PME# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) * pci_pme_restore - Restore PME configuration after config space restore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) * @dev: PCI device to update.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) void pci_pme_restore(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) u16 pmcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if (!dev->pme_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) if (dev->wakeup_prepared) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) pmcsr |= PCI_PM_CTRL_PME_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) pmcsr |= PCI_PM_CTRL_PME_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) * pci_pme_active - enable or disable PCI device's PME# function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) * @dev: PCI device to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) * @enable: 'true' to enable PME# generation; 'false' to disable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) * The caller must verify that the device is capable of generating PME# before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) * calling this function with @enable equal to 'true'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) void pci_pme_active(struct pci_dev *dev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) __pci_pme_active(dev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) * PCI (as opposed to PCIe) PME requires that the device have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) * its PME# line hooked up correctly. Not all hardware vendors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) * do this, so the PME never gets delivered and the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) * remains asleep. The easiest way around this is to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) * periodically walk the list of suspended devices and check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) * whether any have their PME flag set. The assumption is that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) * we'll wake up often enough anyway that this won't be a huge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) * hit, and the power savings from the devices will still be a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) * win.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) * Although PCIe uses in-band PME message instead of PME# line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) * to report PME, PME does not work for some PCIe devices in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) * reality. For example, there are devices that set their PME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) * status bits, but don't really bother to send a PME message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) * there are PCI Express Root Ports that don't bother to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) * trigger interrupts when they receive PME messages from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) * devices below. So PME poll is used for PCIe devices too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if (dev->pme_poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) struct pci_pme_device *pme_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) pme_dev = kmalloc(sizeof(struct pci_pme_device),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) if (!pme_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) pci_warn(dev, "can't enable PME#\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) pme_dev->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) mutex_lock(&pci_pme_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) list_add(&pme_dev->list, &pci_pme_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) if (list_is_singular(&pci_pme_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) queue_delayed_work(system_freezable_wq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) &pci_pme_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) msecs_to_jiffies(PME_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) mutex_unlock(&pci_pme_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) mutex_lock(&pci_pme_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) list_for_each_entry(pme_dev, &pci_pme_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) if (pme_dev->dev == dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) list_del(&pme_dev->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) kfree(pme_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) mutex_unlock(&pci_pme_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) EXPORT_SYMBOL(pci_pme_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) * __pci_enable_wake - enable PCI device as wakeup event source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) * @dev: PCI device affected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) * @state: PCI state from which device will issue wakeup events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) * @enable: True to enable event generation; false to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) * This enables the device as a wakeup event source, or disables it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) * When such events involves platform-specific hooks, those hooks are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) * called automatically by this routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) * Devices with legacy power management (no standard PCI PM capabilities)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) * always require such platform hooks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) * RETURN VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) * 0 is returned on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) * -EINVAL is returned if device is not supposed to wake up the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) * Error code depending on the platform is returned if both the platform and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) * the native mechanism fail to enable the generation of wake-up events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) * Bridges that are not power-manageable directly only signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) * wakeup on behalf of subordinate devices which is set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) * elsewhere, so skip them. However, bridges that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) * power-manageable may signal wakeup for themselves (for example,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) * on a hotplug event) and they need to be covered here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) if (!pci_power_manageable(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) /* Don't do the same thing twice in a row for one device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) if (!!enable == !!dev->wakeup_prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) * Anderson we should be doing PME# wake enable followed by ACPI wake
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) * enable. To disable wake-up we call the platform first, for symmetry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) * Enable PME signaling if the device can signal PME from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) * D3cold regardless of whether or not it can signal PME from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) * the current target state, because that will allow it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) * signal PME when the hierarchy above it goes into D3cold and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) * the device itself ends up in D3cold as a result of that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) pci_pme_active(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) error = platform_pci_set_wakeup(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) ret = error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) dev->wakeup_prepared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) platform_pci_set_wakeup(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) pci_pme_active(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) dev->wakeup_prepared = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) * pci_enable_wake - change wakeup settings for a PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) * @pci_dev: Target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) * @state: PCI state from which device will issue wakeup events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) * @enable: Whether or not to enable event generation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) * If @enable is set, check device_may_wakeup() for the device before calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) * __pci_enable_wake() for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) if (enable && !device_may_wakeup(&pci_dev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) return __pci_enable_wake(pci_dev, state, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) EXPORT_SYMBOL(pci_enable_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) * @dev: PCI device to prepare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) * @enable: True to enable wake-up event generation; false to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) * Many drivers want the device to wake up the system from D3_hot or D3_cold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) * and this function allows them to set that up cleanly - pci_enable_wake()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) * ordering constraints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) * This function only returns error code if the device is not allowed to wake
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) * up the system from sleep or it is not capable of generating PME# from both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) int pci_wake_from_d3(struct pci_dev *dev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) return pci_pme_capable(dev, PCI_D3cold) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) pci_enable_wake(dev, PCI_D3cold, enable) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) pci_enable_wake(dev, PCI_D3hot, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) EXPORT_SYMBOL(pci_wake_from_d3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) * pci_target_state - find an appropriate low power state for a given PCI dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) * @wakeup: Whether or not wakeup functionality will be enabled for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) * Use underlying platform code to find a supported low power state for @dev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) * If the platform can't manage @dev, return the deepest state from which it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) * can generate wake events, based on any available PME info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) pci_power_t target_state = PCI_D3hot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) if (platform_pci_power_manageable(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) * Call the platform to find the target state for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) pci_power_t state = platform_pci_choose_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) case PCI_POWER_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) case PCI_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) case PCI_D1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) case PCI_D2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) if (pci_no_d1d2(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) target_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) return target_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) if (!dev->pm_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) target_state = PCI_D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) * If the device is in D3cold even though it's not power-manageable by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) * the platform, it may have been powered down by non-standard means.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) * Best to let it slumber.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) if (dev->current_state == PCI_D3cold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) target_state = PCI_D3cold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) if (wakeup && dev->pme_support) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) pci_power_t state = target_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) * Find the deepest state from which the device can generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) * PME#.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) while (state && !(dev->pme_support & (1 << state)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) state--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) return state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) else if (dev->pme_support & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) return PCI_D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) return target_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) * pci_prepare_to_sleep - prepare PCI device for system-wide transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) * into a sleep state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) * @dev: Device to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) * Choose the power state appropriate for the device depending on whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) * it can wake up the system and/or is power manageable by the platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) * (PCI_D3hot is the default) and put the device into that state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) int pci_prepare_to_sleep(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) bool wakeup = device_may_wakeup(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) pci_power_t target_state = pci_target_state(dev, wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) if (target_state == PCI_POWER_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) pci_enable_wake(dev, target_state, wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) error = pci_set_power_state(dev, target_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) pci_enable_wake(dev, target_state, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) EXPORT_SYMBOL(pci_prepare_to_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) * pci_back_from_sleep - turn PCI device on during system-wide transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) * into working state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) * @dev: Device to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) * Disable device's system wake-up capability and put it into D0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) int pci_back_from_sleep(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) pci_enable_wake(dev, PCI_D0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) return pci_set_power_state(dev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) EXPORT_SYMBOL(pci_back_from_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) * @dev: PCI device being suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) * Prepare @dev to generate wake-up events at run time and put it into a low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) * power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) int pci_finish_runtime_suspend(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) pci_power_t target_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) if (target_state == PCI_POWER_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) dev->runtime_d3cold = target_state == PCI_D3cold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) error = pci_set_power_state(dev, target_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) pci_enable_wake(dev, target_state, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) dev->runtime_d3cold = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) * pci_dev_run_wake - Check if device can generate run-time wake-up events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) * @dev: Device to check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) * Return true if the device itself is capable of generating wake-up events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) * (through the platform or using the native PCIe PME) or if the device supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) * PME and one of its upstream bridges can generate wake-up events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) bool pci_dev_run_wake(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) struct pci_bus *bus = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) if (!dev->pme_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) /* PME-capable in principle, but not from the target power state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) if (!pci_pme_capable(dev, pci_target_state(dev, true)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) if (device_can_wakeup(&dev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) while (bus->parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) struct pci_dev *bridge = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) if (device_can_wakeup(&bridge->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) bus = bus->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) /* We have reached the root bus. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) if (bus->bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) return device_can_wakeup(bus->bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) EXPORT_SYMBOL_GPL(pci_dev_run_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) * pci_dev_need_resume - Check if it is necessary to resume the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) * @pci_dev: Device to check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) * Return 'true' if the device is not runtime-suspended or it has to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) * reconfigured due to wakeup settings difference between system and runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) * suspend, or the current power state of it is not suitable for the upcoming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) * (system-wide) transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) bool pci_dev_need_resume(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) struct device *dev = &pci_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) pci_power_t target_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) * If the earlier platform check has not triggered, D3cold is just power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) * removal on top of D3hot, so no need to resume the device in that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) * case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) return target_state != pci_dev->current_state &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) target_state != PCI_D3cold &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) pci_dev->current_state != PCI_D3hot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) * @pci_dev: Device to check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) * If the device is suspended and it is not configured for system wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) * disable PME for it to prevent it from waking up the system unnecessarily.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) * Note that if the device's power state is D3cold and the platform check in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) * pci_dev_need_resume() has not triggered, the device's configuration need not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) * be changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) void pci_dev_adjust_pme(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) struct device *dev = &pci_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) spin_lock_irq(&dev->power.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) pci_dev->current_state < PCI_D3cold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) __pci_pme_active(pci_dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) spin_unlock_irq(&dev->power.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) * pci_dev_complete_resume - Finalize resume from system sleep for a device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) * @pci_dev: Device to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) * If the device is runtime suspended and wakeup-capable, enable PME for it as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) * it might have been disabled during the prepare phase of system suspend if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) * the device was not configured for system wakeup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) void pci_dev_complete_resume(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) struct device *dev = &pci_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) if (!pci_dev_run_wake(pci_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) spin_lock_irq(&dev->power.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) __pci_pme_active(pci_dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) spin_unlock_irq(&dev->power.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) void pci_config_pm_runtime_get(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) struct device *parent = dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) if (parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) pm_runtime_get_sync(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) pm_runtime_get_noresume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) * pdev->current_state is set to PCI_D3cold during suspending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) * so wait until suspending completes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) pm_runtime_barrier(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) * Only need to resume devices in D3cold, because config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) * registers are still accessible for devices suspended but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) * not in D3cold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) if (pdev->current_state == PCI_D3cold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) pm_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) void pci_config_pm_runtime_put(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) struct device *parent = dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) if (parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) pm_runtime_put_sync(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) static const struct dmi_system_id bridge_d3_blacklist[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) * Gigabyte X299 root port is not marked as hotplug capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) * which allows Linux to power manage it. However, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) * confuses the BIOS SMI handler so don't power manage root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) * ports on that system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) .ident = "X299 DESIGNARE EX-CF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) * pci_bridge_d3_possible - Is it possible to put the bridge into D3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) * @bridge: Bridge to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) * This function checks if it is possible to move the bridge to D3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) bool pci_bridge_d3_possible(struct pci_dev *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) if (!pci_is_pcie(bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) switch (pci_pcie_type(bridge)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) case PCI_EXP_TYPE_ROOT_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) case PCI_EXP_TYPE_UPSTREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) case PCI_EXP_TYPE_DOWNSTREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) if (pci_bridge_d3_disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) * Hotplug ports handled by firmware in System Management Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) * may not be put into D3 by the OS (Thunderbolt on non-Macs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) if (pci_bridge_d3_force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) /* Even the oldest 2010 Thunderbolt controller supports D3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) if (bridge->is_thunderbolt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) /* Platform might know better if the bridge supports D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) if (platform_pci_bridge_d3(bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) * Hotplug ports handled natively by the OS were not validated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) * by vendors for runtime D3 at least until 2018 because there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) * was no OS support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) if (bridge->is_hotplug_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) if (dmi_check_system(bridge_d3_blacklist))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) * It should be safe to put PCIe ports from 2015 or newer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) * to D3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) if (dmi_get_bios_year() >= 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) bool *d3cold_ok = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) if (/* The device needs to be allowed to go D3cold ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) dev->no_d3cold || !dev->d3cold_allowed ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) /* ... and if it is wakeup capable to do so from D3cold. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) (device_may_wakeup(&dev->dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) !pci_pme_capable(dev, PCI_D3cold)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) /* If it is a bridge it must be allowed to go to D3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) !pci_power_manageable(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) *d3cold_ok = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) return !*d3cold_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) * pci_bridge_d3_update - Update bridge D3 capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) * @dev: PCI device which is changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) * Update upstream bridge PM capabilities accordingly depending on if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) * device PM configuration was changed or the device is being removed. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) * change is also propagated upstream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) void pci_bridge_d3_update(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) bool remove = !device_is_registered(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) bool d3cold_ok = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) bridge = pci_upstream_bridge(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) if (!bridge || !pci_bridge_d3_possible(bridge))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) * If D3 is currently allowed for the bridge, removing one of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) * children won't change that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) if (remove && bridge->bridge_d3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) * If D3 is currently allowed for the bridge and a child is added or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) * changed, disallowance of D3 can only be caused by that child, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) * we only need to check that single device, not any of its siblings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) * If D3 is currently not allowed for the bridge, checking the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) * first may allow us to skip checking its siblings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) if (!remove)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) pci_dev_check_d3cold(dev, &d3cold_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) * If D3 is currently not allowed for the bridge, this may be caused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) * either by the device being changed/removed or any of its siblings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) * so we need to go through all children to find out if one of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) * continues to block D3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) if (d3cold_ok && !bridge->bridge_d3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) &d3cold_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) if (bridge->bridge_d3 != d3cold_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) bridge->bridge_d3 = d3cold_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) /* Propagate change to upstream bridges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) pci_bridge_d3_update(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) * pci_d3cold_enable - Enable D3cold for device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) * @dev: PCI device to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) * This function can be used in drivers to enable D3cold from the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) * they handle. It also updates upstream PCI bridge PM capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) * accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) void pci_d3cold_enable(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) if (dev->no_d3cold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) dev->no_d3cold = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) pci_bridge_d3_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) EXPORT_SYMBOL_GPL(pci_d3cold_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) * pci_d3cold_disable - Disable D3cold for device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) * @dev: PCI device to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) * This function can be used in drivers to disable D3cold from the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) * they handle. It also updates upstream PCI bridge PM capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) * accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) void pci_d3cold_disable(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) if (!dev->no_d3cold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) dev->no_d3cold = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) pci_bridge_d3_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) EXPORT_SYMBOL_GPL(pci_d3cold_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) * pci_pm_init - Initialize PM functions of given PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) * @dev: PCI device to handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) void pci_pm_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) int pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) u16 pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) pm_runtime_forbid(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) pm_runtime_set_active(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) pm_runtime_enable(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) device_enable_async_suspend(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) dev->wakeup_prepared = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) dev->pm_cap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) dev->pme_support = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) /* find PCI PM capability in list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) pm = pci_find_capability(dev, PCI_CAP_ID_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) if (!pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) /* Check device's ability to generate PME# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) pci_err(dev, "unsupported PM cap regs version (%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) pmc & PCI_PM_CAP_VER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) dev->pm_cap = pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) dev->bridge_d3 = pci_bridge_d3_possible(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) dev->d3cold_allowed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) dev->d1_support = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) dev->d2_support = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) if (!pci_no_d1d2(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) if (pmc & PCI_PM_CAP_D1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) dev->d1_support = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) if (pmc & PCI_PM_CAP_D2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) dev->d2_support = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) if (dev->d1_support || dev->d2_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) pci_info(dev, "supports%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) dev->d1_support ? " D1" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) dev->d2_support ? " D2" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) pmc &= PCI_PM_CAP_PME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) if (pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) pci_info(dev, "PME# supported from%s%s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) dev->pme_poll = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) * Make device's PM flags reflect the wake-up capability, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) * let the user space enable it to wake up the system as needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) device_set_wakeup_capable(&dev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) /* Disable the PME# generation functionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) pci_pme_active(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) pci_read_config_word(dev, PCI_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) if (status & PCI_STATUS_IMM_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) dev->imm_ready = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) switch (prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) case PCI_EA_P_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) case PCI_EA_P_VF_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) flags |= IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) case PCI_EA_P_MEM_PREFETCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) case PCI_EA_P_VF_MEM_PREFETCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) case PCI_EA_P_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) flags |= IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) return flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) u8 prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) return &dev->resource[bei];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) #ifdef CONFIG_PCI_IOV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) return &dev->resource[PCI_IOV_RESOURCES +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) bei - PCI_EA_BEI_VF_BAR0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) else if (bei == PCI_EA_BEI_ROM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) return &dev->resource[PCI_ROM_RESOURCE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) /* Read an Enhanced Allocation (EA) entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) static int pci_ea_read(struct pci_dev *dev, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) int ent_size, ent_offset = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) resource_size_t start, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) u32 dw0, bei, base, max_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) u8 prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) bool support_64 = (sizeof(resource_size_t) >= 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) pci_read_config_dword(dev, ent_offset, &dw0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) ent_offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) /* Entry size field indicates DWORDs after 1st */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) bei = (dw0 & PCI_EA_BEI) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) prop = (dw0 & PCI_EA_PP) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) * If the Property is in the reserved range, try the Secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) * Property instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) prop = (dw0 & PCI_EA_SP) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) if (prop > PCI_EA_P_BRIDGE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) res = pci_ea_get_resource(dev, bei, prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) flags = pci_ea_flags(dev, prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) if (!flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) pci_err(dev, "Unsupported EA properties: %#x\n", prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) /* Read Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) pci_read_config_dword(dev, ent_offset, &base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) start = (base & PCI_EA_FIELD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) ent_offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) /* Read MaxOffset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) pci_read_config_dword(dev, ent_offset, &max_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) ent_offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) /* Read Base MSBs (if 64-bit entry) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) if (base & PCI_EA_IS_64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) u32 base_upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) pci_read_config_dword(dev, ent_offset, &base_upper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) ent_offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) flags |= IORESOURCE_MEM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) /* entry starts above 32-bit boundary, can't use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) if (!support_64 && base_upper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) if (support_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) start |= ((u64)base_upper << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) end = start + (max_offset | 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) /* Read MaxOffset MSBs (if 64-bit entry) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) if (max_offset & PCI_EA_IS_64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) u32 max_offset_upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) pci_read_config_dword(dev, ent_offset, &max_offset_upper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) ent_offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) flags |= IORESOURCE_MEM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) /* entry too big, can't use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) if (!support_64 && max_offset_upper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) if (support_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) end += ((u64)max_offset_upper << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) if (end < start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) pci_err(dev, "EA Entry crosses address boundary\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) if (ent_size != ent_offset - offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) ent_size, ent_offset - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) res->name = pci_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) res->start = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) res->end = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) res->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) if (bei <= PCI_EA_BEI_BAR5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) bei, res, prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) else if (bei == PCI_EA_BEI_ROM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) res, prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) bei - PCI_EA_BEI_VF_BAR0, res, prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) bei, res, prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) return offset + ent_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) /* Enhanced Allocation Initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) void pci_ea_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) int ea;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) u8 num_ent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) /* find PCI EA capability in list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) ea = pci_find_capability(dev, PCI_CAP_ID_EA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) if (!ea)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) /* determine the number of entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) &num_ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) num_ent &= PCI_EA_NUM_ENT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) offset = ea + PCI_EA_FIRST_ENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) /* Skip DWORD 2 for type 1 functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) /* parse each EA entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) for (i = 0; i < num_ent; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) offset = pci_ea_read(dev, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) static void pci_add_saved_cap(struct pci_dev *pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) struct pci_cap_saved_state *new_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) * _pci_add_cap_save_buffer - allocate buffer for saving given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) * capability registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) * @dev: the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) * @cap: the capability to allocate the buffer for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) * @extended: Standard or Extended capability ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) * @size: requested size of the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) bool extended, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) struct pci_cap_saved_state *save_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) if (extended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) pos = pci_find_ext_capability(dev, cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) pos = pci_find_capability(dev, cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) if (!save_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) save_state->cap.cap_nr = cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) save_state->cap.cap_extended = extended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) save_state->cap.size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) pci_add_saved_cap(dev, save_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) return _pci_add_cap_save_buffer(dev, cap, false, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) return _pci_add_cap_save_buffer(dev, cap, true, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) * @dev: the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) void pci_allocate_cap_save_buffers(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) PCI_EXP_SAVE_REGS * sizeof(u16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) pci_err(dev, "unable to preallocate PCI Express save buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) pci_err(dev, "unable to preallocate PCI-X save buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) 2 * sizeof(u16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) pci_err(dev, "unable to allocate suspend buffer for LTR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) pci_allocate_vc_save_buffers(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) void pci_free_cap_save_buffers(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) struct pci_cap_saved_state *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) struct hlist_node *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) kfree(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) * pci_configure_ari - enable or disable ARI forwarding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) * @dev: the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) * If @dev and its upstream bridge both support ARI, enable ARI in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) * bridge. Otherwise, disable ARI in the bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) void pci_configure_ari(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) u32 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) bridge = dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) if (!(cap & PCI_EXP_DEVCAP2_ARI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) PCI_EXP_DEVCTL2_ARI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) bridge->ari_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) PCI_EXP_DEVCTL2_ARI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) bridge->ari_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) u16 cap, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) pos = pdev->acs_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) * Except for egress control, capabilities are either required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) * or only required if controllable. Features missing from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) * capability field can therefore be assumed as hard-wired enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) acs_flags &= (cap | PCI_ACS_EC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) return (ctrl & acs_flags) == acs_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) * pci_acs_enabled - test ACS against required flags for a given device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) * @pdev: device to test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) * @acs_flags: required PCI ACS flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) * Return true if the device supports the provided flags. Automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) * filters out flags that are not implemented on multifunction devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) * Note that this interface checks the effective ACS capabilities of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) * device rather than the actual capabilities. For instance, most single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) * function endpoints are not required to support ACS because they have no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) * opportunity for peer-to-peer access. We therefore return 'true'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) * regardless of whether the device exposes an ACS capability. This makes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) * it much easier for callers of this function to ignore the actual type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) * or topology of the device when testing ACS support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) return ret > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) * Conventional PCI and PCI-X devices never support ACS, either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) * effectively or actually. The shared bus topology implies that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) * any device on the bus can receive or snoop DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) if (!pci_is_pcie(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) switch (pci_pcie_type(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) * but since their primary interface is PCI/X, we conservatively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) * handle them as we would a non-PCIe device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) case PCI_EXP_TYPE_PCIE_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) * applicable... must never implement an ACS Extended Capability...".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) * This seems arbitrary, but we take a conservative interpretation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) * of this statement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) case PCI_EXP_TYPE_PCI_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) case PCI_EXP_TYPE_RC_EC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) * implement ACS in order to indicate their peer-to-peer capabilities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) * regardless of whether they are single- or multi-function devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) case PCI_EXP_TYPE_DOWNSTREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) case PCI_EXP_TYPE_ROOT_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) return pci_acs_flags_enabled(pdev, acs_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) * implemented by the remaining PCIe types to indicate peer-to-peer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) * capabilities, but only when they are part of a multifunction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) * device. The footnote for section 6.12 indicates the specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) * PCIe types included here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) case PCI_EXP_TYPE_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) case PCI_EXP_TYPE_UPSTREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) case PCI_EXP_TYPE_LEG_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) case PCI_EXP_TYPE_RC_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) if (!pdev->multifunction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) return pci_acs_flags_enabled(pdev, acs_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) * to single function devices with the exception of downstream ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) * @start: starting downstream device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) * @end: ending upstream device or NULL to search to the root bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) * @acs_flags: required flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) * Walk up a device tree from start to end testing PCI ACS support. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) * any step along the way does not support the required flags, return false.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) bool pci_acs_path_enabled(struct pci_dev *start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) struct pci_dev *end, u16 acs_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) struct pci_dev *pdev, *parent = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) pdev = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) if (!pci_acs_enabled(pdev, acs_flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) if (pci_is_root_bus(pdev->bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) return (end == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) parent = pdev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) } while (pdev != end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) * pci_acs_init - Initialize ACS if hardware supports it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) * @dev: the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) void pci_acs_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) * Attempt to enable ACS regardless of capability because some Root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) * the standard ACS capability but still support ACS via those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) * quirks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) pci_enable_acs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) * pci_rebar_find_pos - find position of resize ctrl reg for BAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) * @pdev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) * @bar: BAR to find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) * Helper to find the position of the ctrl register for a BAR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) * Returns -ENOTSUPP if resizable BARs are not supported at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) * Returns -ENOENT if no ctrl register for the BAR could be found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) unsigned int pos, nbars, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) PCI_REBAR_CTRL_NBAR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) for (i = 0; i < nbars; i++, pos += 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) int bar_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) if (bar_idx == bar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) * pci_rebar_get_possible_sizes - get possible sizes for BAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) * @pdev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) * @bar: BAR to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) * Get the possible sizes of a resizable BAR as bitmask defined in the spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) u32 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) pos = pci_rebar_find_pos(pdev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) if (pos < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) cap &= PCI_REBAR_CAP_SIZES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) bar == 0 && cap == 0x7000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) cap = 0x3f000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) return cap >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) * pci_rebar_get_current_size - get the current size of a BAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) * @pdev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) * @bar: BAR to set size to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) * Read the size of a BAR from the resizable BAR config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) * Returns size if found or negative error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) pos = pci_rebar_find_pos(pdev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) if (pos < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) * pci_rebar_set_size - set a new size for a BAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) * @pdev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) * @bar: BAR to set size to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) * @size: new size as defined in the spec (0=1MB, 19=512GB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) * Set the new size of a BAR as defined in the spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) * Returns zero if resizing was successful, error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) pos = pci_rebar_find_pos(pdev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) if (pos < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) * @dev: the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) * PCI_EXP_DEVCAP2_ATOMIC_COMP32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) * PCI_EXP_DEVCAP2_ATOMIC_COMP64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) * PCI_EXP_DEVCAP2_ATOMIC_COMP128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) * Return 0 if all upstream bridges support AtomicOp routing, egress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) * blocking is disabled on all upstream ports, and the root port supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) * AtomicOp completion), or negative otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) struct pci_bus *bus = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) u32 cap, ctl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) if (!pci_is_pcie(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) * AtomicOp requesters. For now, we only support endpoints as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) * requesters and root ports as completers. No endpoints as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) * completers, and no peer-to-peer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) switch (pci_pcie_type(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) case PCI_EXP_TYPE_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) case PCI_EXP_TYPE_LEG_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) case PCI_EXP_TYPE_RC_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) while (bus->parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) bridge = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) switch (pci_pcie_type(bridge)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) /* Ensure switch ports support AtomicOp routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) case PCI_EXP_TYPE_UPSTREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) case PCI_EXP_TYPE_DOWNSTREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) /* Ensure root port supports all the sizes we care about */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) case PCI_EXP_TYPE_ROOT_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) if ((cap & cap_mask) != cap_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) /* Ensure upstream ports don't block AtomicOps on egress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) &ctl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) bus = bus->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) PCI_EXP_DEVCTL2_ATOMIC_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) * @dev: the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) * Perform INTx swizzling for a device behind one level of bridge. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) * required by section 9.1 of the PCI-to-PCI bridge specification for devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) * behind bridges on add-in cards. For devices with ARI enabled, the slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) * number is always 0 (see the Implementation Note in section 2.2.8.1 of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) * the PCI Express Base Specification, Revision 2.1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) if (pci_ari_enabled(dev->bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) slot = PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) return (((pin - 1) + slot) % 4) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) u8 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) pin = dev->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) if (!pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) while (!pci_is_root_bus(dev->bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) pin = pci_swizzle_interrupt_pin(dev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) dev = dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) *bridge = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) return pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) * pci_common_swizzle - swizzle INTx all the way to root bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) * @dev: the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) * bridges all the way up to a PCI root bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) u8 pin = *pinp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) while (!pci_is_root_bus(dev->bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) pin = pci_swizzle_interrupt_pin(dev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) dev = dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) *pinp = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) return PCI_SLOT(dev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) EXPORT_SYMBOL_GPL(pci_common_swizzle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) * pci_release_region - Release a PCI bar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) * @pdev: PCI device whose resources were previously reserved by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) * pci_request_region()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) * @bar: BAR to release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) * Releases the PCI I/O and memory resources previously reserved by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) * successful call to pci_request_region(). Call this function only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) * after all use of the PCI regions has ceased.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) void pci_release_region(struct pci_dev *pdev, int bar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) struct pci_devres *dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) if (pci_resource_len(pdev, bar) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) release_region(pci_resource_start(pdev, bar),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) pci_resource_len(pdev, bar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) release_mem_region(pci_resource_start(pdev, bar),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) pci_resource_len(pdev, bar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) dr = find_pci_dr(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) if (dr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) dr->region_mask &= ~(1 << bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) EXPORT_SYMBOL(pci_release_region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) * __pci_request_region - Reserved PCI I/O and memory resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) * @pdev: PCI device whose resources are to be reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) * @bar: BAR to be reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) * @res_name: Name to be associated with resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) * @exclusive: whether the region access is exclusive or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) * Mark the PCI region associated with PCI device @pdev BAR @bar as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) * being reserved by owner @res_name. Do not access any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) * address inside the PCI regions unless this call returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) * successfully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) * If @exclusive is set, then the region is marked so that userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) * is explicitly not allowed to map the resource via /dev/mem or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) * sysfs MMIO access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) * Returns 0 on success, or %EBUSY on error. A warning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) * message is also printed on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) static int __pci_request_region(struct pci_dev *pdev, int bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) const char *res_name, int exclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) struct pci_devres *dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) if (pci_resource_len(pdev, bar) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) if (!request_region(pci_resource_start(pdev, bar),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) pci_resource_len(pdev, bar), res_name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) if (!__request_mem_region(pci_resource_start(pdev, bar),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) pci_resource_len(pdev, bar), res_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) exclusive))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) dr = find_pci_dr(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) if (dr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) dr->region_mask |= 1 << bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) &pdev->resource[bar]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) * pci_request_region - Reserve PCI I/O and memory resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) * @pdev: PCI device whose resources are to be reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) * @bar: BAR to be reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) * @res_name: Name to be associated with resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) * Mark the PCI region associated with PCI device @pdev BAR @bar as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) * being reserved by owner @res_name. Do not access any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) * address inside the PCI regions unless this call returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) * successfully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) * Returns 0 on success, or %EBUSY on error. A warning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) * message is also printed on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) return __pci_request_region(pdev, bar, res_name, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) EXPORT_SYMBOL(pci_request_region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) * pci_release_selected_regions - Release selected PCI I/O and memory resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) * @pdev: PCI device whose resources were previously reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) * @bars: Bitmask of BARs to be released
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) * Release selected PCI I/O and memory resources previously reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) * Call this function only after all use of the PCI regions has ceased.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) void pci_release_selected_regions(struct pci_dev *pdev, int bars)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) for (i = 0; i < PCI_STD_NUM_BARS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) if (bars & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) pci_release_region(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) EXPORT_SYMBOL(pci_release_selected_regions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) const char *res_name, int excl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) for (i = 0; i < PCI_STD_NUM_BARS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) if (bars & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) if (__pci_request_region(pdev, i, res_name, excl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) if (bars & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) pci_release_region(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) * @pdev: PCI device whose resources are to be reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) * @bars: Bitmask of BARs to be requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) * @res_name: Name to be associated with resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) int pci_request_selected_regions(struct pci_dev *pdev, int bars,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) const char *res_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) return __pci_request_selected_regions(pdev, bars, res_name, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) EXPORT_SYMBOL(pci_request_selected_regions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) const char *res_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) return __pci_request_selected_regions(pdev, bars, res_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) IORESOURCE_EXCLUSIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) * pci_release_regions - Release reserved PCI I/O and memory resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) * @pdev: PCI device whose resources were previously reserved by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) * pci_request_regions()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) * Releases all PCI I/O and memory resources previously reserved by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) * successful call to pci_request_regions(). Call this function only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) * after all use of the PCI regions has ceased.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) void pci_release_regions(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) EXPORT_SYMBOL(pci_release_regions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) * pci_request_regions - Reserve PCI I/O and memory resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) * @pdev: PCI device whose resources are to be reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) * @res_name: Name to be associated with resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) * Mark all PCI regions associated with PCI device @pdev as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) * being reserved by owner @res_name. Do not access any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) * address inside the PCI regions unless this call returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) * successfully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) * Returns 0 on success, or %EBUSY on error. A warning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) * message is also printed on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) int pci_request_regions(struct pci_dev *pdev, const char *res_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) return pci_request_selected_regions(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) ((1 << PCI_STD_NUM_BARS) - 1), res_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) EXPORT_SYMBOL(pci_request_regions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) * @pdev: PCI device whose resources are to be reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) * @res_name: Name to be associated with resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) * Mark all PCI regions associated with PCI device @pdev as being reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) * by owner @res_name. Do not access any address inside the PCI regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) * unless this call returns successfully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) * pci_request_regions_exclusive() will mark the region so that /dev/mem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) * and the sysfs MMIO access will not be allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) * Returns 0 on success, or %EBUSY on error. A warning message is also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) * printed on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) return pci_request_selected_regions_exclusive(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) ((1 << PCI_STD_NUM_BARS) - 1), res_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) EXPORT_SYMBOL(pci_request_regions_exclusive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) * Record the PCI IO range (expressed as CPU physical address + size).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) * Return a negative value if an error has occurred, zero otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) resource_size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) #ifdef PCI_IOBASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) struct logic_pio_hwaddr *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) if (!size || addr + size < addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) range = kzalloc(sizeof(*range), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) if (!range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) range->fwnode = fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) range->size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) range->hw_start = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) range->flags = LOGIC_PIO_CPU_MMIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) ret = logic_pio_register_range(range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) kfree(range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) /* Ignore duplicates due to deferred probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) if (ret == -EEXIST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) phys_addr_t pci_pio_to_address(unsigned long pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) #ifdef PCI_IOBASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) if (pio >= MMIO_UPPER_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) return address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) address = logic_pio_to_hwaddr(pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) return address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) EXPORT_SYMBOL_GPL(pci_pio_to_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) unsigned long __weak pci_address_to_pio(phys_addr_t address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) #ifdef PCI_IOBASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) return logic_pio_trans_cpuaddr(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) if (address > IO_SPACE_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) return (unsigned long)-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) return (unsigned long) address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) * pci_remap_iospace - Remap the memory mapped I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) * @res: Resource describing the I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) * @phys_addr: physical address of range to be mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) * Remap the memory mapped I/O space described by the @res and the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) * physical address @phys_addr into virtual address space. Only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) * architectures that have memory mapped IO functions defined (and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) * PCI_IOBASE value defined) should call this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) if (!(res->flags & IORESOURCE_IO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) if (res->end > IO_SPACE_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) pgprot_device(PAGE_KERNEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) * This architecture does not have memory mapped I/O space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) * so this function should never be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) EXPORT_SYMBOL(pci_remap_iospace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) * pci_unmap_iospace - Unmap the memory mapped I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) * @res: resource to be unmapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) * Unmap the CPU virtual address @res from virtual address space. Only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) * architectures that have memory mapped IO functions defined (and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) * PCI_IOBASE value defined) should call this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) void pci_unmap_iospace(struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) unmap_kernel_range(vaddr, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) EXPORT_SYMBOL(pci_unmap_iospace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) struct resource **res = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) pci_unmap_iospace(*res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) * devm_pci_remap_iospace - Managed pci_remap_iospace()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) * @dev: Generic device to remap IO address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) * @res: Resource describing the I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) * @phys_addr: physical address of range to be mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) * Managed pci_remap_iospace(). Map is automatically unmapped on driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) * detach.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) phys_addr_t phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) const struct resource **ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) if (!ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) error = pci_remap_iospace(res, phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) devres_free(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) *ptr = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) devres_add(dev, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) EXPORT_SYMBOL(devm_pci_remap_iospace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) * @dev: Generic device to remap IO address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) * @offset: Resource address to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) * @size: Size of map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) * detach.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) void __iomem *devm_pci_remap_cfgspace(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) resource_size_t offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) resource_size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) void __iomem **ptr, *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) if (!ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) addr = pci_remap_cfgspace(offset, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) if (addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) *ptr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) devres_add(dev, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) devres_free(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) EXPORT_SYMBOL(devm_pci_remap_cfgspace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) * @dev: generic device to handle the resource for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) * @res: configuration space resource to be handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) * Checks that a resource is a valid memory region, requests the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) * region and ioremaps with pci_remap_cfgspace() API that ensures the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) * proper PCI configuration space memory attributes are guaranteed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) * All operations are managed and will be undone on driver detach.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) * on failure. Usage example::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) * if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) * return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) void __iomem *dest_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) BUG_ON(!dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) if (!res || resource_type(res) != IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) dev_err(dev, "invalid resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) return IOMEM_ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) name = res->name ?: dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) if (!devm_request_mem_region(dev, res->start, size, name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) dev_err(dev, "can't request region for resource %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) return IOMEM_ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) if (!dest_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) dev_err(dev, "ioremap failed for resource %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) devm_release_mem_region(dev, res->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) return dest_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) static void __pci_set_master(struct pci_dev *dev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) u16 old_cmd, cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) cmd = old_cmd | PCI_COMMAND_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) cmd = old_cmd & ~PCI_COMMAND_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) if (cmd != old_cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) pci_dbg(dev, "%s bus mastering\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) enable ? "enabling" : "disabling");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) pci_write_config_word(dev, PCI_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) dev->is_busmaster = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) * pcibios_setup - process "pci=" kernel boot arguments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) * @str: string used to pass in "pci=" kernel boot arguments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) * Process kernel boot arguments. This is the default implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) * Architecture specific implementations can override this as necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) char * __weak __init pcibios_setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) return str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) * pcibios_set_master - enable PCI bus-mastering for device dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) * @dev: the PCI device to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) * Enables PCI bus-mastering for the device. This is the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) * implementation. Architecture specific implementations can override
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) * this if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) void __weak pcibios_set_master(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) u8 lat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) if (pci_is_pcie(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) if (lat < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) else if (lat > pcibios_max_latency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) lat = pcibios_max_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) * pci_set_master - enables bus-mastering for device dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) * @dev: the PCI device to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) * Enables bus-mastering on the device and calls pcibios_set_master()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) * to do the needed arch specific settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) void pci_set_master(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) __pci_set_master(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) pcibios_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) EXPORT_SYMBOL(pci_set_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) * pci_clear_master - disables bus-mastering for device dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) * @dev: the PCI device to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) void pci_clear_master(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) __pci_set_master(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) EXPORT_SYMBOL(pci_clear_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) * @dev: the PCI device for which MWI is to be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) * Helper function for pci_set_mwi.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) * Originally copied from drivers/net/acenic.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) int pci_set_cacheline_size(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) u8 cacheline_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) if (!pci_cache_line_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) equal to or multiple of the right value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) if (cacheline_size >= pci_cache_line_size &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) (cacheline_size % pci_cache_line_size) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) /* Write the correct value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) /* Read it back. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) if (cacheline_size == pci_cache_line_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) pci_info(dev, "cache line size of %d is not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) pci_cache_line_size << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) * pci_set_mwi - enables memory-write-invalidate PCI transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) * @dev: the PCI device for which MWI is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) int pci_set_mwi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) #ifdef PCI_DISABLE_MWI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) rc = pci_set_cacheline_size(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) pci_read_config_word(dev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) if (!(cmd & PCI_COMMAND_INVALIDATE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) pci_dbg(dev, "enabling Mem-Wr-Inval\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) cmd |= PCI_COMMAND_INVALIDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) pci_write_config_word(dev, PCI_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) EXPORT_SYMBOL(pci_set_mwi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) * pcim_set_mwi - a device-managed pci_set_mwi()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) * @dev: the PCI device for which MWI is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) * Managed pci_set_mwi().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) int pcim_set_mwi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) struct pci_devres *dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) dr = find_pci_dr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) if (!dr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) dr->mwi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) return pci_set_mwi(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) EXPORT_SYMBOL(pcim_set_mwi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) * @dev: the PCI device for which MWI is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) * Callers are not required to check the return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) int pci_try_set_mwi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) #ifdef PCI_DISABLE_MWI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) return pci_set_mwi(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) EXPORT_SYMBOL(pci_try_set_mwi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) * @dev: the PCI device to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) * Disables PCI Memory-Write-Invalidate transaction on the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) void pci_clear_mwi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) #ifndef PCI_DISABLE_MWI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) pci_read_config_word(dev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) if (cmd & PCI_COMMAND_INVALIDATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) cmd &= ~PCI_COMMAND_INVALIDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) pci_write_config_word(dev, PCI_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) EXPORT_SYMBOL(pci_clear_mwi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) * pci_intx - enables/disables PCI INTx for device dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) * @pdev: the PCI device to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) * @enable: boolean: whether to enable or disable PCI INTx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) * Enables/disables PCI INTx for device @pdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) void pci_intx(struct pci_dev *pdev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) u16 pci_command, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) new = pci_command | PCI_COMMAND_INTX_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) if (new != pci_command) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) struct pci_devres *dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) pci_write_config_word(pdev, PCI_COMMAND, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) dr = find_pci_dr(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) if (dr && !dr->restore_intx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) dr->restore_intx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) dr->orig_intx = !enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) EXPORT_SYMBOL_GPL(pci_intx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) struct pci_bus *bus = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) bool mask_updated = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) u32 cmd_status_dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) u16 origcmd, newcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) bool irq_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) * We do a single dword read to retrieve both command and status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) * Document assumptions that make this possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) BUILD_BUG_ON(PCI_COMMAND % 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) raw_spin_lock_irqsave(&pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) * Check interrupt status register to see whether our device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) * triggered the interrupt (when masking) or the next IRQ is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) * already pending (when unmasking).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) if (mask != irq_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) mask_updated = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) origcmd = cmd_status_dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) if (mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) newcmd |= PCI_COMMAND_INTX_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) if (newcmd != origcmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) raw_spin_unlock_irqrestore(&pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) return mask_updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) * pci_check_and_mask_intx - mask INTx on pending interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) * @dev: the PCI device to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) * Check if the device dev has its INTx line asserted, mask it and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) * true in that case. False is returned if no interrupt was pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) bool pci_check_and_mask_intx(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) return pci_check_and_set_intx_mask(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) * @dev: the PCI device to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) * Check if the device dev has its INTx line asserted, unmask it if not and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) * return true. False is returned and the mask remains active if there was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) * still an interrupt pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) bool pci_check_and_unmask_intx(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) return pci_check_and_set_intx_mask(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) * pci_wait_for_pending_transaction - wait for pending transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) * @dev: the PCI device to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) * Return 0 if transaction is pending 1 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) int pci_wait_for_pending_transaction(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) if (!pci_is_pcie(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) PCI_EXP_DEVSTA_TRPND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) EXPORT_SYMBOL(pci_wait_for_pending_transaction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) * pcie_has_flr - check if a device supports function level resets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) * @dev: device to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) * Returns true if the device advertises support for PCIe function level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) * resets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) bool pcie_has_flr(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) u32 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) return cap & PCI_EXP_DEVCAP_FLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) EXPORT_SYMBOL_GPL(pcie_has_flr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) * pcie_flr - initiate a PCIe function level reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) * @dev: device to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) * Initiate a function level reset on @dev. The caller should ensure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) * device supports FLR before calling this function, e.g. by using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) * pcie_has_flr() helper.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) int pcie_flr(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) if (!pci_wait_for_pending_transaction(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) if (dev->imm_ready)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) * 100ms, but may silently discard requests while the FLR is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) * progress. Wait 100ms before trying to access the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) EXPORT_SYMBOL_GPL(pcie_flr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) static int pci_af_flr(struct pci_dev *dev, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) u8 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) pos = pci_find_capability(dev, PCI_CAP_ID_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) if (!pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) if (probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) * Wait for Transaction Pending bit to clear. A word-aligned test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) * is used, so we use the control offset rather than status and shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) * the test bit to match.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) PCI_AF_STATUS_TP << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) if (dev->imm_ready)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) * updated 27 July 2006; a device must complete an FLR within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) * 100ms, but may silently discard requests while the FLR is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) * progress. Wait 100ms before trying to access the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) * @dev: Device to reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) * @probe: If set, only check if the device can be reset this way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) * unset, it will be reinitialized internally when going from PCI_D3hot to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) * PCI_D0. If that's the case and the device is not in a low-power state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) * NOTE: This causes the caller to sleep for twice the device power transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) * by default (i.e. unless the @dev's d3hot_delay field has a different value).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) * Moreover, only devices in D0 can be reset by this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) static int pci_pm_reset(struct pci_dev *dev, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) u16 csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) if (probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) if (dev->current_state != PCI_D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) csr &= ~PCI_PM_CTRL_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) csr |= PCI_D3hot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) pci_dev_d3_sleep(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) csr &= ~PCI_PM_CTRL_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) csr |= PCI_D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) pci_dev_d3_sleep(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) * pcie_wait_for_link_delay - Wait until link is active or inactive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) * @pdev: Bridge device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) * @active: waiting for active or inactive?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) * @delay: Delay to wait after link has become active (in ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) * Use this to wait till link becomes active or inactive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) int delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) int timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) bool ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) u16 lnk_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) * Some controllers might not implement link active reporting. In this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) * case, we wait for 1000 ms + any delay requested by the caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) if (!pdev->link_active_reporting) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) msleep(timeout + delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) * after which we should expect an link active if the reset was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) * successful. If so, software must wait a minimum 100ms before sending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) * configuration requests to devices downstream this port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) * If the link fails to activate, either the device was physically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) * removed or the link is permanently failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) if (active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) if (ret == active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) if (timeout <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) timeout -= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) if (active && ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) msleep(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) return ret == active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) * pcie_wait_for_link - Wait until link is active or inactive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) * @pdev: Bridge device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) * @active: waiting for active or inactive?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) * Use this to wait till link becomes active or inactive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) return pcie_wait_for_link_delay(pdev, active, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) * Find maximum D3cold delay required by all the devices on the bus. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) * spec says 100 ms, but firmware can lower it and we allow drivers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) * increase it as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) * Called with @pci_bus_sem locked for reading.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) const struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) int min_delay = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) int max_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) list_for_each_entry(pdev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) if (pdev->d3cold_delay < min_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) min_delay = pdev->d3cold_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) if (pdev->d3cold_delay > max_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) max_delay = pdev->d3cold_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) return max(min_delay, max_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) * @dev: PCI bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) * Handle necessary delays before access to the devices on the secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) * side of the bridge are permitted after D3cold to D0 transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) * 4.3.2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) struct pci_dev *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) int delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) if (pci_dev_is_disconnected(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) if (!pci_is_bridge(dev) || !dev->bridge_d3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) down_read(&pci_bus_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) * We only deal with devices that are present currently on the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) * For any hot-added devices the access delay is handled in pciehp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) * board_added(). In case of ACPI hotplug the firmware is expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) * to configure the devices before OS is notified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) up_read(&pci_bus_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) /* Take d3cold_delay requirements into account */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) delay = pci_bus_max_d3cold_delay(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) if (!delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) up_read(&pci_bus_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) bus_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) up_read(&pci_bus_sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) * accessing the device after reset (that is 1000 ms + 100 ms). In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) * practice this should not be needed because we don't do power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) * management for them (see pci_bridge_d3_possible()).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) if (!pci_is_pcie(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) msleep(1000 + delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) * For PCIe downstream and root ports that do not support speeds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) * greater than 5 GT/s need to wait minimum 100 ms. For higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) * speeds (gen3) we need to wait first for the data link layer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) * become active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) * However, 100 ms is the minimum and the PCIe spec says the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) * software must allow at least 1s before it can determine that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) * device that did not respond is a broken device. There is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) * evidence that 100 ms is not always enough, for example certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) * Titan Ridge xHCI controller does not always respond to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) * configuration requests if we only wait for 100 ms (see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) * Therefore we wait for 100 ms and check for the device presence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) * If it is still not present give it an additional 100 ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) if (!pcie_downstream_port(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) msleep(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) if (!pcie_wait_for_link_delay(dev, true, delay)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) /* Did not train, no need to wait any further */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) if (!pci_device_is_present(child)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) msleep(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) void pci_reset_secondary_bus(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) * this to 2ms to ensure that we meet the minimum requirement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) msleep(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) * Trhfa for conventional PCI is 2^25 clock cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) * Assuming a minimum 33MHz clock this results in a 1s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) * delay before we can consider subordinate devices to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) * be re-initialized. PCIe has some ways to shorten this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) * but we don't make use of them yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) ssleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) pci_reset_secondary_bus(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) * @dev: Bridge device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) * Use the bridge control register to assert reset on the secondary bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) * Devices on the secondary bus are left in power-on state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) pcibios_reset_secondary_bus(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) if (pci_is_root_bus(dev->bus) || dev->subordinate ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) list_for_each_entry(pdev, &dev->bus->devices, bus_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) if (pdev != dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) if (probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) return pci_bridge_secondary_bus_reset(dev->bus->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) int rc = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) if (!hotplug || !try_module_get(hotplug->owner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) if (hotplug->ops->reset_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) rc = hotplug->ops->reset_slot(hotplug, probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) module_put(hotplug->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) if (dev->multifunction || dev->subordinate || !dev->slot ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) static void pci_dev_lock(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) pci_cfg_access_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) /* block PM suspend, driver probe, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) device_lock(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) /* Return 1 on successful lock, 0 on contention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) static int pci_dev_trylock(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) if (pci_cfg_access_trylock(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) if (device_trylock(&dev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) pci_cfg_access_unlock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) static void pci_dev_unlock(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) device_unlock(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) pci_cfg_access_unlock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) static void pci_dev_save_and_disable(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) const struct pci_error_handlers *err_handler =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) dev->driver ? dev->driver->err_handler : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) * dev->driver->err_handler->reset_prepare() is protected against
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) * races with ->remove() by the device lock, which must be held by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) * the caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) if (err_handler && err_handler->reset_prepare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) err_handler->reset_prepare(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) * Wake-up device prior to save. PM registers default to D0 after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) * reset and a simple register restore doesn't reliably return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) * to a non-D0 state anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) pci_set_power_state(dev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) pci_save_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) * Disable the device by clearing the Command register, except for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) * INTx-disable which is set. This not only disables MMIO and I/O port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) * BARs, but also prevents the device from being Bus Master, preventing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) * compliant devices, INTx-disable prevents legacy interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) static void pci_dev_restore(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) const struct pci_error_handlers *err_handler =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) dev->driver ? dev->driver->err_handler : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) pci_restore_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) * dev->driver->err_handler->reset_done() is protected against
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) * races with ->remove() by the device lock, which must be held by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) * the caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) if (err_handler && err_handler->reset_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) err_handler->reset_done(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) * __pci_reset_function_locked - reset a PCI device function while holding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) * the @dev mutex lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) * @dev: PCI device to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) * Some devices allow an individual function to be reset without affecting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) * other functions in the same device. The PCI device must be responsive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) * to PCI config space in order to use this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) * The device function is presumed to be unused and the caller is holding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) * the device mutex lock when this function is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) * Resetting the device will make the contents of PCI configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) * random, so any caller of this must be prepared to reinitialise the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) * etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) * Returns 0 if the device function was successfully reset or negative if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) * device doesn't support resetting a single function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) int __pci_reset_function_locked(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) might_sleep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) * A reset method returns -ENOTTY if it doesn't support this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) * and we should try the next method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) * If it returns 0 (success), we're finished. If it returns any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) * other error, we're also finished: this indicates that further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) * reset mechanisms might be broken on the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) rc = pci_dev_specific_reset(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) if (rc != -ENOTTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) if (pcie_has_flr(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) rc = pcie_flr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) if (rc != -ENOTTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) rc = pci_af_flr(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) if (rc != -ENOTTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) rc = pci_pm_reset(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) if (rc != -ENOTTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) rc = pci_dev_reset_slot_function(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) if (rc != -ENOTTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) return pci_parent_bus_reset(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) * pci_probe_reset_function - check whether the device can be safely reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) * @dev: PCI device to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) * Some devices allow an individual function to be reset without affecting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) * other functions in the same device. The PCI device must be responsive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) * to PCI config space in order to use this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) * Returns 0 if the device function can be reset or negative if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) * device doesn't support resetting a single function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) int pci_probe_reset_function(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) might_sleep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) rc = pci_dev_specific_reset(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) if (rc != -ENOTTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) if (pcie_has_flr(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) rc = pci_af_flr(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) if (rc != -ENOTTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) rc = pci_pm_reset(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) if (rc != -ENOTTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) rc = pci_dev_reset_slot_function(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) if (rc != -ENOTTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) return pci_parent_bus_reset(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) * pci_reset_function - quiesce and reset a PCI device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) * @dev: PCI device to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) * Some devices allow an individual function to be reset without affecting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) * other functions in the same device. The PCI device must be responsive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) * to PCI config space in order to use this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) * This function does not just reset the PCI portion of a device, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) * clears all the state associated with the device. This function differs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) * from __pci_reset_function_locked() in that it saves and restores device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) * over the reset and takes the PCI device lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) * Returns 0 if the device function was successfully reset or negative if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) * device doesn't support resetting a single function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) int pci_reset_function(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) if (!dev->reset_fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) pci_dev_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) pci_dev_save_and_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) rc = __pci_reset_function_locked(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) pci_dev_restore(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) pci_dev_unlock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) EXPORT_SYMBOL_GPL(pci_reset_function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) * pci_reset_function_locked - quiesce and reset a PCI device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) * @dev: PCI device to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) * Some devices allow an individual function to be reset without affecting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) * other functions in the same device. The PCI device must be responsive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) * to PCI config space in order to use this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) * This function does not just reset the PCI portion of a device, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) * clears all the state associated with the device. This function differs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) * from __pci_reset_function_locked() in that it saves and restores device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) * over the reset. It also differs from pci_reset_function() in that it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) * requires the PCI device lock to be held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) * Returns 0 if the device function was successfully reset or negative if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) * device doesn't support resetting a single function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) int pci_reset_function_locked(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) if (!dev->reset_fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) pci_dev_save_and_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) rc = __pci_reset_function_locked(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) pci_dev_restore(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) EXPORT_SYMBOL_GPL(pci_reset_function_locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) * pci_try_reset_function - quiesce and reset a PCI device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) * @dev: PCI device to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) * Same as above, except return -EAGAIN if unable to lock device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) int pci_try_reset_function(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) if (!dev->reset_fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) if (!pci_dev_trylock(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) pci_dev_save_and_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) rc = __pci_reset_function_locked(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) pci_dev_restore(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) pci_dev_unlock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) EXPORT_SYMBOL_GPL(pci_try_reset_function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) /* Do any devices on or below this bus prevent a bus reset? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) static bool pci_bus_resetable(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) /* Lock devices from the top of the tree down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) static void pci_bus_lock(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) pci_dev_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) if (dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) pci_bus_lock(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) /* Unlock devices from the bottom of the tree up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) static void pci_bus_unlock(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) if (dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) pci_bus_unlock(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) pci_dev_unlock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) /* Return 1 on successful lock, 0 on contention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) static int pci_bus_trylock(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) if (!pci_dev_trylock(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) if (dev->subordinate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) if (!pci_bus_trylock(dev->subordinate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) pci_dev_unlock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) if (dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) pci_bus_unlock(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) pci_dev_unlock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) /* Do any devices on or below this slot prevent a bus reset? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) static bool pci_slot_resetable(struct pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) if (slot->bus->self &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) list_for_each_entry(dev, &slot->bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) if (!dev->slot || dev->slot != slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) /* Lock devices from the top of the tree down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) static void pci_slot_lock(struct pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) list_for_each_entry(dev, &slot->bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) if (!dev->slot || dev->slot != slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) pci_dev_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) if (dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) pci_bus_lock(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) /* Unlock devices from the bottom of the tree up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) static void pci_slot_unlock(struct pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) list_for_each_entry(dev, &slot->bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) if (!dev->slot || dev->slot != slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) if (dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) pci_bus_unlock(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) pci_dev_unlock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) /* Return 1 on successful lock, 0 on contention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) static int pci_slot_trylock(struct pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) list_for_each_entry(dev, &slot->bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) if (!dev->slot || dev->slot != slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) if (!pci_dev_trylock(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) if (dev->subordinate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) if (!pci_bus_trylock(dev->subordinate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) pci_dev_unlock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) list_for_each_entry_continue_reverse(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) &slot->bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) if (!dev->slot || dev->slot != slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) if (dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) pci_bus_unlock(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) pci_dev_unlock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) * Save and disable devices from the top of the tree down while holding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) * the @dev mutex lock for the entire tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) pci_dev_save_and_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) if (dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) pci_bus_save_and_disable_locked(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) * Restore devices from top of the tree down while holding @dev mutex lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) * for the entire tree. Parent bridges need to be restored before we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) * get to subordinate devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) static void pci_bus_restore_locked(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) pci_dev_restore(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) if (dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) pci_bus_restore_locked(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) * Save and disable devices from the top of the tree down while holding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) * the @dev mutex lock for the entire tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) list_for_each_entry(dev, &slot->bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) if (!dev->slot || dev->slot != slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) pci_dev_save_and_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) if (dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) pci_bus_save_and_disable_locked(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) * Restore devices from top of the tree down while holding @dev mutex lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) * for the entire tree. Parent bridges need to be restored before we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) * get to subordinate devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) static void pci_slot_restore_locked(struct pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) list_for_each_entry(dev, &slot->bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) if (!dev->slot || dev->slot != slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) pci_dev_restore(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) if (dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) pci_bus_restore_locked(dev->subordinate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) static int pci_slot_reset(struct pci_slot *slot, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) if (!slot || !pci_slot_resetable(slot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) if (!probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) pci_slot_lock(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) might_sleep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) rc = pci_reset_hotplug_slot(slot->hotplug, probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) if (!probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) pci_slot_unlock(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) * pci_probe_reset_slot - probe whether a PCI slot can be reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) * @slot: PCI slot to probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) * Return 0 if slot can be reset, negative if a slot reset is not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) int pci_probe_reset_slot(struct pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) return pci_slot_reset(slot, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) * __pci_reset_slot - Try to reset a PCI slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) * @slot: PCI slot to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) * A PCI bus may host multiple slots, each slot may support a reset mechanism
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) * independent of other slots. For instance, some slots may support slot power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) * control. In the case of a 1:1 bus to slot architecture, this function may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) * wrap the bus reset to avoid spurious slot related events such as hotplug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) * Generally a slot reset should be attempted before a bus reset. All of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) * function of the slot and any subordinate buses behind the slot are reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) * through this function. PCI config space of all devices in the slot and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) * behind the slot is saved before and restored after reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) * Same as above except return -EAGAIN if the slot cannot be locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) static int __pci_reset_slot(struct pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) rc = pci_slot_reset(slot, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) if (pci_slot_trylock(slot)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) pci_slot_save_and_disable_locked(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) might_sleep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) rc = pci_reset_hotplug_slot(slot->hotplug, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) pci_slot_restore_locked(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) pci_slot_unlock(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) rc = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) static int pci_bus_reset(struct pci_bus *bus, int probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) if (!bus->self || !pci_bus_resetable(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) if (probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) pci_bus_lock(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) might_sleep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) ret = pci_bridge_secondary_bus_reset(bus->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) pci_bus_unlock(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) * pci_bus_error_reset - reset the bridge's subordinate bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) * @bridge: The parent device that connects to the bus to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) * This function will first try to reset the slots on this bus if the method is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) * available. If slot reset fails or is not available, this will fall back to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) * secondary bus reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) int pci_bus_error_reset(struct pci_dev *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) struct pci_bus *bus = bridge->subordinate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) struct pci_slot *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) mutex_lock(&pci_slot_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) if (list_empty(&bus->slots))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) goto bus_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) list_for_each_entry(slot, &bus->slots, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) if (pci_probe_reset_slot(slot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) goto bus_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) list_for_each_entry(slot, &bus->slots, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) if (pci_slot_reset(slot, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) goto bus_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) mutex_unlock(&pci_slot_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) bus_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) mutex_unlock(&pci_slot_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) return pci_bus_reset(bridge->subordinate, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) * pci_probe_reset_bus - probe whether a PCI bus can be reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) * @bus: PCI bus to probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) * Return 0 if bus can be reset, negative if a bus reset is not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) int pci_probe_reset_bus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) return pci_bus_reset(bus, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) * __pci_reset_bus - Try to reset a PCI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579) * @bus: top level PCI bus to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) * Same as above except return -EAGAIN if the bus cannot be locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) static int __pci_reset_bus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) rc = pci_bus_reset(bus, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) if (pci_bus_trylock(bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) pci_bus_save_and_disable_locked(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) might_sleep();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) rc = pci_bridge_secondary_bus_reset(bus->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) pci_bus_restore_locked(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) pci_bus_unlock(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) rc = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) * pci_reset_bus - Try to reset a PCI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) * @pdev: top level PCI device to reset via slot/bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) * Same as above except return -EAGAIN if the bus cannot be locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) int pci_reset_bus(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) return (!pci_probe_reset_slot(pdev->slot)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) EXPORT_SYMBOL_GPL(pci_reset_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) * Returns mmrbc: maximum designed memory read count in bytes or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) * appropriate error value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) int pcix_get_max_mmrbc(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) int cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) if (!cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) EXPORT_SYMBOL(pcix_get_max_mmrbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) * pcix_get_mmrbc - get PCI-X maximum memory read byte count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) * Returns mmrbc: maximum memory read count in bytes or appropriate error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) * value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) int pcix_get_mmrbc(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) int cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) if (!cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) EXPORT_SYMBOL(pcix_get_mmrbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) * pcix_set_mmrbc - set PCI-X maximum memory read byte count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) * @mmrbc: maximum memory read count in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) * valid values are 512, 1024, 2048, 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) * If possible sets maximum memory read byte count, some bridges have errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) * that prevent this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) int cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) u32 stat, v, o;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) v = ffs(mmrbc) - 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) if (!cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) if (o != v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) cmd &= ~PCI_X_CMD_MAX_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) cmd |= v << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) EXPORT_SYMBOL(pcix_set_mmrbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) * pcie_get_readrq - get PCI Express read request size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) * Returns maximum memory read request in bytes or appropriate error value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) int pcie_get_readrq(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) u16 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) EXPORT_SYMBOL(pcie_get_readrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) * pcie_set_readrq - set PCI Express maximum memory read request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) * @rq: maximum memory read count in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) * valid values are 128, 256, 512, 1024, 2048, 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) * If possible sets maximum memory read request in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) int pcie_set_readrq(struct pci_dev *dev, int rq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) u16 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) * If using the "performance" PCIe config, we clamp the read rq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) * size to the max packet size to keep the host bridge from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) * generating requests larger than we can cope with.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) int mps = pcie_get_mps(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) if (mps < rq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) rq = mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) v = (ffs(rq) - 8) << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) PCI_EXP_DEVCTL_READRQ, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) return pcibios_err_to_errno(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) EXPORT_SYMBOL(pcie_set_readrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) * pcie_get_mps - get PCI Express maximum payload size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) * Returns maximum payload size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) int pcie_get_mps(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) u16 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) EXPORT_SYMBOL(pcie_get_mps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) * pcie_set_mps - set PCI Express maximum payload size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) * @mps: maximum payload size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) * valid values are 128, 256, 512, 1024, 2048, 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) * If possible sets maximum payload size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) int pcie_set_mps(struct pci_dev *dev, int mps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) u16 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) v = ffs(mps) - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) if (v > dev->pcie_mpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) v <<= 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) PCI_EXP_DEVCTL_PAYLOAD, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) return pcibios_err_to_errno(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) EXPORT_SYMBOL(pcie_set_mps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) * pcie_bandwidth_available - determine minimum link settings of a PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) * device and its bandwidth limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) * @limiting_dev: storage for device causing the bandwidth limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) * @speed: storage for speed of limiting device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) * @width: storage for width of limiting device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) * Walk up the PCI device chain and find the point where the minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) * bandwidth is available. Return the bandwidth available there and (if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) * limiting_dev, speed, and width pointers are supplied) information about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) * raw bandwidth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) enum pci_bus_speed *speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) enum pcie_link_width *width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) u16 lnksta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) enum pci_bus_speed next_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) enum pcie_link_width next_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) u32 bw, next_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) if (speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) *speed = PCI_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831) if (width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) *width = PCIE_LNK_WIDTH_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) bw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) while (dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) PCI_EXP_LNKSTA_NLW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) /* Check if current device limits the total bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) if (!bw || next_bw <= bw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) bw = next_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) if (limiting_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) *limiting_dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) if (speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) *speed = next_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) if (width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) *width = next_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) dev = pci_upstream_bridge(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) return bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) EXPORT_SYMBOL(pcie_bandwidth_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) * pcie_get_speed_cap - query for the PCI device's link speed capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) * Query the PCI device speed capability. Return the maximum link speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) * supported by the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) u32 lnkcap2, lnkcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) * implementation note there recommends using the Supported Link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) * Speeds Vector in Link Capabilities 2 when supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) * should use the Supported Link Speeds field in Link Capabilities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) /* PCIe r3.0-compliant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) if (lnkcap2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) return PCIE_SPEED_5_0GT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) return PCIE_SPEED_2_5GT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) return PCI_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) EXPORT_SYMBOL(pcie_get_speed_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) * pcie_get_width_cap - query for the PCI device's link width capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) * Query the PCI device width capability. Return the maximum link width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) * supported by the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) u32 lnkcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) if (lnkcap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) return PCIE_LNK_WIDTH_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917) EXPORT_SYMBOL(pcie_get_width_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922) * @speed: storage for link speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923) * @width: storage for link width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) * Calculate a PCI device's link bandwidth by querying for its link speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926) * and width, multiplying them, and applying encoding overhead. The result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) * is in Mb/s, i.e., megabits/second of raw bandwidth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929) u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) enum pcie_link_width *width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) *speed = pcie_get_speed_cap(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933) *width = pcie_get_width_cap(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935) if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) return *width * PCIE_SPEED2MBS_ENC(*speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) * __pcie_print_link_status - Report the PCI device's link speed and width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) * @verbose: Print info even when enough bandwidth is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946) * If the available bandwidth at the device is less than the device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) * capable of, report the device's maximum possible bandwidth and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) * upstream link that limits its performance. If @verbose, always print
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) * the available bandwidth, even if the device isn't constrained.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953) enum pcie_link_width width, width_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) enum pci_bus_speed speed, speed_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) struct pci_dev *limiting_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956) u32 bw_avail, bw_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958) bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) if (bw_avail >= bw_cap && verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) bw_cap / 1000, bw_cap % 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964) pci_speed_string(speed_cap), width_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965) else if (bw_avail < bw_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967) bw_avail / 1000, bw_avail % 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968) pci_speed_string(speed), width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) limiting_dev ? pci_name(limiting_dev) : "<unknown>",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) bw_cap / 1000, bw_cap % 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) pci_speed_string(speed_cap), width_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) * pcie_print_link_status - Report the PCI device's link speed and width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) * @dev: PCI device to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) * Report the available bandwidth at the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) void pcie_print_link_status(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982) __pcie_print_link_status(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) EXPORT_SYMBOL(pcie_print_link_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) * pci_select_bars - Make BAR mask from the type of resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) * @dev: the PCI device for which BAR mask is made
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) * @flags: resource type mask to be selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991) * This helper routine makes bar mask from the type of resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) int pci_select_bars(struct pci_dev *dev, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995) int i, bars = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) for (i = 0; i < PCI_NUM_RESOURCES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) if (pci_resource_flags(dev, i) & flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) bars |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) return bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001) EXPORT_SYMBOL(pci_select_bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) /* Some architectures require additional programming to enable VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) static arch_set_vga_state_t arch_set_vga_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006) void __init pci_register_set_vga_state(arch_set_vga_state_t func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) arch_set_vga_state = func; /* NULL disables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012) unsigned int command_bits, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) if (arch_set_vga_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015) return arch_set_vga_state(dev, decode, command_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) * pci_set_vga_state - set VGA decode state on device and parents if requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022) * @dev: the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) * @decode: true = enable decoding, false = disable decoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025) * @flags: traverse ancestors and change bridges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) int pci_set_vga_state(struct pci_dev *dev, bool decode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029) unsigned int command_bits, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032) struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036) WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038) /* ARCH specific VGA enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039) rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) pci_read_config_word(dev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) if (decode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) cmd |= command_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048) cmd &= ~command_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) pci_write_config_word(dev, PCI_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) bus = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056) while (bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) bridge = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058) if (bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059) pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060) &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) if (decode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062) cmd |= PCI_BRIDGE_CTL_VGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) cmd &= ~PCI_BRIDGE_CTL_VGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066) cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) bus = bus->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) bool pci_pr3_present(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076) struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) if (acpi_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) adev = ACPI_COMPANION(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082) if (!adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) return adev->power.flags.power_resources &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) acpi_has_method(adev->handle, "_PR3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) EXPORT_SYMBOL_GPL(pci_pr3_present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) * pci_add_dma_alias - Add a DMA devfn alias for a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093) * @dev: the PCI device for which alias is added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094) * @devfn_from: alias slot and function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) * @nr_devfns: number of subsequent devfns to alias
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097) * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) * which is used to program permissible bus-devfn source addresses for DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099) * requests in an IOMMU. These aliases factor into IOMMU group creation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) * and are useful for devices generating DMA requests beyond or different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) * from their logical bus-devfn. Examples include device quirks where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) * device simply uses the wrong devfn, as well as non-transparent bridges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) * where the alias may be a proxy for devices in another domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) * IOMMU group creation is performed during device discovery or addition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) * prior to any potential DMA mapping and therefore prior to driver probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) * (especially for userspace assigned devices where IOMMU group definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) * cannot be left as a userspace activity). DMA aliases should therefore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) * be configured via quirks, such as the PCI fixup header quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111) void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) int devfn_to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) devfn_to = devfn_from + nr_devfns - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118) if (!dev->dma_alias_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120) if (!dev->dma_alias_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121) pci_warn(dev, "Unable to allocate DMA alias mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125) bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127) if (nr_devfns == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128) pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129) PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130) else if (nr_devfns > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131) pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132) PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138) return (dev1->dma_alias_mask &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139) test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) (dev2->dma_alias_mask &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142) pci_real_dma_dev(dev1) == dev2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143) pci_real_dma_dev(dev2) == dev1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) bool pci_device_is_present(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) if (pci_dev_is_disconnected(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152) return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) EXPORT_SYMBOL_GPL(pci_device_is_present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) void pci_ignore_hotplug(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) struct pci_dev *bridge = dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160) dev->ignore_hotplug = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) /* Propagate the "ignore hotplug" setting to the parent bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162) if (bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) bridge->ignore_hotplug = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165) EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168) * pci_real_dma_dev - Get PCI DMA device for PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) * @dev: the PCI device that may have a PCI DMA alias
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171) * Permits the platform to provide architecture-specific functionality to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172) * devices needing to alias DMA to another PCI device on another PCI bus. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173) * the PCI device is on the same bus, it is recommended to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) * pci_add_dma_alias(). This is the default implementation. Architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) * implementations can override this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177) struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) resource_size_t __weak pcibios_default_alignment(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) * Arches that don't want to expose struct resource to userland as-is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189) * sysfs and /proc can implement their own pci_resource_to_user().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) const struct resource *rsrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193) resource_size_t *start, resource_size_t *end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195) *start = rsrc->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196) *end = rsrc->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199) static char *resource_alignment_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200) static DEFINE_SPINLOCK(resource_alignment_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) * pci_specified_resource_alignment - get resource alignment specified by user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) * @dev: the PCI device to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205) * @resize: whether or not to change resources' size when reassigning alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207) * RETURNS: Resource alignment if it is specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) * Zero if it is not specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210) static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) bool *resize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213) int align_order, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214) resource_size_t align = pcibios_default_alignment();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) const char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) spin_lock(&resource_alignment_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219) p = resource_alignment_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220) if (!p || !*p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) if (pci_has_flag(PCI_PROBE_ONLY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) align = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224) pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228) while (*p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) p[count] == '@') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232) p += count + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233) if (align_order > 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234) pr_err("PCI: Invalid requested alignment (order %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235) align_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) align_order = PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) align_order = PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242) ret = pci_dev_str_match(dev, p, &p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243) if (ret == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244) *resize = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245) align = 1ULL << align_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) } else if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248) pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249) p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253) if (*p != ';' && *p != ',') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254) /* End of param or invalid format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257) p++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) spin_unlock(&resource_alignment_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261) return align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264) static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) resource_size_t align, bool resize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267) struct resource *r = &dev->resource[bar];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270) if (!(r->flags & IORESOURCE_MEM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) if (r->flags & IORESOURCE_PCI_FIXED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274) pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275) bar, r, (unsigned long long)align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279) size = resource_size(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280) if (size >= align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284) * Increase the alignment of the resource. There are two ways we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285) * can do this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287) * 1) Increase the size of the resource. BARs are aligned on their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288) * size, so when we reallocate space for this resource, we'll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) * allocate it with the larger alignment. This also prevents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) * assignment of any other BARs inside the alignment region, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291) * if we're requesting page alignment, this means no other BARs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292) * will share the page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294) * The disadvantage is that this makes the resource larger than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) * the hardware BAR, which may break drivers that compute things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296) * based on the resource size, e.g., to find registers at a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) * fixed offset before the end of the BAR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) * set r->start to the desired alignment. By itself this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301) * doesn't prevent other BARs being put inside the alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302) * region, but if we realign *every* resource of every device in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) * the system, none of them will share an alignment region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305) * When the user has requested alignment for only some devices via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) * the "pci=resource_alignment" argument, "resize" is true and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307) * use the first method. Otherwise we assume we're aligning all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308) * devices and we use the second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312) bar, r, (unsigned long long)align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) if (resize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) r->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) r->end = align - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318) r->flags &= ~IORESOURCE_SIZEALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) r->flags |= IORESOURCE_STARTALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) r->start = align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321) r->end = r->start + size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) r->flags |= IORESOURCE_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) * This function disables memory decoding and releases memory resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328) * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329) * It also rounds up size to specified alignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) * Later on, the kernel will assign page-aligned memory resource back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331) * to the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) void pci_reassigndev_resource_alignment(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337) resource_size_t align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) u16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) bool resize = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) * 3.4.1.11. Their resources are allocated from the space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344) * described by the VF BARx register in the PF's SR-IOV capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) * We can't influence their alignment here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) if (dev->is_virtfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) /* check if specified PCI is target device to reassign */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) align = pci_specified_resource_alignment(dev, &resize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) if (!align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356) (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) pci_warn(dev, "Can't reassign resources to host bridge\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) pci_read_config_word(dev, PCI_COMMAND, &command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) command &= ~PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363) pci_write_config_word(dev, PCI_COMMAND, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365) for (i = 0; i <= PCI_ROM_RESOURCE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366) pci_request_resource_alignment(dev, i, align, resize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369) * Need to disable bridge's resource window,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370) * to enable the kernel to reassign new resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371) * window later on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373) if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375) r = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) if (!(r->flags & IORESOURCE_MEM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) r->flags |= IORESOURCE_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) r->end = resource_size(r) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) r->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) pci_disable_bridge_window(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) size_t count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390) spin_lock(&resource_alignment_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391) if (resource_alignment_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392) count = scnprintf(buf, PAGE_SIZE, "%s", resource_alignment_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393) spin_unlock(&resource_alignment_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396) * When set by the command line, resource_alignment_param will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) * have a trailing line feed, which is ugly. So conditionally add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) * it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400) if (count >= 2 && buf[count - 2] != '\n' && count < PAGE_SIZE - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) buf[count - 1] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) buf[count++] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) static ssize_t resource_alignment_store(struct bus_type *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411) char *param = kstrndup(buf, count, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) if (!param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416) spin_lock(&resource_alignment_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) kfree(resource_alignment_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418) resource_alignment_param = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419) spin_unlock(&resource_alignment_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) static BUS_ATTR_RW(resource_alignment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425) static int __init pci_resource_alignment_sysfs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427) return bus_create_file(&pci_bus_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) &bus_attr_resource_alignment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430) late_initcall(pci_resource_alignment_sysfs_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) static void pci_no_domains(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) #ifdef CONFIG_PCI_DOMAINS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435) pci_domains_supported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439) #ifdef CONFIG_PCI_DOMAINS_GENERIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440) static atomic_t __domain_nr = ATOMIC_INIT(-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442) static int pci_get_new_domain_nr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) return atomic_inc_return(&__domain_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447) static int of_pci_bus_find_domain_nr(struct device *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449) static int use_dt_domains = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) int domain = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) if (parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453) domain = of_get_pci_domain_nr(parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456) * Check DT domain and use_dt_domains values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458) * If DT domain property is valid (domain >= 0) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) * use_dt_domains != 0, the DT assignment is valid since this means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460) * we have not previously allocated a domain number by using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461) * pci_get_new_domain_nr(); we should also update use_dt_domains to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462) * 1, to indicate that we have just assigned a domain number from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) * DT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465) * If DT domain property value is not valid (ie domain < 0), and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) * have not previously assigned a domain number from DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467) * (use_dt_domains != 1) we should assign a domain number by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) * using the:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) * pci_get_new_domain_nr()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472) * API and update the use_dt_domains value to keep track of method we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473) * are using to assign domain numbers (use_dt_domains = 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) * All other combinations imply we have a platform that is trying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476) * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) * which is a recipe for domain mishandling and it is prevented by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) * invalidating the domain value (domain = -1) and printing a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479) * corresponding error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481) if (domain >= 0 && use_dt_domains) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482) use_dt_domains = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) } else if (domain < 0 && use_dt_domains != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) use_dt_domains = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) domain = pci_get_new_domain_nr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) if (parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) pr_err("Node %pOF has ", parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) domain = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) return domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496) int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499) acpi_pci_bus_find_domain_nr(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) * pci_ext_cfg_avail - can we access extended PCI config space?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506) * Returns 1 if we can access PCI extended config space (offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507) * greater than 0xff). This is the default implementation. Architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) * implementations can override this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) int __weak pci_ext_cfg_avail(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515) void __weak pci_fixup_cardbus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) EXPORT_SYMBOL(pci_fixup_cardbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) static int __init pci_setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) while (str) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) char *k = strchr(str, ',');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) if (k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525) *k++ = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) if (*str && (str = pcibios_setup(str)) && *str) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) if (!strcmp(str, "nomsi")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) pci_no_msi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) } else if (!strncmp(str, "noats", 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530) pr_info("PCIe: ATS is disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) pcie_ats_disabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532) } else if (!strcmp(str, "noaer")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) pci_no_aer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534) } else if (!strcmp(str, "earlydump")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) pci_early_dump = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536) } else if (!strncmp(str, "realloc=", 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) pci_realloc_get_opt(str + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538) } else if (!strncmp(str, "realloc", 7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539) pci_realloc_get_opt("on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540) } else if (!strcmp(str, "nodomains")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) pci_no_domains();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542) } else if (!strncmp(str, "noari", 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543) pcie_ari_disabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) } else if (!strncmp(str, "cbiosize=", 9)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545) pci_cardbus_io_size = memparse(str + 9, &str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546) } else if (!strncmp(str, "cbmemsize=", 10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) pci_cardbus_mem_size = memparse(str + 10, &str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548) } else if (!strncmp(str, "resource_alignment=", 19)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549) resource_alignment_param = str + 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550) } else if (!strncmp(str, "ecrc=", 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) pcie_ecrc_get_policy(str + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552) } else if (!strncmp(str, "hpiosize=", 9)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) pci_hotplug_io_size = memparse(str + 9, &str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554) } else if (!strncmp(str, "hpmmiosize=", 11)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) pci_hotplug_mmio_size = memparse(str + 11, &str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556) } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557) pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) } else if (!strncmp(str, "hpmemsize=", 10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) pci_hotplug_mmio_size = memparse(str + 10, &str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) } else if (!strncmp(str, "hpbussize=", 10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562) pci_hotplug_bus_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) simple_strtoul(str + 10, &str, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564) if (pci_hotplug_bus_size > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567) pcie_bus_config = PCIE_BUS_TUNE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) } else if (!strncmp(str, "pcie_bus_safe", 13)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) pcie_bus_config = PCIE_BUS_SAFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) } else if (!strncmp(str, "pcie_bus_perf", 13)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571) pcie_bus_config = PCIE_BUS_PERFORMANCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573) pcie_bus_config = PCIE_BUS_PEER2PEER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) } else if (!strncmp(str, "pcie_scan_all", 13)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) } else if (!strncmp(str, "disable_acs_redir=", 18)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577) disable_acs_redir_param = str + 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) pr_err("PCI: Unknown option `%s'\n", str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582) str = k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) early_param("pci", pci_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590) * in pci_setup(), above, to point to data in the __initdata section which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591) * will be freed after the init sequence is complete. We can't allocate memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592) * in pci_setup() because some architectures do not have any memory allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) * service available during an early_param() call. So we allocate memory and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594) * copy the variable here before the init section is freed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) static int __init pci_realloc_setup_params(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) resource_alignment_param = kstrdup(resource_alignment_param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601) disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605) pure_initcall(pci_realloc_setup_params);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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