^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __PCI_BRIDGE_EMUL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __PCI_BRIDGE_EMUL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* PCI configuration space of a PCI-to-PCI bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) struct pci_bridge_emul_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) __le16 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) __le16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) __le16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) __le16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) __le32 class_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) u8 cache_line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u8 latency_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u8 header_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u8 bist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) __le32 bar[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u8 primary_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 secondary_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u8 subordinate_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u8 secondary_latency_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u8 iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u8 iolimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) __le16 secondary_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) __le16 membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) __le16 memlimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) __le16 pref_mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __le16 pref_mem_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __le32 prefbaseupper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) __le32 preflimitupper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __le16 iobaseupper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) __le16 iolimitupper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 capabilities_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 reserve[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __le32 romaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 intline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 intpin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) __le16 bridgectrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* PCI configuration space of the PCIe capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct pci_bridge_emul_pcie_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 cap_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __le16 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __le32 devcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __le16 devctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __le16 devsta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __le32 lnkcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __le16 lnkctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) __le16 lnksta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) __le32 slotcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __le16 slotctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __le16 slotsta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __le16 rootctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __le16 rootcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __le32 rootsta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __le32 devcap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __le16 devctl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __le16 devsta2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __le32 lnkcap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __le16 lnkctl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __le16 lnksta2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __le32 slotcap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __le16 slotctl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __le16 slotsta2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct pci_bridge_emul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) typedef enum { PCI_BRIDGE_EMUL_HANDLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PCI_BRIDGE_EMUL_NOT_HANDLED } pci_bridge_emul_read_status_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct pci_bridge_emul_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Called when reading from the regular PCI bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * configuration space. Return PCI_BRIDGE_EMUL_HANDLED when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * operation has handled the read operation and filled in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * *value, or PCI_BRIDGE_EMUL_NOT_HANDLED when the read should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * be emulated by the common code by reading from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * in-memory copy of the configuration space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pci_bridge_emul_read_status_t (*read_base)(struct pci_bridge_emul *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int reg, u32 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Same as ->read_base(), except it is for reading from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * PCIe capability configuration space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int reg, u32 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Called when writing to the regular PCI bridge configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * space. old is the current value, new is the new value being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * written, and mask indicates which parts of the value are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * being changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void (*write_base)(struct pci_bridge_emul *bridge, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 old, u32 new, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Same as ->write_base(), except it is for writing from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * PCIe capability configuration space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 old, u32 new, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct pci_bridge_reg_behavior;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct pci_bridge_emul {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct pci_bridge_emul_conf conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct pci_bridge_emul_pcie_conf pcie_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct pci_bridge_emul_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct pci_bridge_reg_behavior *pci_regs_behavior;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct pci_bridge_reg_behavior *pcie_cap_regs_behavior;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) bool has_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int size, u32 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int size, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif /* __PCI_BRIDGE_EMUL_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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