^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file helps PCI controller drivers implement a fake root port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * PCI bridge when the HW doesn't provide such a root port PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * It emulates a PCI bridge by providing a fake PCI configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * space (and optionally a PCIe capability configuration space) in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * memory. By default the read/write operations simply read and update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * this fake configuration space in memory. However, PCI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * drivers can provide through the 'struct pci_sw_bridge_ops'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * structure a set of operations to override or complement this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * default behavior.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "pci-bridge-emul.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCI_CAP_PCIE_SIZEOF (PCI_EXP_SLTSTA2 + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCI_CAP_PCIE_START PCI_BRIDGE_CONF_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * struct pci_bridge_reg_behavior - register bits behaviors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @ro: Read-Only bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @rw: Read-Write bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @w1c: Write-1-to-Clear bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Reads and Writes will be filtered by specified behavior. All other bits not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * declared are assumed 'Reserved' and will return 0 on reads, per PCIe 5.0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * "Reserved register fields must be read only and must return 0 (all 0's for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * multi-bit fields) when read".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct pci_bridge_reg_behavior {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Read-only bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 ro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Read-write bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 rw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Write-1-to-clear bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 w1c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) [PCI_VENDOR_ID / 4] = { .ro = ~0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) [PCI_COMMAND / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PCI_COMMAND_SERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PCI_COMMAND_FAST_BACK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .w1c = PCI_STATUS_ERROR_BITS << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [PCI_CLASS_REVISION / 4] = { .ro = ~0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Cache Line Size register: implement as read-only, we do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * pretend implementing "Memory Write and Invalidate"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * transactions"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Latency Timer Register: implemented as read-only, as "A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * bridge that is not capable of a burst transfer of more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * two data phases on its primary interface is permitted to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * hardwire the Latency Timer to a value of 16 or less"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Header Type: always read-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * BIST register: implemented as read-only, as "A bridge that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * does not support BIST must implement this register as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * read-only register that returns 0 when read"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Base Address registers not used must be implemented as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * read-only registers that return 0 when read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [PCI_PRIMARY_BUS / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Primary, secondary and subordinate bus are RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .rw = GENMASK(24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Secondary latency is read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .ro = GENMASK(31, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [PCI_IO_BASE / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* The high four bits of I/O base/limit are RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .rw = (GENMASK(15, 12) | GENMASK(7, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* The low four bits of I/O base/limit are RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PCI_STATUS_DEVSEL_MASK) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) GENMASK(11, 8) | GENMASK(3, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .w1c = PCI_STATUS_ERROR_BITS << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [PCI_MEMORY_BASE / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* The high 12-bits of mem base/limit are RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .rw = GENMASK(31, 20) | GENMASK(15, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* The low four bits of mem base/limit are RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .ro = GENMASK(19, 16) | GENMASK(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [PCI_PREF_MEMORY_BASE / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* The high 12-bits of pref mem base/limit are RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .rw = GENMASK(31, 20) | GENMASK(15, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* The low four bits of pref mem base/limit are RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .ro = GENMASK(19, 16) | GENMASK(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [PCI_PREF_BASE_UPPER32 / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .rw = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [PCI_PREF_LIMIT_UPPER32 / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .rw = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [PCI_IO_BASE_UPPER16 / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .rw = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [PCI_CAPABILITY_LIST / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .ro = GENMASK(7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * If expansion ROM is unsupported then ROM Base Address register must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * be implemented as read-only register that return 0 when read, same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * as for unused Base Address registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [PCI_ROM_ADDRESS1 / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .ro = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * are RO, and bridge control (31:16) are a mix of RW, RO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * reserved and W1C bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [PCI_INTERRUPT_LINE / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Interrupt line is RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .rw = (GENMASK(7, 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ((PCI_BRIDGE_CTL_PARITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PCI_BRIDGE_CTL_SERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PCI_BRIDGE_CTL_ISA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PCI_BRIDGE_CTL_VGA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PCI_BRIDGE_CTL_MASTER_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PCI_BRIDGE_CTL_BUS_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) BIT(8) | BIT(9) | BIT(11)) << 16)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Interrupt pin is RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .w1c = BIT(10) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [PCI_CAP_LIST_ID / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Capability ID, Next Capability Pointer and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * bits [14:0] of Capabilities register are all read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Bit 15 of Capabilities register is reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .ro = GENMASK(30, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [PCI_EXP_DEVCAP / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Bits [31:29] and [17:16] are reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Bits [27:18] are reserved for non-upstream ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Bits 28 and [14:6] are reserved for non-endpoint devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Other bits are read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .ro = BIT(15) | GENMASK(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [PCI_EXP_DEVCTL / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Device control register is RW, except bit 15 which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * reserved for non-endpoints or non-PCIe-to-PCI/X bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .rw = GENMASK(14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Device status register has bits 6 and [3:0] W1C, [5:4] RO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * the rest is reserved. Also bit 6 is reserved for non-upstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .w1c = GENMASK(3, 0) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .ro = GENMASK(5, 4) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [PCI_EXP_LNKCAP / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * All bits are RO, except bit 23 which is reserved and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * bit 18 which is reserved for non-upstream ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .ro = lower_32_bits(~(BIT(23) | PCI_EXP_LNKCAP_CLKPM)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [PCI_EXP_LNKCTL / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * Link control has bits [15:14], [11:3] and [1:0] RW, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * rest is reserved. Bit 8 is reserved for non-upstream ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Link status has bits [13:0] RO, and bits [15:14]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * W1C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .ro = GENMASK(13, 0) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .w1c = GENMASK(15, 14) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [PCI_EXP_SLTCAP / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .ro = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [PCI_EXP_SLTCTL / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Slot control has bits [14:0] RW, the rest is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * rest is reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .rw = GENMASK(14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PCI_EXP_SLTSTA_EIS) << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [PCI_EXP_RTCTL / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Root control has bits [4:0] RW, the rest is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Root capabilities has bit 0 RO, the rest is reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PCI_EXP_RTCTL_CRSSVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .ro = PCI_EXP_RTCAP_CRSVIS << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [PCI_EXP_RTSTA / 4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * Root status has bits 17 and [15:0] RO, bit 16 W1C, the rest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * is reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .w1c = PCI_EXP_RTSTA_PME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * Initialize a pci_bridge_emul structure to represent a fake PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * bridge configuration space. The caller needs to have initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * the PCI configuration space with whatever values make sense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * (typically at least vendor, device, revision), the ->ops pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * and optionally ->data and ->has_pcie.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) bridge->conf.cache_line_size = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) sizeof(pci_regs_behavior),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!bridge->pci_regs_behavior)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (bridge->has_pcie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bridge->pcie_cap_regs_behavior =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) kmemdup(pcie_cap_regs_behavior,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) sizeof(pcie_cap_regs_behavior),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!bridge->pcie_cap_regs_behavior) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) kfree(bridge->pci_regs_behavior);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* These bits are applicable only for PCI and reserved on PCIe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ~GENMASK(15, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ~((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PCI_COMMAND_FAST_BACK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) (PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PCI_STATUS_DEVSEL_MASK) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ~GENMASK(31, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ~((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PCI_STATUS_DEVSEL_MASK) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ~((PCI_BRIDGE_CTL_MASTER_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) BIT(8) | BIT(9) | BIT(11)) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ~((PCI_BRIDGE_CTL_FAST_BACK) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ~(BIT(10) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) EXPORT_SYMBOL_GPL(pci_bridge_emul_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * Cleanup a pci_bridge_emul structure that was previously initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * using pci_bridge_emul_init().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (bridge->has_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) kfree(bridge->pcie_cap_regs_behavior);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) kfree(bridge->pci_regs_behavior);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) EXPORT_SYMBOL_GPL(pci_bridge_emul_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Should be called by the PCI controller driver when reading the PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * configuration space of the fake bridge. It will call back the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * ->ops->read_base or ->ops->read_pcie operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int reg = where & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int reg, u32 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) __le32 *cfgspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) const struct pci_bridge_reg_behavior *behavior;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) reg -= PCI_CAP_PCIE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) read_op = bridge->ops->read_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cfgspace = (__le32 *) &bridge->pcie_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) behavior = bridge->pcie_cap_regs_behavior;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) read_op = bridge->ops->read_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) cfgspace = (__le32 *) &bridge->conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) behavior = bridge->pci_regs_behavior;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (read_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = read_op(bridge, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) *value = le32_to_cpu(cfgspace[reg / 4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Make sure we never return any reserved bit with a value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * different from 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) behavior[reg / 4].w1c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *value = (*value >> (8 * (where & 3))) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *value = (*value >> (8 * (where & 3))) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) else if (size != 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * Should be called by the PCI controller driver when writing the PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * configuration space of the fake bridge. It will call back the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * ->ops->write_base or ->ops->write_pcie operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int reg = where & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int mask, ret, old, new, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) void (*write_op)(struct pci_bridge_emul *bridge, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 old, u32 new, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) __le32 *cfgspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) const struct pci_bridge_reg_behavior *behavior;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) shift = (where & 0x3) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (size == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mask = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mask = 0xffff << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) else if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mask = 0xff << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret != PCIBIOS_SUCCESSFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) reg -= PCI_CAP_PCIE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) write_op = bridge->ops->write_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) cfgspace = (__le32 *) &bridge->pcie_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) behavior = bridge->pcie_cap_regs_behavior;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) write_op = bridge->ops->write_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) cfgspace = (__le32 *) &bridge->conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) behavior = bridge->pci_regs_behavior;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Keep all bits, except the RW bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) new = old & (~mask | ~behavior[reg / 4].rw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Update the value of the RW bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) new |= (value << shift) & (behavior[reg / 4].rw & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Clear the W1C bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Save the new value with the cleared W1C bits into the cfgspace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) cfgspace[reg / 4] = cpu_to_le32(new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * Clear the W1C bits not specified by the write mask, so that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * write_op() does not clear them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) new &= ~(behavior[reg / 4].w1c & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Set the W1C bits specified by the write mask, so that write_op()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * knows about that they are to be cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) new |= (value << shift) & (behavior[reg / 4].w1c & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (write_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) write_op(bridge, reg, old, new, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_write);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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