^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCI Message Signaled Interrupt (MSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003-2004 Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2016 Christoph Hellwig.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/acpi_iort.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int pci_msi_enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int pci_msi_ignore_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) domain = dev_get_msi_domain(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (domain && irq_domain_is_hierarchy(domain))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return arch_setup_msi_irqs(dev, nvec, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) domain = dev_get_msi_domain(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (domain && irq_domain_is_hierarchy(domain))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) msi_domain_free_irqs(domain, &dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) arch_teardown_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Arch hooks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct msi_controller *chip = dev->bus->msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (!chip || !chip->setup_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) err = chip->setup_irq(chip, dev, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) irq_set_chip_data(desc->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void __weak arch_teardown_msi_irq(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct msi_controller *chip = irq_get_chip_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!chip || !chip->teardown_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) chip->teardown_irq(chip, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct msi_controller *chip = dev->bus->msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (chip && chip->setup_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return chip->setup_irqs(chip, dev, nvec, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * If an architecture wants to support multiple MSI, it needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * override arch_setup_msi_irqs()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (type == PCI_CAP_ID_MSI && nvec > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) for_each_pci_msi_entry(entry, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = arch_setup_msi_irq(dev, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * We have a default implementation available as a separate non-weak
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * function, as it is used by the Xen x86 PCI code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void default_teardown_msi_irqs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) for_each_pci_msi_entry(entry, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (entry->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) for (i = 0; i < entry->nvec_used; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) arch_teardown_msi_irq(entry->irq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return default_teardown_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif /* CONFIG_PCI_MSI_ARCH_FALLBACKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void default_restore_msi_irq(struct pci_dev *dev, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) entry = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (dev->msix_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for_each_pci_msi_entry(entry, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (irq == entry->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) } else if (dev->msi_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) entry = irq_get_msi_desc(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __pci_write_msi_msg(entry, &entry->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void __weak arch_restore_msi_irqs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return default_restore_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline __attribute_const__ u32 msi_mask(unsigned x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Don't shift by >= width of type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (x >= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return (1 << (1 << x)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * mask all MSI interrupts by clearing the MSI enable bit does not work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * reliably as devices without an INTx disable bit will then generate a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * level IRQ which will never be cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 mask_bits = desc->masked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mask_bits &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mask_bits |= flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mask_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return mask_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (desc->msi_attrib.is_virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return desc->mask_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * This internal function does not flush PCI writes to the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * All users must ensure that they read from the device before either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * assuming that the device state is up to date, or returning out of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * file. This saves a few milliseconds when initialising devices with lots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * of MSI-X interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 mask_bits = desc->masked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void __iomem *desc_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (pci_msi_ignore_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) desc_addr = pci_msix_desc_addr(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!desc_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return mask_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void msix_mask_irq(struct msi_desc *desc, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) desc->masked = __pci_msix_desc_mask_irq(desc, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void msi_set_mask_bit(struct irq_data *data, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct msi_desc *desc = irq_data_get_msi_desc(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (desc->msi_attrib.is_msix) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) msix_mask_irq(desc, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) readl(desc->mask_base); /* Flush write to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned offset = data->irq - desc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) msi_mask_irq(desc, 1 << offset, flag << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * @data: pointer to irqdata associated to that interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void pci_msi_mask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) msi_set_mask_bit(data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @data: pointer to irqdata associated to that interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void pci_msi_unmask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) msi_set_mask_bit(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void default_restore_msi_irqs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) for_each_pci_msi_entry(entry, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) default_restore_msi_irq(dev, entry->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct pci_dev *dev = msi_desc_to_pci_dev(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) BUG_ON(dev->current_state != PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (entry->msi_attrib.is_msix) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void __iomem *base = pci_msix_desc_addr(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int pos = dev->msi_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) &msg->address_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (entry->msi_attrib.is_64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) &msg->address_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) msg->address_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) msg->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct pci_dev *dev = msi_desc_to_pci_dev(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Don't touch the hardware now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) } else if (entry->msi_attrib.is_msix) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) void __iomem *base = pci_msix_desc_addr(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) bool unmasked = !(entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) goto skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * The specification mandates that the entry is masked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * when the message is modified:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * "If software changes the Address or Data value of an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * entry while the entry is unmasked, the result is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * undefined."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (unmasked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) __pci_msix_desc_mask_irq(entry, PCI_MSIX_ENTRY_CTRL_MASKBIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (unmasked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) __pci_msix_desc_mask_irq(entry, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Ensure that the writes are visible in the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) readl(base + PCI_MSIX_ENTRY_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int pos = dev->msi_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u16 msgctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) msgctl &= ~PCI_MSI_FLAGS_QSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) msgctl |= entry->msi_attrib.multiple << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) msg->address_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (entry->msi_attrib.is_64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) msg->address_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) msg->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) msg->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Ensure that the writes are visible in the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) skip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) entry->msg = *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (entry->write_msi_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) entry->write_msi_msg(entry, entry->write_msi_msg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct msi_desc *entry = irq_get_msi_desc(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) __pci_write_msi_msg(entry, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) EXPORT_SYMBOL_GPL(pci_write_msi_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static void free_msi_irqs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct list_head *msi_list = dev_to_msi_list(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct msi_desc *entry, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct attribute **msi_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct device_attribute *dev_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int i, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) for_each_pci_msi_entry(entry, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (entry->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) for (i = 0; i < entry->nvec_used; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) BUG_ON(irq_has_action(entry->irq + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (dev->msi_irq_groups) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) msi_attrs = dev->msi_irq_groups[0]->attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) while (msi_attrs[count]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_attr = container_of(msi_attrs[count],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct device_attribute, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) kfree(dev_attr->attr.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) kfree(dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ++count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) kfree(msi_attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) kfree(dev->msi_irq_groups[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) kfree(dev->msi_irq_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev->msi_irq_groups = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pci_msi_teardown_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) list_for_each_entry_safe(entry, tmp, msi_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (entry->msi_attrib.is_msix) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (list_is_last(&entry->list, msi_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) iounmap(entry->mask_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) list_del(&entry->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) free_msi_entry(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void pci_intx_for_msi(struct pci_dev *dev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pci_intx(dev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static void __pci_restore_msi_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u16 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!dev->msi_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) entry = irq_get_msi_desc(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pci_intx_for_msi(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pci_msi_set_enable(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) arch_restore_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) entry->masked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) control &= ~PCI_MSI_FLAGS_QSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static void __pci_restore_msix_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!dev->msix_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* route the table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pci_intx_for_msi(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pci_msix_clear_and_set_ctrl(dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) arch_restore_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) for_each_pci_msi_entry(entry, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) msix_mask_irq(entry, entry->masked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) void pci_restore_msi_state(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) __pci_restore_msi_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) __pci_restore_msix_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) EXPORT_SYMBOL_GPL(pci_restore_msi_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned long irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) retval = kstrtoul(attr->attr.name, 10, &irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) entry = irq_get_msi_desc(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return sprintf(buf, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) entry->msi_attrib.is_msix ? "msix" : "msi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int populate_msi_sysfs(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct attribute **msi_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct attribute *msi_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct device_attribute *msi_dev_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct attribute_group *msi_irq_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) const struct attribute_group **msi_irq_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int num_msi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Determine how many msi entries we have */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) for_each_pci_msi_entry(entry, pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) num_msi += entry->nvec_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (!num_msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Dynamically create the MSI attributes for the PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) msi_attrs = kcalloc(num_msi + 1, sizeof(void *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!msi_attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) for_each_pci_msi_entry(entry, pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) for (i = 0; i < entry->nvec_used; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!msi_dev_attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) goto error_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) msi_attrs[count] = &msi_dev_attr->attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) sysfs_attr_init(&msi_dev_attr->attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) entry->irq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!msi_dev_attr->attr.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) goto error_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) msi_dev_attr->attr.mode = S_IRUGO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) msi_dev_attr->show = msi_mode_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ++count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!msi_irq_group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) goto error_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) msi_irq_group->name = "msi_irqs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) msi_irq_group->attrs = msi_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) msi_irq_groups = kcalloc(2, sizeof(void *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!msi_irq_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) goto error_irq_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) msi_irq_groups[0] = msi_irq_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) goto error_irq_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pdev->msi_irq_groups = msi_irq_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) error_irq_groups:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) kfree(msi_irq_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) error_irq_group:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) kfree(msi_irq_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) error_attrs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) msi_attr = msi_attrs[count];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) while (msi_attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) kfree(msi_attr->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) kfree(msi_dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ++count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) msi_attr = msi_attrs[count];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) kfree(msi_attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static struct msi_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct irq_affinity_desc *masks = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u16 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (affd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) masks = irq_create_affinity_masks(nvec, affd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* MSI Entry Initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) entry = alloc_msi_entry(&dev->dev, nvec, masks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (!entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Lies, damned lies, and MSIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) control |= PCI_MSI_FLAGS_MASKBIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) entry->msi_attrib.is_msix = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) entry->msi_attrib.is_virtual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) entry->msi_attrib.entry_nr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (control & PCI_MSI_FLAGS_64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Save the initial mask status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (entry->msi_attrib.maskbit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) kfree(masks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int msi_verify_entries(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) for_each_pci_msi_entry(entry, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!dev->no_64bit_msi || !entry->msg.address_hi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pci_err(dev, "Device has broken 64-bit MSI but arch"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) " tried to assign one above 4G\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * msi_capability_init - configure device's MSI capability structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * @dev: pointer to the pci_dev data structure of MSI device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * @nvec: number of interrupts to allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * @affd: description of automatic IRQ affinity assignments (may be %NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * Setup the MSI capability structure of the device with the requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * number of interrupts. A return value of zero indicates the successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * setup of an entry with the new MSI IRQ. A negative return value indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * an error, and a positive return value indicates the number of interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * which could have been allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int msi_capability_init(struct pci_dev *dev, int nvec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct irq_affinity *affd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) entry = msi_setup_entry(dev, nvec, affd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (!entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* All MSIs are unmasked by default; mask them all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) mask = msi_mask(entry->msi_attrib.multi_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) msi_mask_irq(entry, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Configure MSI capability structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) msi_mask_irq(entry, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) free_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = msi_verify_entries(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) msi_mask_irq(entry, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) free_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret = populate_msi_sysfs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) msi_mask_irq(entry, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) free_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Set MSI enabled bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) pci_intx_for_msi(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) pci_msi_set_enable(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dev->msi_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pcibios_free_irq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev->irq = entry->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) resource_size_t phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u32 table_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u8 bir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) &table_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) flags = pci_resource_flags(dev, bir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (!flags || (flags & IORESOURCE_UNSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) table_offset &= PCI_MSIX_TABLE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) phys_addr = pci_resource_start(dev, bir) + table_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct msix_entry *entries, int nvec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct irq_affinity *affd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct irq_affinity_desc *curmsk, *masks = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int vec_count = pci_msix_vec_count(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (affd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) masks = irq_create_affinity_masks(nvec, affd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) for (i = 0, curmsk = masks; i < nvec; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) entry = alloc_msi_entry(&dev->dev, 1, curmsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (!entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (!i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) free_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* No enough memory. Don't try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) entry->msi_attrib.is_msix = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) entry->msi_attrib.is_64 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) entry->msi_attrib.entry_nr = entries[i].entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) entry->msi_attrib.entry_nr = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) entry->msi_attrib.is_virtual =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) entry->msi_attrib.entry_nr >= vec_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) entry->msi_attrib.default_irq = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) entry->mask_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) addr = pci_msix_desc_addr(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) entry->masked = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (masks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) curmsk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) kfree(masks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) for_each_pci_msi_entry(entry, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (entries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) entries->vector = entry->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) entries++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static void msix_mask_all(void __iomem *base, int tsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (pci_msi_ignore_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * msix_capability_init - configure device's MSI-X capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * @dev: pointer to the pci_dev data structure of MSI-X device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * @entries: pointer to an array of struct msix_entry entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * @nvec: number of @entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * @affd: Optional pointer to enable automatic affinity assignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * Setup the MSI-X capability structure of device function with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * single MSI-X IRQ. A return of zero indicates the successful setup of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int nvec, struct irq_affinity *affd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int ret, tsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u16 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * Some devices require MSI-X to be enabled before the MSI-X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * registers can be accessed. Mask all the vectors to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * interrupts coming in before they're fully set up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PCI_MSIX_FLAGS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* Request & Map MSI-X table region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) tsize = msix_table_size(control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) base = msix_map_region(dev, tsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = msix_setup_entries(dev, base, entries, nvec, affd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) goto out_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* Check if all MSI entries honor device restrictions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ret = msi_verify_entries(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) msix_update_entries(dev, entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = populate_msi_sysfs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* Set MSI-X enabled bits and unmask the function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) pci_intx_for_msi(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev->msix_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * Ensure that all table entries are masked to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * stale entries from firing in a crash kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * Done late to deal with a broken Marvell NVME device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * which takes the MSI-X mask bits into account even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * when MSI-X is disabled, which prevents MSI delivery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) msix_mask_all(base, tsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) pcibios_free_irq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) out_avail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * If we had some success, report the number of IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * we succeeded in setting up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int avail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) for_each_pci_msi_entry(entry, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (entry->irq != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) avail++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (avail != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) free_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * pci_msi_supported - check whether MSI may be enabled on a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * @dev: pointer to the pci_dev data structure of MSI device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * @nvec: how many MSIs have been requested?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * Look at global flags, the device itself, and its parent buses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * to determine if MSI/-X are supported for the device. If MSI/-X is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * supported return 1, else return 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int pci_msi_supported(struct pci_dev *dev, int nvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* MSI must be globally enabled and supported by the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (!pci_msi_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (!dev || dev->no_msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * You can't ask to have 0 or less MSIs configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * a) it's stupid ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * b) the list manipulation code assumes nvec >= 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (nvec < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * Any bridge which does NOT route MSI transactions from its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * secondary bus to its primary bus must set NO_MSI flag on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * the secondary pci_bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * We expect only arch-specific PCI host bus controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * or quirks for specific PCI bridges to be setting NO_MSI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) for (bus = dev->bus; bus; bus = bus->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * pci_msi_vec_count - Return the number of MSI vectors a device can send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * @dev: device to report about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * This function returns the number of MSI vectors a device requested via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * Multiple Message Capable register. It returns a negative errno if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * device is not capable sending MSI interrupts. Otherwise, the call succeeds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * and returns a power of two, up to a maximum of 2^5 (32), according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * MSI specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) int pci_msi_vec_count(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) u16 msgctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (!dev->msi_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) EXPORT_SYMBOL(pci_msi_vec_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static void pci_msi_shutdown(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct msi_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (!pci_msi_enable || !dev || !dev->msi_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) desc = first_pci_msi_entry(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) pci_msi_set_enable(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) pci_intx_for_msi(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev->msi_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Return the device with MSI unmasked as initial states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) mask = msi_mask(desc->msi_attrib.multi_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) msi_mask_irq(desc, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* Restore dev->irq to its default pin-assertion IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dev->irq = desc->msi_attrib.default_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) pcibios_alloc_irq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) void pci_disable_msi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (!pci_msi_enable || !dev || !dev->msi_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) pci_msi_shutdown(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) free_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) EXPORT_SYMBOL(pci_disable_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * pci_msix_vec_count - return the number of device's MSI-X table entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * @dev: pointer to the pci_dev data structure of MSI-X device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * This function returns the number of device's MSI-X table entries and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * therefore the number of MSI-X vectors device is capable of sending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * It returns a negative errno if the device is not capable of sending MSI-X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int pci_msix_vec_count(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u16 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (!dev->msix_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return msix_table_size(control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) EXPORT_SYMBOL(pci_msix_vec_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int nvec, struct irq_affinity *affd, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) int nr_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) nr_entries = pci_msix_vec_count(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (nr_entries < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return nr_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return nr_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (entries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* Check for any invalid entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) for (i = 0; i < nvec; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (entries[i].entry >= nr_entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return -EINVAL; /* invalid entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) for (j = i + 1; j < nvec; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (entries[i].entry == entries[j].entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return -EINVAL; /* duplicate entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* Check whether driver already requested for MSI IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (dev->msi_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return msix_capability_init(dev, entries, nvec, affd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static void pci_msix_shutdown(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (!pci_msi_enable || !dev || !dev->msix_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (pci_dev_is_disconnected(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dev->msix_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Return the device with MSI-X masked as initial states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) for_each_pci_msi_entry(entry, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) __pci_msix_desc_mask_irq(entry, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) pci_intx_for_msi(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) dev->msix_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) pcibios_alloc_irq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) void pci_disable_msix(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (!pci_msi_enable || !dev || !dev->msix_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) pci_msix_shutdown(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) free_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) EXPORT_SYMBOL(pci_disable_msix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) void pci_no_msi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) pci_msi_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * pci_msi_enabled - is MSI enabled?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * Returns true if MSI has not been disabled by the command-line option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * pci=nomsi.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) int pci_msi_enabled(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return pci_msi_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) EXPORT_SYMBOL(pci_msi_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct irq_affinity *affd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) int nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* Check whether driver already requested MSI-X IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (dev->msix_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (maxvec < minvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (WARN_ON_ONCE(dev->msi_enabled))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) nvec = pci_msi_vec_count(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (nvec < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (nvec < minvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (nvec > maxvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) nvec = maxvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (affd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (nvec < minvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) rc = msi_capability_init(dev, nvec, affd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (rc < minvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) nvec = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* deprecated, don't use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) int pci_enable_msi(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int rc = __pci_enable_msi_range(dev, 1, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) EXPORT_SYMBOL(pci_enable_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static int __pci_enable_msix_range(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct msix_entry *entries, int minvec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) int maxvec, struct irq_affinity *affd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) int rc, nvec = maxvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (maxvec < minvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (WARN_ON_ONCE(dev->msix_enabled))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (affd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (nvec < minvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (rc < minvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) nvec = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * pci_enable_msix_range - configure device's MSI-X capability structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * @dev: pointer to the pci_dev data structure of MSI-X device function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * @entries: pointer to an array of MSI-X entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * @minvec: minimum number of MSI-X IRQs requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * @maxvec: maximum number of MSI-X IRQs requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * Setup the MSI-X capability structure of device function with a maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * possible number of interrupts in the range between @minvec and @maxvec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * upon its software driver call to request for MSI-X mode enabled on its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * hardware device function. It returns a negative errno if an error occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * If it succeeds, it returns the actual number of interrupts allocated and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * indicates the successful configuration of MSI-X capability structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * with new allocated MSI-X interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) int minvec, int maxvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) EXPORT_SYMBOL(pci_enable_msix_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * @dev: PCI device to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * @min_vecs: minimum number of vectors required (must be >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * @max_vecs: maximum (desired) number of vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * @flags: flags or quirks for the allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * @affd: optional description of the affinity requirements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * vectors if available, and fall back to a single legacy vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * if neither is available. Return the number of vectors allocated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * (which might be smaller than @max_vecs) if successful, or a negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * error code on error. If less than @min_vecs interrupt vectors are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * available for @dev the function will fail with -ENOSPC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * To get the Linux IRQ number used for a vector that can be passed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * request_irq() use the pci_irq_vector() helper.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) unsigned int max_vecs, unsigned int flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct irq_affinity *affd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct irq_affinity msi_default_affd = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) int nvecs = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (flags & PCI_IRQ_AFFINITY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (!affd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) affd = &msi_default_affd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (WARN_ON(affd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) affd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (flags & PCI_IRQ_MSIX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) affd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (nvecs > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return nvecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (flags & PCI_IRQ_MSI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (nvecs > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return nvecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /* use legacy IRQ if allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (flags & PCI_IRQ_LEGACY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (min_vecs == 1 && dev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * Invoke the affinity spreading logic to ensure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * the device driver can adjust queue configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * for the single interrupt case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (affd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) irq_create_affinity_masks(1, affd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) pci_intx(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return nvecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * pci_free_irq_vectors - free previously allocated IRQs for a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * @dev: PCI device to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * Undoes the allocations and enabling in pci_alloc_irq_vectors().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) void pci_free_irq_vectors(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) pci_disable_msix(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) pci_disable_msi(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) EXPORT_SYMBOL(pci_free_irq_vectors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * pci_irq_vector - return Linux IRQ number of a device vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * @dev: PCI device to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * @nr: Interrupt vector index (0-based)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * @nr has the following meanings depending on the interrupt mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * MSI-X: The index in the MSI-X vector table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * MSI: The index of the enabled MSI vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * INTx: Must be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * Return: The Linux interrupt number or -EINVAl if @nr is out of range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (dev->msix_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) for_each_pci_msi_entry(entry, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (entry->msi_attrib.entry_nr == nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return entry->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (dev->msi_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct msi_desc *entry = first_pci_msi_entry(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (WARN_ON_ONCE(nr >= entry->nvec_used))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (WARN_ON_ONCE(nr > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return dev->irq + nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) EXPORT_SYMBOL(pci_irq_vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * pci_irq_get_affinity - return the affinity of a particular MSI vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * @dev: PCI device to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * @nr: device-relative interrupt vector index (0-based).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * @nr has the following meanings depending on the interrupt mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * MSI-X: The index in the MSI-X vector table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * MSI: The index of the enabled MSI vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * INTx: Must be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * Return: A cpumask pointer or NULL if @nr is out of range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (dev->msix_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) for_each_pci_msi_entry(entry, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (entry->msi_attrib.entry_nr == nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return &entry->affinity->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) } else if (dev->msi_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct msi_desc *entry = first_pci_msi_entry(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (WARN_ON_ONCE(!entry || !entry->affinity ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) nr >= entry->nvec_used))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return &entry->affinity[nr].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return cpu_possible_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) EXPORT_SYMBOL(pci_irq_get_affinity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return to_pci_dev(desc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) EXPORT_SYMBOL(msi_desc_to_pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) struct pci_dev *dev = msi_desc_to_pci_dev(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return dev->bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * @irq_data: Pointer to interrupt data of the MSI interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * @msg: Pointer to the message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * For MSI-X desc->irq is always equal to irq_data->irq. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * MSI only the first interrupt of MULTI MSI passes the test.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (desc->irq == irq_data->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) __pci_write_msi_msg(desc, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * @desc: Pointer to the MSI descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * The ID number is only used within the irqdomain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static irq_hw_number_t pci_msi_domain_calc_hwirq(struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct pci_dev *dev = msi_desc_to_pci_dev(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return (irq_hw_number_t)desc->msi_attrib.entry_nr |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) pci_dev_id(dev) << 11 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * pci_msi_domain_check_cap - Verify that @domain supports the capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * for @dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * @domain: The interrupt domain to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * @info: The domain info for verification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * @dev: The device to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) * 0 if the functionality is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * 1 if Multi MSI is requested, but the domain does not support it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * -ENOTSUPP otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) int pci_msi_domain_check_cap(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct msi_domain_info *info, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) /* Special handling to support __pci_enable_msi_range() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (pci_msi_desc_is_multi_msi(desc) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) static int pci_msi_domain_handle_error(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct msi_desc *desc, int error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* Special handling to support __pci_enable_msi_range() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) arg->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) arg->hwirq = pci_msi_domain_calc_hwirq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static struct msi_domain_ops pci_msi_domain_ops_default = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .set_desc = pci_msi_domain_set_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .msi_check = pci_msi_domain_check_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .handle_error = pci_msi_domain_handle_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) struct msi_domain_ops *ops = info->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (ops == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) info->ops = &pci_msi_domain_ops_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (ops->set_desc == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ops->set_desc = pci_msi_domain_set_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (ops->msi_check == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) ops->msi_check = pci_msi_domain_check_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (ops->handle_error == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ops->handle_error = pci_msi_domain_handle_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct irq_chip *chip = info->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) BUG_ON(!chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (!chip->irq_write_msi_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) chip->irq_write_msi_msg = pci_msi_domain_write_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (!chip->irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) chip->irq_mask = pci_msi_mask_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (!chip->irq_unmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) chip->irq_unmask = pci_msi_unmask_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) * pci_msi_create_irq_domain - Create a MSI interrupt domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) * @fwnode: Optional fwnode of the interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) * @info: MSI domain info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * @parent: Parent irq domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * Updates the domain and chip ops and creates a MSI interrupt domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * A domain pointer or NULL in case of failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct msi_domain_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct irq_domain *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (WARN_ON(info->flags & MSI_FLAG_LEVEL_CAPABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) info->flags &= ~MSI_FLAG_LEVEL_CAPABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) pci_msi_domain_update_dom_ops(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) pci_msi_domain_update_chip_ops(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) info->flags |= MSI_FLAG_ACTIVATE_EARLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) info->flags |= MSI_FLAG_MUST_REACTIVATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) /* PCI-MSI is oneshot-safe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) info->chip->flags |= IRQCHIP_ONESHOT_SAFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) domain = msi_create_irq_domain(fwnode, info, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (!domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * Users of the generic MSI infrastructure expect a device to have a single ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * so with DMA aliases we have to pick the least-worst compromise. Devices with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * DMA phantom functions tend to still emit MSIs from the real function number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * so we ignore those and only consider topological aliases where either the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * alias device or RID appears on a different bus number. We also make the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * reasonable assumption that bridges are walked in an upstream direction (so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * the last one seen wins), and the much braver assumption that the most likely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * case is that of PCI->PCIe so we should always use the alias RID. This echoes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * the logic from intel_irq_remapping's set_msi_sid(), which presumably works
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * for taking ownership all we can really do is close our eyes and hope...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) u32 *pa = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) u8 bus = PCI_BUS_NUM(*pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) *pa = alias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * @domain: The interrupt domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * @pdev: The PCI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * The RID for a device is formed from the alias, with a firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * supplied mapping applied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) * Returns: The RID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) struct device_node *of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) u32 rid = pci_dev_id(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) of_node = irq_domain_get_of_node(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) rid = of_node ? of_msi_map_id(&pdev->dev, of_node, rid) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) iort_msi_map_id(&pdev->dev, rid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return rid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) * @pdev: The PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) * Use the firmware data to find a device-specific MSI domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) * (i.e. not one that is set as a default).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) * Returns: The corresponding MSI domain or NULL if none has been found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) struct irq_domain *dom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) u32 rid = pci_dev_id(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) dom = of_msi_map_get_device_domain(&pdev->dev, rid, DOMAIN_BUS_PCI_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (!dom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) dom = iort_get_device_domain(&pdev->dev, rid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) DOMAIN_BUS_PCI_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) return dom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) * pci_dev_has_special_msi_domain - Check whether the device is handled by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) * a non-standard PCI-MSI domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) * @pdev: The PCI device to check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) * Returns: True if the device irqdomain or the bus irqdomain is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * non-standard PCI/MSI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) bool pci_dev_has_special_msi_domain(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) struct irq_domain *dom = dev_get_msi_domain(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (!dom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) dom = dev_get_msi_domain(&pdev->bus->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (!dom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return dom->bus_token != DOMAIN_BUS_PCI_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags