^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Standard PCI Hot Plug Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995,2001 Compaq Computer Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2001 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2003-2004 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "shpchp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Slot Available Register I field definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SLOT_33MHZ 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SLOT_66MHZ_PCIX 0x00001f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SLOT_100MHZ_PCIX 0x001f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SLOT_133MHZ_PCIX 0x1f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Slot Available Register II field definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SLOT_66MHZ 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SLOT_66MHZ_PCIX_266 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SLOT_100MHZ_PCIX_266 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SLOT_133MHZ_PCIX_266 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SLOT_66MHZ_PCIX_533 0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SLOT_100MHZ_PCIX_533 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SLOT_133MHZ_PCIX_533 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Slot Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SLOT_NUM 0x0000001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FIRST_DEV_NUM 0x00001F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PSN 0x07FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UPDOWN 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MRLSENSOR 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ATTN_BUTTON 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Interrupt Locator Register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CMD_INTR_PENDING (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SLOT_INTR_PENDING(i) (1 << (i + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Controller SERR-INT Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GLOBAL_INTR_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GLOBAL_SERR_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define COMMAND_INTR_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ARBITER_SERR_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define COMMAND_DETECTED (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ARBITER_DETECTED (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SERR_INTR_RSVDZ_MASK 0xfffc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Logical Slot Register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SLOT_REG(i) (SLOT1 + (4 * i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SLOT_STATE_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SLOT_STATE_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SLOT_STATE_PWRONLY (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SLOT_STATE_ENABLED (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SLOT_STATE_DISABLED (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PWR_LED_STATE_SHIFT (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PWR_LED_STATE_MASK (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ATN_LED_STATE_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ATN_LED_STATE_MASK (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ATN_LED_STATE_ON (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ATN_LED_STATE_BLINK (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ATN_LED_STATE_OFF (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define POWER_FAULT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ATN_BUTTON (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MRL_SENSOR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MHZ66_CAP (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PRSNT_SHIFT (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PRSNT_MASK (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCIX_CAP_SHIFT (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCIX_CAP_MASK_PI1 (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCIX_CAP_MASK_PI2 (7 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PRSNT_CHANGE_DETECTED (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ISO_PFAULT_DETECTED (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BUTTON_PRESS_DETECTED (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MRL_CHANGE_DETECTED (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CON_PFAULT_DETECTED (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PRSNT_CHANGE_INTR_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ISO_PFAULT_INTR_MASK (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BUTTON_PRESS_INTR_MASK (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MRL_CHANGE_INTR_MASK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CON_PFAULT_INTR_MASK (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MRL_CHANGE_SERR_MASK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CON_PFAULT_SERR_MASK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * SHPC Command Code definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Slot Operation 00h - 3Fh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Set Bus Segment Speed/Mode A 40h - 47h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Power-Only All Slots 48h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Enable All Slots 49h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Reserved Command Codes 60h - BFh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Vendor Specific Commands C0h - FFh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SET_SLOT_PWR 0x01 /* Slot Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SET_SLOT_ENABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SET_SLOT_DISABLE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SET_PWR_ON 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SET_PWR_BLINK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SET_PWR_OFF 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SET_ATTN_ON 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SET_ATTN_BLINK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SET_ATTN_OFF 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SETA_PCI_66MHZ 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SETA_PCIX_66MHZ 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SETA_PCIX_100MHZ 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SETA_PCIX_133MHZ 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SETA_RESERVED1 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SETA_RESERVED2 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SETA_RESERVED3 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SET_ENABLE_ALL 0x49 /* Enable All Slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SETB_PCI_66MHZ 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SETB_PCIX_66MHZ_PM 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SETB_PCIX_100MHZ_PM 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SETB_PCIX_133MHZ_PM 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SETB_PCIX_66MHZ_EM 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SETB_PCIX_100MHZ_EM 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SETB_PCIX_133MHZ_EM 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SETB_PCIX_66MHZ_266 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SETB_PCIX_100MHZ_266 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SETB_PCIX_133MHZ_266 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SETB_PCIX_66MHZ_533 0x5b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SETB_PCIX_100MHZ_533 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SETB_PCIX_133MHZ_533 0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SETB_RESERVED1 0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SETB_RESERVED2 0x5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * SHPC controller command error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SWITCH_OPEN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define INVALID_CMD 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define INVALID_SPEED_MODE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * For accessing SHPC Working Register Set via PCI Configuration Space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DWORD_SELECT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DWORD_DATA 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Field Offset in Logical Slot Register - byte boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SLOT_EVENT_LATCH 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SLOT_SERR_INT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static irqreturn_t shpc_isr(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void start_int_poll_timer(struct controller *ctrl, int sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int hpc_check_cmd_status(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline u8 shpc_readb(struct controller *ctrl, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return readb(ctrl->creg + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) writeb(val, ctrl->creg + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static inline u16 shpc_readw(struct controller *ctrl, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return readw(ctrl->creg + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writew(val, ctrl->creg + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline u32 shpc_readl(struct controller *ctrl, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return readl(ctrl->creg + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(val, ctrl->creg + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline int shpc_indirect_read(struct controller *ctrl, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 cap_offset = ctrl->cap_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct pci_dev *pdev = ctrl->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * This is the interrupt polling timeout function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void int_poll_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct controller *ctrl = from_timer(ctrl, t, poll_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Poll for interrupt events. regs == NULL => polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) shpc_isr(0, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!shpchp_poll_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) shpchp_poll_time = 2; /* default polling interval is 2 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) start_int_poll_timer(ctrl, shpchp_poll_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * This function starts the interrupt polling timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void start_int_poll_timer(struct controller *ctrl, int sec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Clamp to sane value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if ((sec <= 0) || (sec > 60))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) sec = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ctrl->poll_timer.expires = jiffies + sec * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) add_timer(&ctrl->poll_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static inline int is_ctrl_busy(struct controller *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return cmd_status & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * Returns 1 if SHPC finishes executing a command within 1 sec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * otherwise returns 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!is_ctrl_busy(ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Check every 0.1 sec for a total of 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (!is_ctrl_busy(ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static inline int shpc_wait_cmd(struct controller *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned long timeout = msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (shpchp_poll_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) rc = shpc_poll_ctrl_busy(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rc = wait_event_interruptible_timeout(ctrl->queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) !is_ctrl_busy(ctrl), timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (!rc && is_ctrl_busy(ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) retval = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ctrl_err(ctrl, "Command not completed in 1000 msec\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) } else if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) retval = -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ctrl_info(ctrl, "Command was interrupted by a signal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct controller *ctrl = slot->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u16 cmd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u16 temp_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mutex_lock(&slot->ctrl->cmd_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (!shpc_poll_ctrl_busy(ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* After 1 sec and and the controller is still busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ctrl_err(ctrl, "Controller is still busy after 1 sec\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) retval = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ++t_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) temp_word = (t_slot << 8) | (cmd & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* To make sure the Controller Busy bit is 0 before we send out the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) shpc_writew(ctrl, CMD, temp_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * Wait for command completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) retval = shpc_wait_cmd(slot->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cmd_status = hpc_check_cmd_status(slot->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (cmd_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) cmd, cmd_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) retval = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mutex_unlock(&slot->ctrl->cmd_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int hpc_check_cmd_status(struct controller *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) switch (cmd_status >> 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) retval = SWITCH_OPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ctrl_err(ctrl, "Switch opened!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) retval = INVALID_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ctrl_err(ctrl, "Invalid HPC command!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) retval = INVALID_SPEED_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ctrl_err(ctrl, "Invalid bus speed/mode!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) retval = cmd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int hpc_get_attention_status(struct slot *slot, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct controller *ctrl = slot->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case ATN_LED_STATE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *status = 1; /* On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case ATN_LED_STATE_BLINK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) *status = 2; /* Blink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case ATN_LED_STATE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *status = 0; /* Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) *status = 0xFF; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int hpc_get_power_status(struct slot *slot, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct controller *ctrl = slot->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case SLOT_STATE_PWRONLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *status = 2; /* Powered only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case SLOT_STATE_ENABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) *status = 1; /* Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case SLOT_STATE_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) *status = 0; /* Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *status = 0xFF; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int hpc_get_latch_status(struct slot *slot, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct controller *ctrl = slot->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int hpc_get_adapter_status(struct slot *slot, u8 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct controller *ctrl = slot->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *status = (state != 0x3) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct controller *ctrl = slot->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct controller *ctrl = slot->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u8 m66_cap = !!(slot_reg & MHZ66_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u8 pi, pcix_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) retval = hpc_get_prog_int(slot, &pi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) switch (pi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) __func__, slot_reg, pcix_cap, m66_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) switch (pcix_cap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case 0x1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) *value = PCI_SPEED_66MHz_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case 0x3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) *value = PCI_SPEED_133MHz_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case 0x4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) *value = PCI_SPEED_133MHz_PCIX_266;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case 0x5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) *value = PCI_SPEED_133MHz_PCIX_533;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case 0x2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) *value = PCI_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct controller *ctrl = slot->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (pi == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) *mode = (sec_bus_status & 0x0100) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) retval = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int hpc_query_power_fault(struct slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct controller *ctrl = slot->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Note: Logic 0 => fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return !(slot_reg & POWER_FAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int hpc_set_attention_status(struct slot *slot, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u8 slot_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) slot_cmd = SET_ATTN_OFF; /* OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) slot_cmd = SET_ATTN_ON; /* ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) slot_cmd = SET_ATTN_BLINK; /* BLINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static void hpc_set_green_led_on(struct slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static void hpc_set_green_led_off(struct slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static void hpc_set_green_led_blink(struct slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void hpc_release_ctlr(struct controller *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u32 slot_reg, serr_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * Mask event interrupts and SERRs of all slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) for (i = 0; i < ctrl->num_slots; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) slot_reg = shpc_readl(ctrl, SLOT_REG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) CON_PFAULT_SERR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) slot_reg &= ~SLOT_REG_RSVDZ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) shpc_writel(ctrl, SLOT_REG(i), slot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) cleanup_slots(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * Mask SERR and System Interrupt generation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) COMMAND_INTR_MASK | ARBITER_SERR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) serr_int &= ~SERR_INTR_RSVDZ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (shpchp_poll_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) del_timer(&ctrl->poll_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) free_irq(ctrl->pci_dev->irq, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pci_disable_msi(ctrl->pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) iounmap(ctrl->creg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int hpc_power_on_slot(struct slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int hpc_slot_enable(struct slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) retval = shpc_write_cmd(slot, slot->hp_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int hpc_slot_disable(struct slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) retval = shpc_write_cmd(slot, slot->hp_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int shpc_get_cur_bus_speed(struct controller *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct pci_bus *bus = ctrl->pci_dev->subordinate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if ((pi == 1) && (speed_mode > 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) switch (speed_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) bus_speed = PCI_SPEED_33MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case 0x1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) bus_speed = PCI_SPEED_66MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) case 0x2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) bus_speed = PCI_SPEED_66MHz_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case 0x3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) bus_speed = PCI_SPEED_100MHz_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) case 0x4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) bus_speed = PCI_SPEED_133MHz_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) case 0x5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) case 0x6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) case 0x7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case 0x8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) bus_speed = PCI_SPEED_66MHz_PCIX_266;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case 0x9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) bus_speed = PCI_SPEED_100MHz_PCIX_266;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case 0xa:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) bus_speed = PCI_SPEED_133MHz_PCIX_266;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) case 0xb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) bus_speed = PCI_SPEED_66MHz_PCIX_533;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case 0xc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) bus_speed = PCI_SPEED_100MHz_PCIX_533;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) case 0xd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) bus_speed = PCI_SPEED_133MHz_PCIX_533;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) bus->cur_bus_speed = bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dbg("Current bus speed = %d\n", bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int hpc_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct controller *ctrl = slot->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u8 pi, cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) pi = shpc_readb(ctrl, PROG_INTERFACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) case PCI_SPEED_33MHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) cmd = SETA_PCI_33MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) case PCI_SPEED_66MHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) cmd = SETA_PCI_66MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) case PCI_SPEED_66MHz_PCIX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) cmd = SETA_PCIX_66MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) case PCI_SPEED_100MHz_PCIX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) cmd = SETA_PCIX_100MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) case PCI_SPEED_133MHz_PCIX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) cmd = SETA_PCIX_133MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) case PCI_SPEED_66MHz_PCIX_ECC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) cmd = SETB_PCIX_66MHZ_EM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) case PCI_SPEED_100MHz_PCIX_ECC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) cmd = SETB_PCIX_100MHZ_EM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) case PCI_SPEED_133MHz_PCIX_ECC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) cmd = SETB_PCIX_133MHZ_EM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) case PCI_SPEED_66MHz_PCIX_266:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) cmd = SETB_PCIX_66MHZ_266;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) case PCI_SPEED_100MHz_PCIX_266:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) cmd = SETB_PCIX_100MHZ_266;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case PCI_SPEED_133MHz_PCIX_266:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) cmd = SETB_PCIX_133MHZ_266;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) case PCI_SPEED_66MHz_PCIX_533:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) cmd = SETB_PCIX_66MHZ_533;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) case PCI_SPEED_100MHz_PCIX_533:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) cmd = SETB_PCIX_100MHZ_533;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) case PCI_SPEED_133MHz_PCIX_533:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) cmd = SETB_PCIX_133MHZ_533;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) retval = shpc_write_cmd(slot, 0, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ctrl_err(ctrl, "%s: Write command failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) shpc_get_cur_bus_speed(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static irqreturn_t shpc_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct controller *ctrl = (struct controller *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u32 serr_int, slot_reg, intr_loc, intr_loc2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) int hp_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Check to see if it was our interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) intr_loc = shpc_readl(ctrl, INTR_LOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (!intr_loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!shpchp_poll_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * Mask Global Interrupt Mask - see implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * note on p. 139 of SHPC spec rev 1.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) serr_int |= GLOBAL_INTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) serr_int &= ~SERR_INTR_RSVDZ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) intr_loc2 = shpc_readl(ctrl, INTR_LOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (intr_loc & CMD_INTR_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * Command Complete Interrupt Pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * RO only - clear by writing 1 to the Command Completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * Detect bit in Controller SERR-INT register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) serr_int &= ~SERR_INTR_RSVDZ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) wake_up_interruptible(&ctrl->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (!(intr_loc & ~CMD_INTR_PENDING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* To find out which slot has interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) hp_slot, slot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (slot_reg & MRL_CHANGE_DETECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) shpchp_handle_switch_change(hp_slot, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (slot_reg & BUTTON_PRESS_DETECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) shpchp_handle_attention_button(hp_slot, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (slot_reg & PRSNT_CHANGE_DETECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) shpchp_handle_presence_change(hp_slot, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) shpchp_handle_power_fault(hp_slot, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Clear all slot events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) slot_reg &= ~SLOT_REG_RSVDZ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (!shpchp_poll_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* Unmask Global Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int shpc_get_max_bus_speed(struct controller *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct pci_bus *bus = ctrl->pci_dev->subordinate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (pi == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (slot_avail2 & SLOT_133MHZ_PCIX_533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) bus_speed = PCI_SPEED_133MHz_PCIX_533;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) bus_speed = PCI_SPEED_100MHz_PCIX_533;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) bus_speed = PCI_SPEED_66MHz_PCIX_533;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) bus_speed = PCI_SPEED_133MHz_PCIX_266;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) bus_speed = PCI_SPEED_100MHz_PCIX_266;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) bus_speed = PCI_SPEED_66MHz_PCIX_266;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (bus_speed == PCI_SPEED_UNKNOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (slot_avail1 & SLOT_133MHZ_PCIX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) bus_speed = PCI_SPEED_133MHz_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) else if (slot_avail1 & SLOT_100MHZ_PCIX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) bus_speed = PCI_SPEED_100MHz_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) else if (slot_avail1 & SLOT_66MHZ_PCIX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) bus_speed = PCI_SPEED_66MHz_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) else if (slot_avail2 & SLOT_66MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) bus_speed = PCI_SPEED_66MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) else if (slot_avail1 & SLOT_33MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) bus_speed = PCI_SPEED_33MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) bus->max_bus_speed = bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static const struct hpc_ops shpchp_hpc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .power_on_slot = hpc_power_on_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .slot_enable = hpc_slot_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .slot_disable = hpc_slot_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .set_bus_speed_mode = hpc_set_bus_speed_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .set_attention_status = hpc_set_attention_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .get_power_status = hpc_get_power_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .get_attention_status = hpc_get_attention_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .get_latch_status = hpc_get_latch_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .get_adapter_status = hpc_get_adapter_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .get_adapter_speed = hpc_get_adapter_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .get_prog_int = hpc_get_prog_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .query_power_fault = hpc_query_power_fault,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .green_led_on = hpc_set_green_led_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .green_led_off = hpc_set_green_led_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .green_led_blink = hpc_set_green_led_blink,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .release_ctlr = hpc_release_ctlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int rc = -1, num_slots = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) u8 hp_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) u32 shpc_base_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) u32 tempdword, slot_reg, slot_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ctrl_dbg(ctrl, "Hotplug Controller:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (pdev->vendor == PCI_VENDOR_ID_AMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) pdev->device == PCI_DEVICE_ID_AMD_GOLAM_7450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* amd shpc driver doesn't use Base Offset; assume 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ctrl->mmio_base = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ctrl->mmio_size = pci_resource_len(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (!ctrl->cap_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ctrl_err(ctrl, "Cannot find PCI capability\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ctrl_err(ctrl, "Cannot read base_offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) rc = shpc_indirect_read(ctrl, 3, &tempdword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ctrl_err(ctrl, "Cannot read slot config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) num_slots = tempdword & SLOT_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) for (i = 0; i < 9 + num_slots; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) rc = shpc_indirect_read(ctrl, i, &tempdword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ctrl_err(ctrl, "Cannot read creg (index = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ctrl->mmio_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) pci_resource_start(pdev, 0) + shpc_base_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ctrl->mmio_size = 0x24 + 0x4 * num_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) pdev->vendor, pdev->device, pdev->subsystem_vendor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) pdev->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) rc = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ctrl_err(ctrl, "pci_enable_device failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ctrl_err(ctrl, "Cannot reserve MMIO region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) rc = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (!ctrl->creg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ctrl->mmio_size, ctrl->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) rc = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) mutex_init(&ctrl->crit_sect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) mutex_init(&ctrl->cmd_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* Setup wait queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) init_waitqueue_head(&ctrl->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ctrl->hpc_ops = &shpchp_hpc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* Return PCI Controller Info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) slot_config = shpc_readl(ctrl, SLOT_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ctrl->num_slots = slot_config & SLOT_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ctrl->first_slot = (slot_config & PSN) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) COMMAND_INTR_MASK | ARBITER_SERR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) tempdword &= ~SERR_INTR_RSVDZ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* Mask the MRL sensor SERR Mask of individual slot in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * Slot SERR-INT Mask & clear all the existing event if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) hp_slot, slot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) CON_PFAULT_SERR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) slot_reg &= ~SLOT_REG_RSVDZ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (shpchp_poll_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* Install interrupt polling timer. Start with 10 sec delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) timer_setup(&ctrl->poll_timer, int_poll_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) start_int_poll_timer(ctrl, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* Installs the interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) rc = pci_enable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ctrl_info(ctrl, "Can't get msi for the hotplug controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ctrl_info(ctrl, "Use INTx for the hotplug controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) MY_NAME, (void *)ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ctrl->pci_dev->irq, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ctrl->pci_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) goto abort_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) shpc_get_max_bus_speed(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) shpc_get_cur_bus_speed(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * Unmask all event interrupts of all slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) hp_slot, slot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (!shpchp_poll_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* Unmask all general input interrupts and SERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) SERR_INTR_RSVDZ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* We end up here for the many possible ways to fail this API. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) abort_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) iounmap(ctrl->creg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) abort:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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