Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Standard Hot Plug Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 1995,2001 Compaq Computer Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2001 IBM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2003-2004 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #ifndef _SHPCHP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define _SHPCHP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/pci_hotplug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/sched/signal.h>	/* signal_pending(), struct timer_list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #if !defined(MODULE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	#define MY_NAME	"shpchp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	#define MY_NAME	THIS_MODULE->name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) extern bool shpchp_poll_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) extern int shpchp_poll_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) extern bool shpchp_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define dbg(format, arg...)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) do {									\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	if (shpchp_debug)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg);	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define err(format, arg...)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define info(format, arg...)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define warn(format, arg...)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ctrl_dbg(ctrl, format, arg...)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	do {								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		if (shpchp_debug)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			pci_printk(KERN_DEBUG, ctrl->pci_dev,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 					format, ## arg);		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define ctrl_err(ctrl, format, arg...)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	pci_err(ctrl->pci_dev, format, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define ctrl_info(ctrl, format, arg...)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	pci_info(ctrl->pci_dev, format, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define ctrl_warn(ctrl, format, arg...)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	pci_warn(ctrl->pci_dev, format, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SLOT_NAME_SIZE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) struct slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u8 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u8 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u32 number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u8 is_a_board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u8 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u8 attention_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u8 presence_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u8 latch_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u8 pwr_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct controller *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	const struct hpc_ops *hpc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct hotplug_slot hotplug_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct list_head	slot_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct delayed_work work;	/* work for button event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct workqueue_struct *wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u8 hp_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) struct event_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u32 event_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct slot *p_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) struct controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct mutex crit_sect;		/* critical section mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct mutex cmd_lock;		/* command lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int num_slots;			/* Number of slots on ctlr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	int slot_num_inc;		/* 1 or -1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct list_head slot_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	const struct hpc_ops *hpc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	wait_queue_head_t queue;	/* sleep & wake process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u8 slot_device_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u32 pcix_misc2_reg;	/* for amd pogo errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u32 first_slot;		/* First physical slot number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32 cap_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned long mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned long mmio_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	void __iomem *creg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct timer_list poll_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Define AMD SHPC ID  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCI_DEVICE_ID_AMD_POGO_7458	0x7458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* AMD PCI-X bridge registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCIX_MEM_BASE_LIMIT_OFFSET	0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCIX_MISCII_OFFSET		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCIX_MISC_BRIDGE_ERRORS_OFFSET	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* AMD PCIX_MISCII masks and offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PERRNONFATALENABLE_MASK		0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PERRFATALENABLE_MASK		0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PERRFLOODENABLE_MASK		0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SERRNONFATALENABLE_MASK		0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SERRFATALENABLE_MASK		0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PERR_OBSERVED_MASK		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* AMD PCIX_MEM_BASE_LIMIT masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RSE_MASK			0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define INT_BUTTON_IGNORE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define INT_PRESENCE_ON			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define INT_PRESENCE_OFF		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define INT_SWITCH_CLOSE		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define INT_SWITCH_OPEN			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define INT_POWER_FAULT			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define INT_POWER_FAULT_CLEAR		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define INT_BUTTON_PRESS		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define INT_BUTTON_RELEASE		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define INT_BUTTON_CANCEL		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define STATIC_STATE			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define BLINKINGON_STATE		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define BLINKINGOFF_STATE		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define POWERON_STATE			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define POWEROFF_STATE			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Error messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define INTERLOCK_OPEN			0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ADD_NOT_SUPPORTED		0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CARD_FUNCTIONING		0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ADAPTER_NOT_SAME		0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define NO_ADAPTER_PRESENT		0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define NOT_ENOUGH_RESOURCES		0x0000000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DEVICE_TYPE_NOT_SUPPORTED	0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define WRONG_BUS_FREQUENCY		0x0000000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define POWER_FAILURE			0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void shpchp_remove_ctrl_files(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int shpchp_sysfs_enable_slot(struct slot *slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int shpchp_sysfs_disable_slot(struct slot *slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int shpchp_configure_device(struct slot *p_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void shpchp_unconfigure_device(struct slot *p_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void cleanup_slots(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void shpchp_queue_pushbutton_work(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int shpc_init(struct controller *ctrl, struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline const char *slot_name(struct slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	return hotplug_slot_name(&slot->hotplug_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct ctrl_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	volatile u32 base_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	volatile u32 slot_avail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	volatile u32 slot_avail2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	volatile u32 slot_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	volatile u16 sec_bus_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	volatile u8  msi_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	volatile u8  prog_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	volatile u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	volatile u16 cmd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	volatile u32 intr_loc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	volatile u32 serr_loc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	volatile u32 serr_intr_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	volatile u32 slot1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* offsets to the controller registers based on the above structure layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) enum ctrl_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	BASE_OFFSET	 = offsetof(struct ctrl_reg, base_offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	SLOT_AVAIL1	 = offsetof(struct ctrl_reg, slot_avail1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	SLOT_AVAIL2	 = offsetof(struct ctrl_reg, slot_avail2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	SLOT_CONFIG	 = offsetof(struct ctrl_reg, slot_config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	SEC_BUS_CONFIG	 = offsetof(struct ctrl_reg, sec_bus_config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	MSI_CTRL	 = offsetof(struct ctrl_reg, msi_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	PROG_INTERFACE	 = offsetof(struct ctrl_reg, prog_interface),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	CMD		 = offsetof(struct ctrl_reg, cmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	CMD_STATUS	 = offsetof(struct ctrl_reg, cmd_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	INTR_LOC	 = offsetof(struct ctrl_reg, intr_loc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	SERR_LOC	 = offsetof(struct ctrl_reg, serr_loc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	SLOT1		 = offsetof(struct ctrl_reg, slot1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return container_of(hotplug_slot, struct slot, hotplug_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct slot *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		if (slot->device == device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			return slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	u32 pcix_misc2_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/* save MiscII register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	/* clear SERR/PERR enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	u32 pcix_misc2_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	u32 pcix_bridge_errors_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	u32 pcix_mem_base_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	u8  perr_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	u8  rse_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (perr_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		ctrl_dbg(p_slot->ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			 "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			 perr_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* write-one-to-clear Memory_Base_Limit[ RSE ] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	rse_set = pcix_mem_base_reg & RSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (rse_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	/* restore MiscII register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		pcix_misc2_temp |= SERRFATALENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		pcix_misc2_temp |= PERRFLOODENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		pcix_misc2_temp |= PERRFATALENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct hpc_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	int (*power_on_slot)(struct slot *slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	int (*slot_enable)(struct slot *slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	int (*slot_disable)(struct slot *slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	int (*get_power_status)(struct slot *slot, u8 *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	int (*get_attention_status)(struct slot *slot, u8 *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	int (*set_attention_status)(struct slot *slot, u8 status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	int (*get_latch_status)(struct slot *slot, u8 *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	int (*get_adapter_status)(struct slot *slot, u8 *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int (*get_prog_int)(struct slot *slot, u8 *prog_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	int (*query_power_fault)(struct slot *slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	void (*green_led_on)(struct slot *slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	void (*green_led_off)(struct slot *slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	void (*green_led_blink)(struct slot *slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	void (*release_ctlr)(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	int (*check_cmd_status)(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif				/* _SHPCHP_H */