^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCI Express Hot Plug Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995,2001 Compaq Computer Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2001 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2003-2004 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef _PCIEHP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define _PCIEHP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci_hotplug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rwsem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "../pcie/portdrv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) extern bool pciehp_poll_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) extern int pciehp_poll_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Set CONFIG_DYNAMIC_DEBUG=y and boot with 'dyndbg="file pciehp* +p"' to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * enable debug messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ctrl_dbg(ctrl, format, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) pci_dbg(ctrl->pcie->port, format, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ctrl_err(ctrl, format, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) pci_err(ctrl->pcie->port, format, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ctrl_info(ctrl, format, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) pci_info(ctrl->pcie->port, format, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ctrl_warn(ctrl, format, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) pci_warn(ctrl->pcie->port, format, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SLOT_NAME_SIZE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * struct controller - PCIe hotplug controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @pcie: pointer to the controller's PCIe port service device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @slot_cap: cached copy of the Slot Capabilities register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @slot_ctrl: cached copy of the Slot Control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @ctrl_lock: serializes writes to the Slot Control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @cmd_started: jiffies when the Slot Control register was last written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * the next write is allowed 1 second later, absent a Command Completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * interrupt (PCIe r4.0, sec 6.7.3.2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @cmd_busy: flag set on Slot Control register write, cleared by IRQ handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * on reception of a Command Completed event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @queue: wait queue to wake up on reception of a Command Completed event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * used for synchronous writes to the Slot Control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @pending_events: used by the IRQ handler to save events retrieved from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Slot Status register for later consumption by the IRQ thread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @notification_enabled: whether the IRQ was requested successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @power_fault_detected: whether a power fault was detected by the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * that has not yet been cleared by the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @poll_thread: thread to poll for slot events if no IRQ is available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * enabled with pciehp_poll_mode module parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @state: current state machine position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @state_lock: protects reads and writes of @state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * protects scheduling, execution and cancellation of @button_work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @button_work: work item to turn the slot on or off after 5 seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * in response to an Attention Button press
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @hotplug_slot: structure registered with the PCI hotplug core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @reset_lock: prevents access to the Data Link Layer Link Active bit in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Link Status register and to the Presence Detect State bit in the Slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Status register during a slot reset which may cause them to flap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @depth: Number of additional hotplug ports in the path to the root bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * used as lock subclass for @reset_lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @ist_running: flag to keep user request waiting while IRQ thread is running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @request_result: result of last user request submitted to the IRQ thread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @requester: wait queue to wake up on completion of user request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * used for synchronous slot enable/disable request via sysfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * PCIe hotplug has a 1:1 relationship between controller and slot, hence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * unlike other drivers, the two aren't represented by separate structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct pcie_device *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 slot_cap; /* capabilities and quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int inband_presence_disabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u16 slot_ctrl; /* control register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct mutex ctrl_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned long cmd_started;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int cmd_busy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) wait_queue_head_t queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) atomic_t pending_events; /* event handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int notification_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int power_fault_detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct task_struct *poll_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 state; /* state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct mutex state_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct delayed_work button_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct hotplug_slot hotplug_slot; /* hotplug core interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct rw_semaphore reset_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int ist_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int request_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) wait_queue_head_t requester;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * DOC: Slot state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @OFF_STATE: slot is powered off, no subordinate devices are enumerated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @BLINKINGON_STATE: slot will be powered on after the 5 second delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Power Indicator is blinking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @BLINKINGOFF_STATE: slot will be powered off after the 5 second delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Power Indicator is blinking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @POWERON_STATE: slot is currently powering on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @POWEROFF_STATE: slot is currently powering off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @ON_STATE: slot is powered on, subordinate devices have been enumerated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OFF_STATE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BLINKINGON_STATE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BLINKINGOFF_STATE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define POWERON_STATE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define POWEROFF_STATE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ON_STATE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * DOC: Flags to request an action from the IRQ thread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * These are stored together with events read from the Slot Status register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * hence must be greater than its 16-bit width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * %DISABLE_SLOT: Disable the slot in response to a user request via sysfs or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * an Attention Button press after the 5 second delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * %RERUN_ISR: Used by the IRQ handler to inform the IRQ thread that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * hotplug port was inaccessible when the interrupt occurred, requiring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * that the IRQ handler is rerun by the IRQ thread after it has made the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * hotplug port accessible by runtime resuming its parents to D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DISABLE_SLOT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RERUN_ISR (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MRL_SENS(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ATTN_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PWR_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PSN(ctrl) (((ctrl)->slot_cap & PCI_EXP_SLTCAP_PSN) >> 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void pciehp_request(struct controller *ctrl, int action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void pciehp_handle_button_press(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void pciehp_handle_disable_request(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int pciehp_configure_device(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) void pciehp_unconfigure_device(struct controller *ctrl, bool presence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) void pciehp_queue_pushbutton_work(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct controller *pcie_init(struct pcie_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int pcie_init_notification(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) void pcie_shutdown_notification(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void pcie_clear_hotplug_events(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void pcie_enable_interrupt(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void pcie_disable_interrupt(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int pciehp_power_on_slot(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void pciehp_power_off_slot(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void pciehp_get_power_status(struct controller *ctrl, u8 *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define INDICATOR_NOOP -1 /* Leave indicator unchanged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void pciehp_get_latch_status(struct controller *ctrl, u8 *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int pciehp_query_power_fault(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int pciehp_card_present(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int pciehp_card_present_or_link_active(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int pciehp_check_link_status(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int pciehp_check_link_active(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void pciehp_release_ctrl(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int pciehp_sysfs_enable_slot(struct hotplug_slot *hotplug_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int pciehp_sysfs_disable_slot(struct hotplug_slot *hotplug_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int pciehp_set_raw_indicator_status(struct hotplug_slot *h_slot, u8 status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int pciehp_get_raw_indicator_status(struct hotplug_slot *h_slot, u8 *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline const char *slot_name(struct controller *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return hotplug_slot_name(&ctrl->hotplug_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline struct controller *to_ctrl(struct hotplug_slot *hotplug_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return container_of(hotplug_slot, struct controller, hotplug_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #endif /* _PCIEHP_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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