^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __IBMPHP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __IBMPHP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * IBM Hot Plug Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Written By: Jyoti Shah, Tong Yu, Irene Zubarev, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2001-2003 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Send feedback to <gregkh@us.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pci_hotplug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) extern int ibmphp_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #if !defined(MODULE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MY_NAME "ibmphpd"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MY_NAME THIS_MODULE->name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define debug(fmt, arg...) do { if (ibmphp_debug == 1) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define debug_pci(fmt, arg...) do { if (ibmphp_debug) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* EBDA stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /***********************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * SLOT CAPABILITY *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ***********************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EBDA_SLOT_133_MAX 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EBDA_SLOT_100_MAX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EBDA_SLOT_66_MAX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EBDA_SLOT_PCIX_CAP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * RESOURCE TYPE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EBDA_RSRC_TYPE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EBDA_IO_RSRC_TYPE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EBDA_MEM_RSRC_TYPE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EBDA_PFM_RSRC_TYPE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EBDA_RES_RSRC_TYPE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * IO RESTRICTION TYPE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EBDA_IO_RESTRI_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EBDA_NO_RESTRI 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EBDA_AVO_VGA_ADDR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EBDA_AVO_VGA_ADDR_AND_ALIA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EBDA_AVO_ISA_ADDR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /**************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * DEVICE TYPE DEF *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) **************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EBDA_DEV_TYPE_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EBDA_PCI_DEV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define EBDA_NON_PCI_DEV 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /***************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * PRIMARY DEF DEFINITION *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ***************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define EBDA_PRI_DEF_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define EBDA_PRI_PCI_BUS_INFO 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define EBDA_NORM_DEV_RSRC_INFO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) //--------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) // RIO TABLE DATA STRUCTURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) //--------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct rio_table_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 ver_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 scal_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 riodev_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u16 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) //-------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) // SCALABILITY DETAIL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) //-------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct scal_detail {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 node_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 cbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 port0_node_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 port0_port_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 port1_node_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 port1_port_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 port2_node_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 port2_port_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 chassis_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) // struct list_head scal_detail_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) //--------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) // RIO DETAIL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) //--------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct rio_detail {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 rio_node_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 bbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 rio_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 owner_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 port0_node_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u8 port0_port_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 port1_node_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u8 port1_port_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 first_slot_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 wpindex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 chassis_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct list_head rio_detail_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct opt_rio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u8 rio_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u8 chassis_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 first_slot_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 middle_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct list_head opt_rio_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct opt_rio_lo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 rio_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u8 chassis_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 first_slot_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 middle_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 pack_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct list_head opt_rio_lo_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /****************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * HPC DESCRIPTOR NODE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct ebda_hpc_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u16 num_ctlrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) short phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) // struct list_head ebda_hpc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*****************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * IN HPC DATA STRUCTURE, THE ASSOCIATED SLOT AND BUS *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * STRUCTURE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct ebda_hpc_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u8 slot_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 slot_bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 ctl_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 slot_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct ebda_hpc_bus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 slots_at_33_conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 slots_at_66_conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 slots_at_66_pcix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 slots_at_100_pcix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 slots_at_133_pcix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * THREE TYPE OF HOT PLUG CONTROLLER *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct isa_ctlr_access {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u16 io_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u16 io_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct pci_ctlr_access {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u8 dev_fun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct wpeg_i2c_ctlr_access {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ulong wpegbbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define HPC_DEVICE_ID 0x0246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HPC_SUBSYSTEM_ID 0x0247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HPC_PCI_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * RSTC DESCRIPTOR NODE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct ebda_rsrc_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u16 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u16 phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct ebda_rsrc_list *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * PCI RSRC NODE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct ebda_pci_rsrc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u8 rsrc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 dev_fun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 end_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 marked; /* for NVRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct list_head ebda_pci_rsrc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /***********************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * BUS_INFO DATE STRUCTURE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ***********************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct bus_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 slot_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u8 slot_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 slot_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u8 busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 controller_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u8 current_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 current_bus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 slots_at_33_conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 slots_at_66_conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 slots_at_66_pcix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u8 slots_at_100_pcix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 slots_at_133_pcix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct list_head bus_info_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /***********************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * GLOBAL VARIABLES *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ***********************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) extern struct list_head ibmphp_ebda_pci_rsrc_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) extern struct list_head ibmphp_slot_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /***********************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * FUNCTION PROTOTYPES *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ***********************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void ibmphp_free_ebda_hpc_queue(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int ibmphp_access_ebda(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct slot *ibmphp_get_slot_from_physical_num(u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int ibmphp_get_total_hp_slots(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) void ibmphp_free_ibm_slot(struct slot *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void ibmphp_free_bus_info_queue(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void ibmphp_free_ebda_pci_rsrc_queue(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct bus_info *ibmphp_find_same_bus_num(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int ibmphp_get_bus_index(u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u16 ibmphp_get_total_controllers(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int ibmphp_register_pci(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* passed parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MEM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define PFMEM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define RESTYPE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IOMASK 0x00 /* will need to take its complement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define MMASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PFMASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PCIDEVMASK 0x10 /* we should always have PCI devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PRIMARYBUSMASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* pci specific defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define PCI_VENDOR_ID_NOTVALID 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define PCI_HEADER_TYPE_MULTIDEVICE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define PCI_HEADER_TYPE_MULTIBRIDGE 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define LATENCY 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CACHE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DEVICEENABLE 0x015F /* CPQ has 0x0157 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define IOBRIDGE 0x1000 /* 4k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define MEMBRIDGE 0x100000 /* 1M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SCSI_IRQ 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define LAN_IRQ 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define OTHER_IRQ 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Data Structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* type is of the form x x xx xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * | | | |_ 00 - I/O, 01 - Memory, 11 - PFMemory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * | | - 00 - No Restrictions, 01 - Avoid VGA, 10 - Avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * | | VGA and their aliases, 11 - Avoid ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * | - 1 - PCI device, 0 - non pci device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * - 1 - Primary PCI Bus Information (0 if Normal device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * the IO restrictions [2:3] are only for primary buses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* we need this struct because there could be several resource blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * allocated per primary bus in the EBDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct range_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int rangeno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct range_node *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct bus_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int noIORanges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct range_node *rangeIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int noMemRanges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct range_node *rangeMem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int noPFMemRanges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct range_node *rangePFMem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int needIOUpdate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int needMemUpdate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int needPFMemUpdate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct resource_node *firstIO; /* first IO resource on the Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct resource_node *firstMem; /* first memory resource on the Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct resource_node *firstPFMem; /* first prefetchable memory resource on the Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct resource_node *firstPFMemFromMem; /* when run out of pfmem available, taking from Mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct list_head bus_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct resource_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int rangeno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u8 busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 devfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int type; /* MEM, IO, PFMEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 fromMem; /* this is to indicate that the range is from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * from the Memory bucket rather than from PFMem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct resource_node *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct resource_node *nextRange; /* for the other mem range on bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct res_needed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 pfmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 not_correct; /* needed for return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int devices[32]; /* for device numbers behind this bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int ibmphp_rsrc_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int ibmphp_add_resource(struct resource_node *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int ibmphp_remove_resource(struct resource_node *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int ibmphp_find_resource(struct bus_node *, u32, struct resource_node **, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ibmphp_check_resource(struct resource_node *, u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int ibmphp_remove_bus(struct bus_node *, u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) void ibmphp_free_resources(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int ibmphp_add_pfmem_from_mem(struct resource_node *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct bus_node *ibmphp_find_res_bus(u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) void ibmphp_print_test(void); /* for debugging purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int ibmphp_hpc_readslot(struct slot *, u8, u8 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int ibmphp_hpc_writeslot(struct slot *, u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void ibmphp_lock_operations(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) void ibmphp_unlock_operations(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int ibmphp_hpc_start_poll_thread(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) void ibmphp_hpc_stop_poll_thread(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) // HPC return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define HPC_ERROR 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) //-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) // BUS INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) //-----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define BUS_SPEED 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define BUS_MODE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define BUS_MODE_PCIX 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define BUS_MODE_PCI 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define BUS_SPEED_2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define BUS_SPEED_1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define BUS_SPEED_33 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define BUS_SPEED_66 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define BUS_SPEED_100 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define BUS_SPEED_133 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define BUS_SPEED_66PCIX 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define BUS_SPEED_66UNKNOWN 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define BUS_STATUS_AVAILABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define BUS_CONTROL_AVAILABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SLOT_LATCH_REGS_SUPPORTED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define PRGM_MODEL_REV_LEVEL 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MAX_ADAPTER_NONE 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) // HPC 'write' operations/commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) // Command Code State Write to reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) // Machine at index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) //------------------------- ---- ------- ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define HPC_CTLR_ENABLEIRQ 0x00 // N 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define HPC_CTLR_DISABLEIRQ 0x01 // N 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define HPC_SLOT_OFF 0x02 // Y 0-14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define HPC_SLOT_ON 0x03 // Y 0-14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define HPC_SLOT_ATTNOFF 0x04 // N 0-14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define HPC_SLOT_ATTNON 0x05 // N 0-14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define HPC_CTLR_CLEARIRQ 0x06 // N 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define HPC_CTLR_RESET 0x07 // Y 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define HPC_CTLR_IRQSTEER 0x08 // N 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define HPC_BUS_33CONVMODE 0x09 // Y 31-34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define HPC_BUS_66CONVMODE 0x0A // Y 31-34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define HPC_BUS_66PCIXMODE 0x0B // Y 31-34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define HPC_BUS_100PCIXMODE 0x0C // Y 31-34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define HPC_BUS_133PCIXMODE 0x0D // Y 31-34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define HPC_ALLSLOT_OFF 0x11 // Y 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define HPC_ALLSLOT_ON 0x12 // Y 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define HPC_SLOT_BLINKLED 0x13 // N 0-14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) // read commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define READ_SLOTSTATUS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define READ_EXTSLOTSTATUS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define READ_BUSSTATUS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define READ_CTLRSTATUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define READ_ALLSTAT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define READ_ALLSLOT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define READ_SLOTLATCHLOWREG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define READ_REVLEVEL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define READ_HPCOPTIONS 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) // slot status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define HPC_SLOT_POWER 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define HPC_SLOT_CONNECT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define HPC_SLOT_ATTN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define HPC_SLOT_PRSNT2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define HPC_SLOT_PRSNT1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define HPC_SLOT_PWRGD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define HPC_SLOT_BUS_SPEED 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define HPC_SLOT_LATCH 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) // HPC_SLOT_POWER status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define HPC_SLOT_POWER_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define HPC_SLOT_POWER_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) // HPC_SLOT_CONNECT status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define HPC_SLOT_CONNECTED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define HPC_SLOT_DISCONNECTED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) // HPC_SLOT_ATTN status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define HPC_SLOT_ATTN_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define HPC_SLOT_ATTN_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define HPC_SLOT_ATTN_BLINK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) // HPC_SLOT_PRSNT status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define HPC_SLOT_EMPTY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define HPC_SLOT_PRSNT_7 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define HPC_SLOT_PRSNT_15 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define HPC_SLOT_PRSNT_25 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) // HPC_SLOT_PWRGD status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define HPC_SLOT_PWRGD_FAULT_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define HPC_SLOT_PWRGD_GOOD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) // HPC_SLOT_BUS_SPEED status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define HPC_SLOT_BUS_SPEED_OK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define HPC_SLOT_BUS_SPEED_MISM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) // HPC_SLOT_LATCH status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define HPC_SLOT_LATCH_OPEN 0x01 // NOTE : in PCI spec bit off = open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define HPC_SLOT_LATCH_CLOSED 0x00 // NOTE : in PCI spec bit on = closed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) // extended slot status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define HPC_SLOT_PCIX 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define HPC_SLOT_SPEED1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define HPC_SLOT_SPEED2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define HPC_SLOT_BLINK_ATTN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define HPC_SLOT_RSRVD1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define HPC_SLOT_RSRVD2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define HPC_SLOT_BUS_MODE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define HPC_SLOT_RSRVD3 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) // HPC_XSLOT_PCIX_CAP status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define HPC_SLOT_PCIX_NO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define HPC_SLOT_PCIX_YES 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) // HPC_XSLOT_SPEED status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define HPC_SLOT_SPEED_33 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define HPC_SLOT_SPEED_66 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define HPC_SLOT_SPEED_133 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) // HPC_XSLOT_ATTN_BLINK status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define HPC_SLOT_ATTN_BLINK_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define HPC_SLOT_ATTN_BLINK_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) // HPC_XSLOT_BUS_MODE status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define HPC_SLOT_BUS_MODE_OK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define HPC_SLOT_BUS_MODE_MISM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) // Controller status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define HPC_CTLR_WORKING 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define HPC_CTLR_FINISHED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define HPC_CTLR_RESULT0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define HPC_CTLR_RESULT1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define HPC_CTLR_RESULE2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define HPC_CTLR_RESULT3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define HPC_CTLR_IRQ_ROUTG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define HPC_CTLR_IRQ_PENDG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) // HPC_CTLR_WORKING status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define HPC_CTLR_WORKING_NO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define HPC_CTLR_WORKING_YES 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) // HPC_CTLR_FINISHED status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define HPC_CTLR_FINISHED_NO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define HPC_CTLR_FINISHED_YES 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) // HPC_CTLR_RESULT status return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define HPC_CTLR_RESULT_SUCCESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define HPC_CTLR_RESULT_FAILED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define HPC_CTLR_RESULT_RSVD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define HPC_CTLR_RESULT_NORESP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) // macro for slot info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define SLOT_POWER(s) ((u8) ((s & HPC_SLOT_POWER) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ? HPC_SLOT_POWER_ON : HPC_SLOT_POWER_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define SLOT_CONNECT(s) ((u8) ((s & HPC_SLOT_CONNECT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ? HPC_SLOT_DISCONNECTED : HPC_SLOT_CONNECTED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define SLOT_ATTN(s, es) ((u8) ((es & HPC_SLOT_BLINK_ATTN) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ? HPC_SLOT_ATTN_BLINK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) : ((s & HPC_SLOT_ATTN) ? HPC_SLOT_ATTN_ON : HPC_SLOT_ATTN_OFF)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define SLOT_PRESENT(s) ((u8) ((s & HPC_SLOT_PRSNT1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ? ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_EMPTY : HPC_SLOT_PRSNT_15) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) : ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_PRSNT_25 : HPC_SLOT_PRSNT_7)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define SLOT_PWRGD(s) ((u8) ((s & HPC_SLOT_PWRGD) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ? HPC_SLOT_PWRGD_GOOD : HPC_SLOT_PWRGD_FAULT_NONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define SLOT_BUS_SPEED(s) ((u8) ((s & HPC_SLOT_BUS_SPEED) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ? HPC_SLOT_BUS_SPEED_MISM : HPC_SLOT_BUS_SPEED_OK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define SLOT_LATCH(s) ((u8) ((s & HPC_SLOT_LATCH) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ? HPC_SLOT_LATCH_CLOSED : HPC_SLOT_LATCH_OPEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define SLOT_PCIX(es) ((u8) ((es & HPC_SLOT_PCIX) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ? HPC_SLOT_PCIX_YES : HPC_SLOT_PCIX_NO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define SLOT_SPEED(es) ((u8) ((es & HPC_SLOT_SPEED2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ? ((es & HPC_SLOT_SPEED1) ? HPC_SLOT_SPEED_133 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) : HPC_SLOT_SPEED_66) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) : HPC_SLOT_SPEED_33))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define SLOT_BUS_MODE(es) ((u8) ((es & HPC_SLOT_BUS_MODE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ? HPC_SLOT_BUS_MODE_MISM : HPC_SLOT_BUS_MODE_OK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) //--------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) // macro for bus info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) //---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define CURRENT_BUS_SPEED(s) ((u8) (s & BUS_SPEED_2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ? ((s & BUS_SPEED_1) ? BUS_SPEED_133 : BUS_SPEED_100) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) : ((s & BUS_SPEED_1) ? BUS_SPEED_66 : BUS_SPEED_33))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define CURRENT_BUS_MODE(s) ((u8) (s & BUS_MODE) ? BUS_MODE_PCIX : BUS_MODE_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define READ_BUS_STATUS(s) ((u8) (s->options & BUS_STATUS_AVAILABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define READ_BUS_MODE(s) ((s->revision & PRGM_MODEL_REV_LEVEL) >= 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define SET_BUS_STATUS(s) ((u8) (s->options & BUS_CONTROL_AVAILABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define READ_SLOT_LATCH(s) ((u8) (s->options & SLOT_LATCH_REGS_SUPPORTED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) // macro for controller info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) //----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define CTLR_WORKING(c) ((u8) ((c & HPC_CTLR_WORKING) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ? HPC_CTLR_WORKING_YES : HPC_CTLR_WORKING_NO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define CTLR_FINISHED(c) ((u8) ((c & HPC_CTLR_FINISHED) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ? HPC_CTLR_FINISHED_YES : HPC_CTLR_FINISHED_NO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define CTLR_RESULT(c) ((u8) ((c & HPC_CTLR_RESULT1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ? ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_NORESP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) : HPC_CTLR_RESULT_RSVD) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) : ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_FAILED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) : HPC_CTLR_RESULT_SUCCESS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) // command that affect the state machine of HPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define NEEDTOCHECK_CMDSTATUS(c) ((c == HPC_SLOT_OFF) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) (c == HPC_SLOT_ON) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) (c == HPC_CTLR_RESET) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) (c == HPC_BUS_33CONVMODE) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) (c == HPC_BUS_66CONVMODE) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) (c == HPC_BUS_66PCIXMODE) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) (c == HPC_BUS_100PCIXMODE) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) (c == HPC_BUS_133PCIXMODE) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) (c == HPC_ALLSLOT_OFF) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) (c == HPC_ALLSLOT_ON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* Core part of the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define CARD_INFO 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define PCIX133 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define PCIX66 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define PCI66 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) extern struct pci_bus *ibmphp_pci_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct pci_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct pci_dev *dev; /* from the OS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u8 busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u8 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u8 function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct resource_node *io[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct resource_node *mem[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct resource_node *pfmem[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct pci_func *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int devices[32]; /* for bridge config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u8 irq[4]; /* for interrupt config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u8 bus; /* flag for unconfiguring, to say if PPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u8 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u8 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u8 number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u8 real_physical_slot_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u32 capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u8 supported_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u8 supported_bus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u8 flag; /* this is for disable slot and polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u8 ctlr_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct hotplug_slot hotplug_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct controller *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct pci_func *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u8 irq[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int bit_mode; /* 0 = 32, 1 = 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct bus_info *bus_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct list_head ibm_slot_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u8 ext_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u8 busstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct ebda_hpc_slot *slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct ebda_hpc_bus *buses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct pci_dev *ctrl_dev; /* in case where controller is PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u8 starting_slot_num; /* starting and ending slot #'s this ctrl controls*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u8 ending_slot_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u8 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u8 options; /* which options HPC supports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) u8 ctlr_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u8 slot_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u8 bus_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u8 ctlr_relative_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u32 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct isa_ctlr_access isa_ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct pci_ctlr_access pci_ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct wpeg_i2c_ctlr_access wpeg_ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u8 ctlr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct list_head ebda_hpc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int ibmphp_init_devno(struct slot **); /* This function is called from EBDA, so we need it not be static */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int ibmphp_do_disable_slot(struct slot *slot_cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int ibmphp_update_slot_info(struct slot *); /* This function is called from HPC, so we need it to not be be static */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int ibmphp_configure_card(struct pci_func *, u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int ibmphp_unconfigure_card(struct slot **, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) extern const struct hotplug_slot_ops ibmphp_hotplug_slot_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static inline struct slot *to_slot(struct hotplug_slot *hotplug_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return container_of(hotplug_slot, struct slot, hotplug_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #endif //__IBMPHP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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