^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Compaq Hot Plug Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995,2001 Compaq Computer Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2001 IBM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Send feedback to <greg@kroah.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef _CPQPHP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define _CPQPHP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/io.h> /* for read? and write? functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h> /* for delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sched/signal.h> /* for signal_pending() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MY_NAME "cpqphp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define dbg(fmt, arg...) do { if (cpqhp_debug) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct smbios_system_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u16 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 name_string_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 slot_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 slot_current_usage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 slot_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u16 slot_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 properties1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 properties2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* offsets to the smbios generic type based on the above structure layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum smbios_system_slot_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SMBIOS_SLOT_GENERIC_TYPE = offsetof(struct smbios_system_slot, type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SMBIOS_SLOT_GENERIC_LENGTH = offsetof(struct smbios_system_slot, length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SMBIOS_SLOT_GENERIC_HANDLE = offsetof(struct smbios_system_slot, handle),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SMBIOS_SLOT_NAME_STRING_NUM = offsetof(struct smbios_system_slot, name_string_num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SMBIOS_SLOT_TYPE = offsetof(struct smbios_system_slot, slot_type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SMBIOS_SLOT_WIDTH = offsetof(struct smbios_system_slot, slot_width),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SMBIOS_SLOT_CURRENT_USAGE = offsetof(struct smbios_system_slot, slot_current_usage),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SMBIOS_SLOT_LENGTH = offsetof(struct smbios_system_slot, slot_length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SMBIOS_SLOT_NUMBER = offsetof(struct smbios_system_slot, slot_number),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SMBIOS_SLOT_PROPERTIES1 = offsetof(struct smbios_system_slot, properties1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SMBIOS_SLOT_PROPERTIES2 = offsetof(struct smbios_system_slot, properties2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct smbios_generic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u16 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* offsets to the smbios generic type based on the above structure layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) enum smbios_generic_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SMBIOS_GENERIC_TYPE = offsetof(struct smbios_generic, type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SMBIOS_GENERIC_LENGTH = offsetof(struct smbios_generic, length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SMBIOS_GENERIC_HANDLE = offsetof(struct smbios_generic, handle),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct smbios_entry_point {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) char anchor[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 ep_checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 ep_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 major_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 minor_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u16 max_size_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 ep_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 reserved[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) char int_anchor[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 int_checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u16 st_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 st_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u16 number_of_entrys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 bcd_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* offsets to the smbios entry point based on the above structure layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum smbios_entry_point_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ANCHOR = offsetof(struct smbios_entry_point, anchor[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) EP_CHECKSUM = offsetof(struct smbios_entry_point, ep_checksum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) EP_LENGTH = offsetof(struct smbios_entry_point, ep_length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MAJOR_VERSION = offsetof(struct smbios_entry_point, major_version),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MINOR_VERSION = offsetof(struct smbios_entry_point, minor_version),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MAX_SIZE_ENTRY = offsetof(struct smbios_entry_point, max_size_entry),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) EP_REV = offsetof(struct smbios_entry_point, ep_rev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) INT_ANCHOR = offsetof(struct smbios_entry_point, int_anchor[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) INT_CHECKSUM = offsetof(struct smbios_entry_point, int_checksum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ST_LENGTH = offsetof(struct smbios_entry_point, st_length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ST_ADDRESS = offsetof(struct smbios_entry_point, st_address),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) NUMBER_OF_ENTRYS = offsetof(struct smbios_entry_point, number_of_entrys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) BCD_REV = offsetof(struct smbios_entry_point, bcd_rev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct ctrl_reg { /* offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 slot_RST; /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 slot_enable; /* 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 misc; /* 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 led_control; /* 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 int_input_clear; /* 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 int_mask; /* 0x0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 reserved0; /* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 reserved1; /* 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 reserved2; /* 0x12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 gen_output_AB; /* 0x13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 non_int_input; /* 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 reserved3; /* 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 reserved4; /* 0x1a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 reserved5; /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 reserved6; /* 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 reserved7; /* 0x25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u16 reserved8; /* 0x26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 slot_mask; /* 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u8 reserved9; /* 0x29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 reserved10; /* 0x2a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 reserved11; /* 0x2b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 slot_SERR; /* 0x2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 slot_power; /* 0x2d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 reserved12; /* 0x2e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 reserved13; /* 0x2f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 next_curr_freq; /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 reset_freq_mode; /* 0x31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* offsets to the controller registers based on the above structure layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) enum ctrl_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SLOT_RST = offsetof(struct ctrl_reg, slot_RST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) SLOT_ENABLE = offsetof(struct ctrl_reg, slot_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MISC = offsetof(struct ctrl_reg, misc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) LED_CONTROL = offsetof(struct ctrl_reg, led_control),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) INT_INPUT_CLEAR = offsetof(struct ctrl_reg, int_input_clear),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) INT_MASK = offsetof(struct ctrl_reg, int_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CTRL_RESERVED0 = offsetof(struct ctrl_reg, reserved0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CTRL_RESERVED1 = offsetof(struct ctrl_reg, reserved1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CTRL_RESERVED2 = offsetof(struct ctrl_reg, reserved1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) GEN_OUTPUT_AB = offsetof(struct ctrl_reg, gen_output_AB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) NON_INT_INPUT = offsetof(struct ctrl_reg, non_int_input),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CTRL_RESERVED3 = offsetof(struct ctrl_reg, reserved3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CTRL_RESERVED4 = offsetof(struct ctrl_reg, reserved4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CTRL_RESERVED5 = offsetof(struct ctrl_reg, reserved5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CTRL_RESERVED6 = offsetof(struct ctrl_reg, reserved6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CTRL_RESERVED7 = offsetof(struct ctrl_reg, reserved7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CTRL_RESERVED8 = offsetof(struct ctrl_reg, reserved8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) SLOT_MASK = offsetof(struct ctrl_reg, slot_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CTRL_RESERVED9 = offsetof(struct ctrl_reg, reserved9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CTRL_RESERVED10 = offsetof(struct ctrl_reg, reserved10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CTRL_RESERVED11 = offsetof(struct ctrl_reg, reserved11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SLOT_SERR = offsetof(struct ctrl_reg, slot_SERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SLOT_POWER = offsetof(struct ctrl_reg, slot_power),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) NEXT_CURR_FREQ = offsetof(struct ctrl_reg, next_curr_freq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) RESET_FREQ_MODE = offsetof(struct ctrl_reg, reset_freq_mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct hrt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) char sig0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) char sig1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) char sig2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) char sig3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u16 unused_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u16 PCIIRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 number_of_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u16 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* offsets to the hotplug resource table registers based on the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * structure layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) enum hrt_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) SIG0 = offsetof(struct hrt, sig0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SIG1 = offsetof(struct hrt, sig1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SIG2 = offsetof(struct hrt, sig2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) SIG3 = offsetof(struct hrt, sig3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) UNUSED_IRQ = offsetof(struct hrt, unused_IRQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PCIIRQ = offsetof(struct hrt, PCIIRQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) NUMBER_OF_ENTRIES = offsetof(struct hrt, number_of_entries),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) REVISION = offsetof(struct hrt, revision),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) HRT_RESERVED1 = offsetof(struct hrt, reserved1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) HRT_RESERVED2 = offsetof(struct hrt, reserved2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct slot_rt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 dev_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 primary_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 secondary_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 max_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u16 io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u16 io_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u16 mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u16 mem_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u16 pre_mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u16 pre_mem_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* offsets to the hotplug slot resource table registers based on the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * structure layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) enum slot_rt_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) DEV_FUNC = offsetof(struct slot_rt, dev_func),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PRIMARY_BUS = offsetof(struct slot_rt, primary_bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SECONDARY_BUS = offsetof(struct slot_rt, secondary_bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MAX_BUS = offsetof(struct slot_rt, max_bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) IO_BASE = offsetof(struct slot_rt, io_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) IO_LENGTH = offsetof(struct slot_rt, io_length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MEM_BASE = offsetof(struct slot_rt, mem_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MEM_LENGTH = offsetof(struct slot_rt, mem_length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PRE_MEM_BASE = offsetof(struct slot_rt, pre_mem_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PRE_MEM_LENGTH = offsetof(struct slot_rt, pre_mem_length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct pci_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct pci_func *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u8 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 is_a_board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u8 configured;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 switch_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 presence_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 base_length[0x06];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 base_type[0x06];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 config_space[0x20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct pci_resource *mem_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct pci_resource *p_mem_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct pci_resource *io_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct pci_resource *bus_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct timer_list *p_task_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct slot *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u8 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u8 is_a_board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 configured;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u8 switch_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 presence_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct timer_list task_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u8 hp_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct controller *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void __iomem *p_sm_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct hotplug_slot hotplug_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct pci_resource {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct pci_resource *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct event_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 event_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 hp_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct controller *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 ctrl_int_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct mutex crit_sect; /* critical section mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) void __iomem *hpc_reg; /* cookie for our pci controller location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct pci_resource *mem_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct pci_resource *p_mem_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct pci_resource *io_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct pci_resource *bus_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct pci_bus *pci_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct event_info event_queue[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct slot *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u8 interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u8 cfgspc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 bus; /* bus number for the pci hotplug controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u8 slot_device_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u8 first_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u8 add_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u8 push_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u8 push_button; /* 0 = no pushbutton, 1 = pushbutton present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u8 slot_switch_type; /* 0 = no switch, 1 = switch present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u8 defeature_PHP; /* 0 = PHP not supported, 1 = PHP supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 alternate_base_address; /* 0 = not supported, 1 = supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 pci_config_space; /* Index/data access to working registers 0 = not supported, 1 = supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 pcix_speed_capability; /* PCI-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 pcix_support; /* PCI-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u16 vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct work_struct int_task_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) wait_queue_head_t queue; /* sleep & wake process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct dentry *dentry; /* debugfs dentry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct irq_mapping {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u8 barber_pole;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u8 valid_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 interrupt[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct resource_lists {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct pci_resource *mem_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct pci_resource *p_mem_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct pci_resource *io_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct pci_resource *bus_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct irq_mapping *irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define ROM_PHY_ADDR 0x0F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define ROM_PHY_LEN 0x00ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define PCI_HPC_ID 0xA0F7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define PCI_SUB_HPC_ID 0xA2F7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define PCI_SUB_HPC_ID2 0xA2F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define PCI_SUB_HPC_ID3 0xA2F9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define PCI_SUB_HPC_ID_INTC 0xA2FA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define PCI_SUB_HPC_ID4 0xA2FD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define INT_BUTTON_IGNORE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define INT_PRESENCE_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define INT_PRESENCE_OFF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define INT_SWITCH_CLOSE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define INT_SWITCH_OPEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define INT_POWER_FAULT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define INT_POWER_FAULT_CLEAR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define INT_BUTTON_PRESS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define INT_BUTTON_RELEASE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define INT_BUTTON_CANCEL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define STATIC_STATE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define BLINKINGON_STATE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define BLINKINGOFF_STATE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define POWERON_STATE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define POWEROFF_STATE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define PCISLOT_INTERLOCK_CLOSED 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define PCISLOT_ADAPTER_PRESENT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define PCISLOT_POWERED 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define PCISLOT_66_MHZ_OPERATION 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define PCISLOT_64_BIT_OPERATION 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define PCISLOT_REPLACE_SUPPORTED 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define PCISLOT_ADD_SUPPORTED 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PCISLOT_INTERLOCK_SUPPORTED 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PCISLOT_66_MHZ_SUPPORTED 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define PCISLOT_64_BIT_SUPPORTED 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define PCI_TO_PCI_BRIDGE_CLASS 0x00060400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define INTERLOCK_OPEN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define ADD_NOT_SUPPORTED 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CARD_FUNCTIONING 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define ADAPTER_NOT_SAME 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define NO_ADAPTER_PRESENT 0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define NOT_ENOUGH_RESOURCES 0x0000000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define POWER_FAILURE 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define REMOVE_NOT_SUPPORTED 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * error Messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define msg_initialization_err "Initialization failure, error=%d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define msg_HPC_rev_error "Unsupported revision of the PCI hot plug controller found.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define msg_HPC_non_compaq_or_intel "The PCI hot plug controller is not supported by this driver.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define msg_HPC_not_supported "this system is not supported by this version of cpqphpd. Upgrade to a newer version of cpqphpd\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define msg_unable_to_save "unable to store PCI hot plug add resource information. This system must be rebooted before adding any PCI devices.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define msg_button_on "PCI slot #%d - powering on due to button press.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define msg_button_off "PCI slot #%d - powering off due to button press.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define msg_button_cancel "PCI slot #%d - action canceled due to button press.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define msg_button_ignore "PCI slot #%d - button press ignored. (action in progress...)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* debugfs functions for the hotplug controller info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) void cpqhp_initialize_debugfs(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) void cpqhp_shutdown_debugfs(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) void cpqhp_create_debugfs_files(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) void cpqhp_remove_debugfs_files(struct controller *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* controller functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) void cpqhp_pushbutton_thread(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) irqreturn_t cpqhp_ctrl_intr(int IRQ, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int cpqhp_find_available_resources(struct controller *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) void __iomem *rom_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int cpqhp_event_start_thread(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) void cpqhp_event_stop_thread(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct pci_func *cpqhp_slot_create(unsigned char busnumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct pci_func *cpqhp_slot_find(unsigned char bus, unsigned char device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned char index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int cpqhp_process_SI(struct controller *ctrl, struct pci_func *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int cpqhp_process_SS(struct controller *ctrl, struct pci_func *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int cpqhp_hardware_test(struct controller *ctrl, int test_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* resource functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int cpqhp_resource_sort_and_combine(struct pci_resource **head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* pci functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int cpqhp_set_irq(u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int cpqhp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u8 slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int cpqhp_save_used_resources(struct controller *ctrl, struct pci_func *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int cpqhp_configure_board(struct controller *ctrl, struct pci_func *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int cpqhp_save_slot_config(struct controller *ctrl, struct pci_func *new_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int cpqhp_valid_replace(struct controller *ctrl, struct pci_func *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) void cpqhp_destroy_board_resources(struct pci_func *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int cpqhp_return_board_resources(struct pci_func *func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct resource_lists *resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void cpqhp_destroy_resource_list(struct resource_lists *resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int cpqhp_unconfigure_device(struct pci_func *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Global variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) extern int cpqhp_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) extern int cpqhp_legacy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) extern struct controller *cpqhp_ctrl_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) extern struct pci_func *cpqhp_slot_list[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) extern struct irq_routing_table *cpqhp_routing_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* these can be gotten rid of, but for debugging they are purty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) extern u8 cpqhp_nic_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) extern u8 cpqhp_disk_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* inline functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static inline const char *slot_name(struct slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return hotplug_slot_name(&slot->hotplug_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static inline struct slot *to_slot(struct hotplug_slot *hotplug_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return container_of(hotplug_slot, struct slot, hotplug_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * return_resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * Puts node back in the resource list pointed to by head
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static inline void return_resource(struct pci_resource **head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct pci_resource *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!node || !head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) node->next = *head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) *head = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static inline void set_SOGO(struct controller *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u16 misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) misc = readw(ctrl->hpc_reg + MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) misc = (misc | 0x0001) & 0xFFFB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) writew(misc, ctrl->hpc_reg + MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static inline void amber_LED_on(struct controller *ctrl, u8 slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 led_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) led_control = readl(ctrl->hpc_reg + LED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) led_control |= (0x01010000L << slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) writel(led_control, ctrl->hpc_reg + LED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static inline void amber_LED_off(struct controller *ctrl, u8 slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 led_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) led_control = readl(ctrl->hpc_reg + LED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) led_control &= ~(0x01010000L << slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) writel(led_control, ctrl->hpc_reg + LED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static inline int read_amber_LED(struct controller *ctrl, u8 slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 led_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) led_control = readl(ctrl->hpc_reg + LED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) led_control &= (0x01010000L << slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return led_control ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static inline void green_LED_on(struct controller *ctrl, u8 slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u32 led_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) led_control = readl(ctrl->hpc_reg + LED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) led_control |= 0x0101L << slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) writel(led_control, ctrl->hpc_reg + LED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static inline void green_LED_off(struct controller *ctrl, u8 slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 led_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) led_control = readl(ctrl->hpc_reg + LED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) led_control &= ~(0x0101L << slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) writel(led_control, ctrl->hpc_reg + LED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static inline void green_LED_blink(struct controller *ctrl, u8 slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 led_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) led_control = readl(ctrl->hpc_reg + LED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) led_control &= ~(0x0101L << slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) led_control |= (0x0001L << slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) writel(led_control, ctrl->hpc_reg + LED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static inline void slot_disable(struct controller *ctrl, u8 slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u8 slot_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) slot_enable = readb(ctrl->hpc_reg + SLOT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) slot_enable &= ~(0x01 << slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) writeb(slot_enable, ctrl->hpc_reg + SLOT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static inline void slot_enable(struct controller *ctrl, u8 slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u8 slot_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) slot_enable = readb(ctrl->hpc_reg + SLOT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) slot_enable |= (0x01 << slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) writeb(slot_enable, ctrl->hpc_reg + SLOT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static inline u8 is_slot_enabled(struct controller *ctrl, u8 slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u8 slot_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) slot_enable = readb(ctrl->hpc_reg + SLOT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) slot_enable &= (0x01 << slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return slot_enable ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static inline u8 read_slot_enable(struct controller *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return readb(ctrl->hpc_reg + SLOT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * get_controller_speed - find the current frequency/mode of controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * @ctrl: controller to get frequency/mode for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * Returns controller speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static inline u8 get_controller_speed(struct controller *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u8 curr_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u16 misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (ctrl->pcix_support) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) curr_freq = readb(ctrl->hpc_reg + NEXT_CURR_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if ((curr_freq & 0xB0) == 0xB0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return PCI_SPEED_133MHz_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if ((curr_freq & 0xA0) == 0xA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return PCI_SPEED_100MHz_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if ((curr_freq & 0x90) == 0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return PCI_SPEED_66MHz_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (curr_freq & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return PCI_SPEED_66MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return PCI_SPEED_33MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) misc = readw(ctrl->hpc_reg + MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return (misc & 0x0800) ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * get_adapter_speed - find the max supported frequency/mode of adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * @ctrl: hotplug controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * @hp_slot: hotplug slot where adapter is installed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * Returns adapter speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static inline u8 get_adapter_speed(struct controller *ctrl, u8 hp_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u32 temp_dword = readl(ctrl->hpc_reg + NON_INT_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dbg("slot: %d, PCIXCAP: %8x\n", hp_slot, temp_dword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (ctrl->pcix_support) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (temp_dword & (0x10000 << hp_slot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return PCI_SPEED_133MHz_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (temp_dword & (0x100 << hp_slot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return PCI_SPEED_66MHz_PCIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (temp_dword & (0x01 << hp_slot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return PCI_SPEED_66MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return PCI_SPEED_33MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static inline void enable_slot_power(struct controller *ctrl, u8 slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u8 slot_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) slot_power = readb(ctrl->hpc_reg + SLOT_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) slot_power |= (0x01 << slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) writeb(slot_power, ctrl->hpc_reg + SLOT_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static inline void disable_slot_power(struct controller *ctrl, u8 slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u8 slot_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) slot_power = readb(ctrl->hpc_reg + SLOT_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) slot_power &= ~(0x01 << slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) writeb(slot_power, ctrl->hpc_reg + SLOT_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static inline int cpq_get_attention_status(struct controller *ctrl, struct slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u8 hp_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) hp_slot = slot->device - ctrl->slot_device_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return read_amber_LED(ctrl, hp_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static inline int get_slot_enabled(struct controller *ctrl, struct slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u8 hp_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) hp_slot = slot->device - ctrl->slot_device_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return is_slot_enabled(ctrl, hp_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static inline int cpq_get_latch_status(struct controller *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u8 hp_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) hp_slot = slot->device - ctrl->slot_device_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dbg("%s: slot->device = %d, ctrl->slot_device_offset = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) __func__, slot->device, ctrl->slot_device_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) status = (readl(ctrl->hpc_reg + INT_INPUT_CLEAR) & (0x01L << hp_slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return (status == 0) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static inline int get_presence_status(struct controller *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int presence_save = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u8 hp_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 tempdword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) hp_slot = slot->device - ctrl->slot_device_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) tempdword = readl(ctrl->hpc_reg + INT_INPUT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) presence_save = (int) ((((~tempdword) >> 23) | ((~tempdword) >> 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) >> hp_slot) & 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return presence_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static inline int wait_for_ctrl_irq(struct controller *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) DECLARE_WAITQUEUE(wait, current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dbg("%s - start\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) add_wait_queue(&ctrl->queue, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Sleep for up to 1 second to wait for the LED to change. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) msleep_interruptible(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) remove_wait_queue(&ctrl->queue, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (signal_pending(current))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) retval = -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dbg("%s - end\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #include <asm/pci_x86.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static inline int cpqhp_routing_table_length(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) BUG_ON(cpqhp_routing_table == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return ((cpqhp_routing_table->size - sizeof(struct irq_routing_table)) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) sizeof(struct irq_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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