Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * cpcihp_zt5550.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Intel/Ziatech ZT5550 CompactPCI Host Controller driver definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright 2002 SOMA Networks, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright 2001 Intel San Luis Obispo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Copyright 2000,2001 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * Send feedback to <scottm@somanetworks.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef _CPCIHP_ZT5550_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define _CPCIHP_ZT5550_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Direct registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CSR_HCINDEX		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CSR_HCDATA		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CSR_INTSTAT		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CSR_INTMASK		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CSR_CNT0CMD		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CSR_CNT1CMD		0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CSR_CNT0		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CSR_CNT1		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Masks for interrupt bits in CSR_INTMASK direct register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CNT0_INT_MASK		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CNT1_INT_MASK		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ENUM_INT_MASK		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ALL_DIRECT_INTS_MASK	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Indexed registers (through CSR_INDEX, CSR_DATA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HC_INT_MASK_REG		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HC_STATUS_REG		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HC_CMD_REG		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ARB_CONFIG_GNT_REG	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ARB_CONFIG_CFG_REG	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ARB_CONFIG_REG		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ISOL_CONFIG_REG		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FAULT_STATUS_REG	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FAULT_CONFIG_REG	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WD_CONFIG_REG		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HC_DIAG_REG		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SERIAL_COMM_REG		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SERIAL_OUT_REG		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SERIAL_IN_REG		0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Masks for interrupt bits in HC_INT_MASK_REG indexed register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SERIAL_INT_MASK		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FAULT_INT_MASK		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HCF_INT_MASK		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ALL_INDEXED_INTS_MASK	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Digital I/O port storing ENUM# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ENUM_PORT	0xE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Mask to get to the ENUM# bit on the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ENUM_MASK	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif				/* _CPCIHP_ZT5550_H */