^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * cpcihp_zt5550.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Intel/Ziatech ZT5550 CompactPCI Host Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2002 SOMA Networks, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2001 Intel San Luis Obispo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2000,2001 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Send feedback to <scottm@somanetworks.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/signal.h> /* IRQF_SHARED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "cpci_hotplug.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "cpcihp_zt5550.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRIVER_VERSION "0.2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRIVER_AUTHOR "Scott Murray <scottm@somanetworks.com>"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRIVER_DESC "ZT5550 CompactPCI Hot Plug Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MY_NAME "cpcihp_zt5550"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define dbg(format, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) printk(KERN_DEBUG "%s: " format "\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MY_NAME, ## arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n", MY_NAME, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* local variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static bool debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static bool poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct cpci_hp_controller_ops zt5550_hpc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct cpci_hp_controller zt5550_hpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Primary cPCI bus bridge device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static struct pci_dev *bus0_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct pci_bus *bus0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Host controller device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct pci_dev *hc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Host controller register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void __iomem *hc_registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void __iomem *csr_hc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void __iomem *csr_hc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void __iomem *csr_int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void __iomem *csr_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int zt5550_hc_config(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Since we know that no boards exist with two HC chips, treat it as an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (hc_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) err("too many host controller devices?");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ret = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) err("cannot enable %s\n", pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) hc_dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dbg("hc_dev = %p", hc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dbg("pci resource start %llx", (unsigned long long)pci_resource_start(hc_dev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dbg("pci resource len %llx", (unsigned long long)pci_resource_len(hc_dev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (!request_mem_region(pci_resource_start(hc_dev, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pci_resource_len(hc_dev, 1), MY_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) err("cannot reserve MMIO region");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) goto exit_disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) hc_registers =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ioremap(pci_resource_start(hc_dev, 1), pci_resource_len(hc_dev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!hc_registers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) err("cannot remap MMIO region %llx @ %llx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) (unsigned long long)pci_resource_len(hc_dev, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) (unsigned long long)pci_resource_start(hc_dev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) goto exit_release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) csr_hc_index = hc_registers + CSR_HCINDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) csr_hc_data = hc_registers + CSR_HCDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) csr_int_status = hc_registers + CSR_INTSTAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) csr_int_mask = hc_registers + CSR_INTMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Disable host control, fault and serial interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dbg("disabling host control, fault and serial interrupts");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) writeb((u8) HC_INT_MASK_REG, csr_hc_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writeb((u8) ALL_INDEXED_INTS_MASK, csr_hc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dbg("disabled host control, fault and serial interrupts");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Disable timer0, timer1 and ENUM interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dbg("disabling timer0, timer1 and ENUM interrupts");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writeb((u8) ALL_DIRECT_INTS_MASK, csr_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dbg("disabled timer0, timer1 and ENUM interrupts");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) exit_release_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) release_mem_region(pci_resource_start(hc_dev, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pci_resource_len(hc_dev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) exit_disable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pci_disable_device(hc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int zt5550_hc_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!hc_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) iounmap(hc_registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) release_mem_region(pci_resource_start(hc_dev, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pci_resource_len(hc_dev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pci_disable_device(hc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int zt5550_hc_query_enum(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) value = inb_p(ENUM_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return ((value & ENUM_MASK) == ENUM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int zt5550_hc_check_irq(void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (dev_id == zt5550_hpc.dev_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) reg = readb(csr_int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int zt5550_hc_enable_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (hc_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) reg = readb(csr_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) reg = reg & ~ENUM_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) writeb(reg, csr_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int zt5550_hc_disable_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (hc_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) reg = readb(csr_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) reg = reg | ENUM_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writeb(reg, csr_int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int zt5550_hc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) status = zt5550_hc_config(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (status != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dbg("returned from zt5550_hc_config");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) memset(&zt5550_hpc, 0, sizeof(struct cpci_hp_controller));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) zt5550_hpc_ops.query_enum = zt5550_hc_query_enum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) zt5550_hpc.ops = &zt5550_hpc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (!poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) zt5550_hpc.irq = hc_dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) zt5550_hpc.irq_flags = IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) zt5550_hpc.dev_id = hc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) zt5550_hpc_ops.enable_irq = zt5550_hc_enable_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) zt5550_hpc_ops.disable_irq = zt5550_hc_disable_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) zt5550_hpc_ops.check_irq = zt5550_hc_check_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) info("using ENUM# polling mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) status = cpci_hp_register_controller(&zt5550_hpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) err("could not register cPCI hotplug controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) goto init_hc_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dbg("registered controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Look for first device matching cPCI bus's bridge vendor and device IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) bus0_dev = pci_get_device(PCI_VENDOR_ID_DEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PCI_DEVICE_ID_DEC_21154, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!bus0_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) status = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto init_register_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) bus0 = bus0_dev->subordinate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pci_dev_put(bus0_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) status = cpci_hp_register_bus(bus0, 0x0a, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) err("could not register cPCI hotplug bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto init_register_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dbg("registered bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) status = cpci_hp_start();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) err("could not started cPCI hotplug system");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) cpci_hp_unregister_bus(bus0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) goto init_register_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dbg("started cpci hp system");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) init_register_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) cpci_hp_unregister_controller(&zt5550_hpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) init_hc_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) err("status = %d", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) zt5550_hc_cleanup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static void zt5550_hc_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) cpci_hp_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) cpci_hp_unregister_bus(bus0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) cpci_hp_unregister_controller(&zt5550_hpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) zt5550_hc_cleanup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const struct pci_device_id zt5550_hc_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { PCI_VENDOR_ID_ZIATECH, PCI_DEVICE_ID_ZIATECH_5550_HC, PCI_ANY_ID, PCI_ANY_ID, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_DEVICE_TABLE(pci, zt5550_hc_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct pci_driver zt5550_hc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .name = "zt5550_hc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .id_table = zt5550_hc_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .probe = zt5550_hc_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .remove = zt5550_hc_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int __init zt5550_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) info(DRIVER_DESC " version: " DRIVER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) r = request_region(ENUM_PORT, 1, "#ENUM hotswap signal register");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (!r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) rc = pci_register_driver(&zt5550_hc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) release_region(ENUM_PORT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void __exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) zt5550_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pci_unregister_driver(&zt5550_hc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) release_region(ENUM_PORT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) module_init(zt5550_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) module_exit(zt5550_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_AUTHOR(DRIVER_AUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) module_param(debug, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MODULE_PARM_DESC(debug, "Debugging mode enabled or not");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) module_param(poll, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MODULE_PARM_DESC(poll, "#ENUM polling mode enabled or not");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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