^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Volume Management Device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2015, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/srcu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/rculist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/rcupdate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/msidef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VMD_CFGBAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VMD_MEMBAR1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VMD_MEMBAR2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCI_REG_VMCAP 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BUS_RESTRICT_CAP(vmcap) (vmcap & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCI_REG_VMCONFIG 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BUS_RESTRICT_CFG(vmcfg) ((vmcfg >> 8) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCI_REG_VMLOCK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MB2_SHADOW_EN(vmlock) (vmlock & 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MB2_SHADOW_OFFSET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MB2_SHADOW_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum vmd_features {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Device may contain registers which hint the physical location of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * membars, in order to allow proper address translation during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * resource assignment to enable guest virtualization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) VMD_FEAT_HAS_MEMBAR_SHADOW = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Device may provide root port configuration information which limits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * bus numbering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) VMD_FEAT_HAS_BUS_RESTRICTIONS = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Device contains physical location shadow registers in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * vendor-specific capability space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Lock for manipulating VMD IRQ lists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static DEFINE_RAW_SPINLOCK(list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * struct vmd_irq - private data to map driver IRQ to the VMD shared vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @node: list item for parent traversal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @irq: back pointer to parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @enabled: true if driver enabled IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @virq: the virtual IRQ value provided to the requesting driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * a VMD IRQ using this structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct vmd_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct vmd_irq_list *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @irq_list: the list of irq's the VMD one demuxes to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @srcu: SRCU struct for local synchronization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @count: number of child IRQs assigned to this vector; used to track
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * sharing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct vmd_irq_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct list_head irq_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct srcu_struct srcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct vmd_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) spinlock_t cfg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) char __iomem *cfgbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int msix_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct vmd_irq_list *irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct pci_sysdata sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct resource resources[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 busn_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return container_of(bus->sysdata, struct vmd_dev, sysdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline unsigned int index_from_irqs(struct vmd_dev *vmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct vmd_irq_list *irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return irqs - vmd->irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Drivers managing a device in a VMD domain allocate their own IRQs as before,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * but the MSI entry for the hardware it's driving will be programmed with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * destination ID for the VMD MSI-X table. The VMD muxes interrupts in its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * domain into one of its own, and the VMD driver de-muxes these for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * handlers sharing that VMD IRQ. The vmd irq_domain provides the operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * and irq_chip to set this up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void vmd_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct vmd_irq *vmdirq = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct vmd_irq_list *irq = vmdirq->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct vmd_dev *vmd = irq_data_get_irq_handler_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) msg->address_hi = MSI_ADDR_BASE_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) msg->address_lo = MSI_ADDR_BASE_LO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MSI_ADDR_DEST_ID(index_from_irqs(vmd, irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) msg->data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * We rely on MSI_FLAG_USE_DEF_CHIP_OPS to set the IRQ mask/unmask ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void vmd_irq_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct vmd_irq *vmdirq = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) raw_spin_lock_irqsave(&list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) WARN_ON(vmdirq->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) list_add_tail_rcu(&vmdirq->node, &vmdirq->irq->irq_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) vmdirq->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) raw_spin_unlock_irqrestore(&list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) data->chip->irq_unmask(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void vmd_irq_disable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct vmd_irq *vmdirq = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) data->chip->irq_mask(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) raw_spin_lock_irqsave(&list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (vmdirq->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) list_del_rcu(&vmdirq->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) vmdirq->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) raw_spin_unlock_irqrestore(&list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * XXX: Stubbed until we develop acceptable way to not create conflicts with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * other devices sharing the same vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int vmd_irq_set_affinity(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const struct cpumask *dest, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct irq_chip vmd_msi_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .name = "VMD-MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .irq_enable = vmd_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .irq_disable = vmd_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .irq_compose_msi_msg = vmd_compose_msi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .irq_set_affinity = vmd_irq_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static irq_hw_number_t vmd_get_hwirq(struct msi_domain_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) msi_alloc_info_t *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * XXX: We can be even smarter selecting the best IRQ once we solve the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * affinity problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd, struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int i, best = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (vmd->msix_count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return &vmd->irqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * White list for fast-interrupt handlers. All others will share the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * "slow" interrupt vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) switch (msi_desc_to_pci_dev(desc)->class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case PCI_CLASS_STORAGE_EXPRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return &vmd->irqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) raw_spin_lock_irqsave(&list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) for (i = 1; i < vmd->msix_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (vmd->irqs[i].count < vmd->irqs[best].count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) best = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) vmd->irqs[best].count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) raw_spin_unlock_irqrestore(&list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return &vmd->irqs[best];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int vmd_msi_init(struct irq_domain *domain, struct msi_domain_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned int virq, irq_hw_number_t hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) msi_alloc_info_t *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct msi_desc *desc = arg->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct vmd_dev *vmd = vmd_from_bus(msi_desc_to_pci_dev(desc)->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct vmd_irq *vmdirq = kzalloc(sizeof(*vmdirq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned int index, vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!vmdirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) INIT_LIST_HEAD(&vmdirq->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) vmdirq->irq = vmd_next_irq(vmd, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) vmdirq->virq = virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) index = index_from_irqs(vmd, vmdirq->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) vector = pci_irq_vector(vmd->dev, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) irq_domain_set_info(domain, virq, vector, info->chip, vmdirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) handle_untracked_irq, vmd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void vmd_msi_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct msi_domain_info *info, unsigned int virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct vmd_irq *vmdirq = irq_get_chip_data(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) synchronize_srcu(&vmdirq->irq->srcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* XXX: Potential optimization to rebalance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) raw_spin_lock_irqsave(&list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) vmdirq->irq->count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) raw_spin_unlock_irqrestore(&list_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) kfree(vmdirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int vmd_msi_prepare(struct irq_domain *domain, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int nvec, msi_alloc_info_t *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct vmd_dev *vmd = vmd_from_bus(pdev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (nvec > vmd->msix_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return vmd->msix_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) memset(arg, 0, sizeof(*arg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void vmd_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) arg->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct msi_domain_ops vmd_msi_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .get_hwirq = vmd_get_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .msi_init = vmd_msi_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .msi_free = vmd_msi_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .msi_prepare = vmd_msi_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .set_desc = vmd_set_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct msi_domain_info vmd_msi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MSI_FLAG_PCI_MSIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .ops = &vmd_msi_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .chip = &vmd_msi_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int vmd_create_irq_domain(struct vmd_dev *vmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct fwnode_handle *fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) fn = irq_domain_alloc_named_id_fwnode("VMD-MSI", vmd->sysdata.domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) vmd->irq_domain = pci_msi_create_irq_domain(fn, &vmd_msi_domain_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!vmd->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) irq_domain_free_fwnode(fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void vmd_remove_irq_domain(struct vmd_dev *vmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (vmd->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct fwnode_handle *fn = vmd->irq_domain->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) irq_domain_remove(vmd->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) irq_domain_free_fwnode(fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static char __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned int devfn, int reg, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) char __iomem *addr = vmd->cfgbar +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ((bus->number - vmd->busn_start) << 20) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) (devfn << 12) + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if ((addr - vmd->cfgbar) + len >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) resource_size(&vmd->dev->resource[VMD_CFGBAR]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * CPU may deadlock if config space is not serialized on some versions of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * hardware, so all config space access is done under a spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int len, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct vmd_dev *vmd = vmd_from_bus(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) spin_lock_irqsave(&vmd->cfg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *value = readb(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) *value = readw(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *value = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) spin_unlock_irqrestore(&vmd->cfg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * VMD h/w converts non-posted config writes to posted memory writes. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * read-back in this function forces the completion so it returns only after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * the config space was written, as expected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int len, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct vmd_dev *vmd = vmd_from_bus(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) spin_lock_irqsave(&vmd->cfg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) writeb(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) readb(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) writew(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) readw(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) writel(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) spin_unlock_irqrestore(&vmd->cfg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct pci_ops vmd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .read = vmd_pci_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .write = vmd_pci_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void vmd_attach_resources(struct vmd_dev *vmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) vmd->dev->resource[VMD_MEMBAR1].child = &vmd->resources[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) vmd->dev->resource[VMD_MEMBAR2].child = &vmd->resources[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void vmd_detach_resources(struct vmd_dev *vmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) vmd->dev->resource[VMD_MEMBAR1].child = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) vmd->dev->resource[VMD_MEMBAR2].child = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * VMD domains start at 0x10000 to not clash with ACPI _SEG domains.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * Per ACPI r6.0, sec 6.5.6, _SEG returns an integer, of which the lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * 16 bits are the PCI Segment Group (domain) number. Other bits are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * currently reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int vmd_find_free_domain(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int domain = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct pci_bus *bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) while ((bus = pci_find_next_bus(bus)) != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) domain = max_t(int, domain, pci_domain_nr(bus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return domain + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int vmd_get_phys_offsets(struct vmd_dev *vmd, bool native_hint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) resource_size_t *offset1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) resource_size_t *offset2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct pci_dev *dev = vmd->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u64 phys1, phys2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (native_hint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u32 vmlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = pci_read_config_dword(dev, PCI_REG_VMLOCK, &vmlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ret || vmlock == ~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (MB2_SHADOW_EN(vmlock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) void __iomem *membar2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) membar2 = pci_iomap(dev, VMD_MEMBAR2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!membar2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) phys1 = readq(membar2 + MB2_SHADOW_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) phys2 = readq(membar2 + MB2_SHADOW_OFFSET + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pci_iounmap(dev, membar2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Hypervisor-Emulated Vendor-Specific Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u32 reg, regu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pci_read_config_dword(dev, pos + 4, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* "SHDW" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (pos && reg == 0x53484457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pci_read_config_dword(dev, pos + 8, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pci_read_config_dword(dev, pos + 12, ®u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) phys1 = (u64) regu << 32 | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pci_read_config_dword(dev, pos + 16, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) pci_read_config_dword(dev, pos + 20, ®u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) phys2 = (u64) regu << 32 | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) *offset1 = dev->resource[VMD_MEMBAR1].start -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) (phys1 & PCI_BASE_ADDRESS_MEM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) *offset2 = dev->resource[VMD_MEMBAR2].start -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) (phys2 & PCI_BASE_ADDRESS_MEM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int vmd_get_bus_number_start(struct vmd_dev *vmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct pci_dev *dev = vmd->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pci_read_config_word(dev, PCI_REG_VMCAP, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (BUS_RESTRICT_CAP(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pci_read_config_word(dev, PCI_REG_VMCONFIG, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) switch (BUS_RESTRICT_CFG(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) vmd->busn_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) vmd->busn_start = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) vmd->busn_start = 224;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pci_err(dev, "Unknown Bus Offset Setting (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) BUS_RESTRICT_CFG(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static irqreturn_t vmd_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct vmd_irq_list *irqs = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct vmd_irq *vmdirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) idx = srcu_read_lock(&irqs->srcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) list_for_each_entry_rcu(vmdirq, &irqs->irq_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) generic_handle_irq(vmdirq->virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) srcu_read_unlock(&irqs->srcu, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int vmd_alloc_irqs(struct vmd_dev *vmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct pci_dev *dev = vmd->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) vmd->msix_count = pci_msix_vec_count(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (vmd->msix_count < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) vmd->msix_count = pci_alloc_irq_vectors(dev, 1, vmd->msix_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PCI_IRQ_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (vmd->msix_count < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return vmd->msix_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) vmd->irqs = devm_kcalloc(&dev->dev, vmd->msix_count, sizeof(*vmd->irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!vmd->irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) for (i = 0; i < vmd->msix_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) err = init_srcu_struct(&vmd->irqs[i].srcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) INIT_LIST_HEAD(&vmd->irqs[i].irq_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) err = devm_request_irq(&dev->dev, pci_irq_vector(dev, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) vmd_irq, IRQF_NO_THREAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) "vmd", &vmd->irqs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct pci_sysdata *sd = &vmd->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 upper_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) LIST_HEAD(resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) resource_size_t offset[2] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) resource_size_t membar2_offset = 0x2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct pci_bus *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * Shadow registers may exist in certain VMD device ids which allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * guests to correctly assign host physical addresses to the root ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * and child devices. These registers will either return the host value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * or 0, depending on an enable bit in the VMD device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (features & VMD_FEAT_HAS_MEMBAR_SHADOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) membar2_offset = MB2_SHADOW_OFFSET + MB2_SHADOW_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ret = vmd_get_phys_offsets(vmd, true, &offset[0], &offset[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) } else if (features & VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = vmd_get_phys_offsets(vmd, false, &offset[0], &offset[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * Certain VMD devices may have a root port configuration option which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * limits the bus range to between 0-127, 128-255, or 224-255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (features & VMD_FEAT_HAS_BUS_RESTRICTIONS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = vmd_get_bus_number_start(vmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) res = &vmd->dev->resource[VMD_CFGBAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) vmd->resources[0] = (struct resource) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .name = "VMD CFGBAR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .start = vmd->busn_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .end = vmd->busn_start + (resource_size(res) >> 20) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * If the window is below 4GB, clear IORESOURCE_MEM_64 so we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * put 32-bit resources in the window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * There's no hardware reason why a 64-bit window *couldn't*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * contain a 32-bit resource, but pbus_size_mem() computes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * bridge window size assuming a 64-bit window will contain no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * 32-bit resources. __pci_assign_resource() enforces that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * artificial restriction to make sure everything will fit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * The only way we could use a 64-bit non-prefetchable MEMBAR is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * if its address is <4GB so that we can convert it to a 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * resource. To be visible to the host OS, all VMD endpoints must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * be initially configured by platform BIOS, which includes setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * up these resources. We can assume the device is configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * according to the platform needs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) res = &vmd->dev->resource[VMD_MEMBAR1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) upper_bits = upper_32_bits(res->end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) flags = res->flags & ~IORESOURCE_SIZEALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!upper_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) flags &= ~IORESOURCE_MEM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) vmd->resources[1] = (struct resource) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .name = "VMD MEMBAR1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .start = res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .end = res->end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .flags = flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .parent = res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) res = &vmd->dev->resource[VMD_MEMBAR2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) upper_bits = upper_32_bits(res->end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) flags = res->flags & ~IORESOURCE_SIZEALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (!upper_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) flags &= ~IORESOURCE_MEM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) vmd->resources[2] = (struct resource) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .name = "VMD MEMBAR2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .start = res->start + membar2_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .end = res->end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .flags = flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .parent = res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) sd->vmd_dev = vmd->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) sd->domain = vmd_find_free_domain();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (sd->domain < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return sd->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) sd->node = pcibus_to_node(vmd->dev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret = vmd_create_irq_domain(vmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * Override the irq domain bus token so the domain can be distinguished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * from a regular PCI/MSI domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) irq_domain_update_bus_token(vmd->irq_domain, DOMAIN_BUS_VMD_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) pci_add_resource(&resources, &vmd->resources[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) pci_add_resource_offset(&resources, &vmd->resources[1], offset[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) pci_add_resource_offset(&resources, &vmd->resources[2], offset[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) &vmd_ops, sd, &resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (!vmd->bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pci_free_resource_list(&resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) vmd_remove_irq_domain(vmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) vmd_attach_resources(vmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (vmd->irq_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_set_msi_domain(&vmd->bus->dev, vmd->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) pci_scan_child_bus(vmd->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) pci_assign_unassigned_bus_resources(vmd->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * VMD root buses are virtual and don't return true on pci_is_pcie()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * and will fail pcie_bus_configure_settings() early. It can instead be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * run on each of the real root ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) list_for_each_entry(child, &vmd->bus->children, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) pcie_bus_configure_settings(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) pci_bus_add_devices(vmd->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) WARN(sysfs_create_link(&vmd->dev->dev.kobj, &vmd->bus->dev.kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "domain"), "Can't create symlink to domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct vmd_dev *vmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (resource_size(&dev->resource[VMD_CFGBAR]) < (1 << 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) vmd = devm_kzalloc(&dev->dev, sizeof(*vmd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!vmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) vmd->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) err = pcim_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) vmd->cfgbar = pcim_iomap(dev, VMD_CFGBAR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (!vmd->cfgbar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) err = vmd_alloc_irqs(vmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) spin_lock_init(&vmd->cfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) pci_set_drvdata(dev, vmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) err = vmd_enable_domain(vmd, (unsigned long) id->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dev_info(&vmd->dev->dev, "Bound to PCI domain %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) vmd->sysdata.domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static void vmd_cleanup_srcu(struct vmd_dev *vmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) for (i = 0; i < vmd->msix_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) cleanup_srcu_struct(&vmd->irqs[i].srcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static void vmd_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct vmd_dev *vmd = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) sysfs_remove_link(&vmd->dev->dev.kobj, "domain");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) pci_stop_root_bus(vmd->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) pci_remove_root_bus(vmd->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) vmd_cleanup_srcu(vmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) vmd_detach_resources(vmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) vmd_remove_irq_domain(vmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int vmd_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct vmd_dev *vmd = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) for (i = 0; i < vmd->msix_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) devm_free_irq(dev, pci_irq_vector(pdev, i), &vmd->irqs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int vmd_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct vmd_dev *vmd = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) for (i = 0; i < vmd->msix_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) err = devm_request_irq(dev, pci_irq_vector(pdev, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) vmd_irq, IRQF_NO_THREAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "vmd", &vmd->irqs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops, vmd_suspend, vmd_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static const struct pci_device_id vmd_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_201D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) VMD_FEAT_HAS_BUS_RESTRICTIONS,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x467f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) VMD_FEAT_HAS_BUS_RESTRICTIONS,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4c3d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) VMD_FEAT_HAS_BUS_RESTRICTIONS,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) VMD_FEAT_HAS_BUS_RESTRICTIONS,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) MODULE_DEVICE_TABLE(pci, vmd_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static struct pci_driver vmd_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .name = "vmd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .id_table = vmd_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .probe = vmd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .remove = vmd_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .pm = &vmd_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) module_pci_driver(vmd_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) MODULE_AUTHOR("Intel Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) MODULE_VERSION("0.6");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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