Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PCIe host controller driver for Xilinx AXI PCIe Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2012 - 2014 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on the Tegra PCIe driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Bits taken from Synopsys DesignWare Host controller driver and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * ARM PCI Host generic driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define XILINX_PCIE_REG_BIR		0x00000130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define XILINX_PCIE_REG_IDR		0x00000138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define XILINX_PCIE_REG_IMR		0x0000013c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define XILINX_PCIE_REG_PSCR		0x00000144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define XILINX_PCIE_REG_RPSC		0x00000148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define XILINX_PCIE_REG_MSIBASE1	0x0000014c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define XILINX_PCIE_REG_MSIBASE2	0x00000150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define XILINX_PCIE_REG_RPEFR		0x00000154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define XILINX_PCIE_REG_RPIFR1		0x00000158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define XILINX_PCIE_REG_RPIFR2		0x0000015c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* Interrupt registers definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define XILINX_PCIE_INTR_LINK_DOWN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define XILINX_PCIE_INTR_ECRC_ERR	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define XILINX_PCIE_INTR_STR_ERR	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define XILINX_PCIE_INTR_HOT_RESET	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define XILINX_PCIE_INTR_CFG_TIMEOUT	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define XILINX_PCIE_INTR_CORRECTABLE	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define XILINX_PCIE_INTR_NONFATAL	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define XILINX_PCIE_INTR_FATAL		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define XILINX_PCIE_INTR_INTX		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define XILINX_PCIE_INTR_MSI		BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define XILINX_PCIE_INTR_SLV_UNSUPP	BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define XILINX_PCIE_INTR_SLV_UNEXP	BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define XILINX_PCIE_INTR_SLV_COMPL	BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define XILINX_PCIE_INTR_SLV_ERRP	BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define XILINX_PCIE_INTR_SLV_CMPABT	BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define XILINX_PCIE_INTR_SLV_ILLBUR	BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define XILINX_PCIE_INTR_MST_DECERR	BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define XILINX_PCIE_INTR_MST_SLVERR	BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define XILINX_PCIE_INTR_MST_ERRP	BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define XILINX_PCIE_IMR_ALL_MASK	0x1FF30FED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define XILINX_PCIE_IMR_ENABLE_MASK	0x1FF30F0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define XILINX_PCIE_IDR_ALL_MASK	0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* Root Port Error FIFO Read Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define XILINX_PCIE_RPEFR_ERR_VALID	BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define XILINX_PCIE_RPEFR_REQ_ID	GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define XILINX_PCIE_RPEFR_ALL_MASK	0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* Root Port Interrupt FIFO Read Register 1 definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define XILINX_PCIE_RPIFR1_INTR_VALID	BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define XILINX_PCIE_RPIFR1_MSI_INTR	BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define XILINX_PCIE_RPIFR1_INTR_MASK	GENMASK(28, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define XILINX_PCIE_RPIFR1_ALL_MASK	0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define XILINX_PCIE_RPIFR1_INTR_SHIFT	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* Bridge Info Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define XILINX_PCIE_BIR_ECAM_SZ_MASK	GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define XILINX_PCIE_BIR_ECAM_SZ_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /* Root Port Interrupt FIFO Read Register 2 definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define XILINX_PCIE_RPIFR2_MSG_DATA	GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* Root Port Status/control Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define XILINX_PCIE_REG_RPSC_BEN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* Phy Status/Control Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define XILINX_PCIE_REG_PSCR_LNKUP	BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* ECAM definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define ECAM_BUS_NUM_SHIFT		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define ECAM_DEV_NUM_SHIFT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* Number of MSI IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define XILINX_NUM_MSI_IRQS		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * struct xilinx_pcie_port - PCIe port information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * @reg_base: IO Mapped Register Base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * @irq: Interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * @msi_pages: MSI pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * @dev: Device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * @msi_domain: MSI IRQ domain pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * @leg_domain: Legacy IRQ domain pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * @resources: Bus Resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct xilinx_pcie_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u32 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	unsigned long msi_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct irq_domain *msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct irq_domain *leg_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct list_head resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return readl(port->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	writel(val, port->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline bool xilinx_pcie_link_up(struct xilinx_pcie_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return (pcie_read(port, XILINX_PCIE_REG_PSCR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * @port: PCIe port information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct device *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	unsigned long val = pcie_read(port, XILINX_PCIE_REG_RPEFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		dev_dbg(dev, "Requester ID %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			val & XILINX_PCIE_RPEFR_REQ_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			   XILINX_PCIE_REG_RPEFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  * xilinx_pcie_valid_device - Check if a valid device is present on bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * @bus: PCI Bus structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * @devfn: device/function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * Return: 'true' on success and 'false' if invalid device is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct xilinx_pcie_port *port = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* Check if link is up when trying to access downstream ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (!pci_is_root_bus(bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		if (!xilinx_pcie_link_up(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	} else if (devfn > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		/* Only one device down on each root port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  * xilinx_pcie_map_bus - Get configuration base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * @bus: PCI Bus structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * @devfn: Device/function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  * @where: Offset from base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  * Return: Base address of the configuration space needed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  *	   accessed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 					 unsigned int devfn, int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct xilinx_pcie_port *port = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	int relbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (!xilinx_pcie_valid_device(bus, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		 (devfn << ECAM_DEV_NUM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return port->reg_base + relbus + where;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* PCIe operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct pci_ops xilinx_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.map_bus = xilinx_pcie_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.read	= pci_generic_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.write	= pci_generic_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* MSI functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * xilinx_pcie_destroy_msi - Free MSI number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * @irq: IRQ to be freed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void xilinx_pcie_destroy_msi(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct msi_desc *msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct xilinx_pcie_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct irq_data *d = irq_get_irq_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (!test_bit(hwirq, msi_irq_in_use)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		msi = irq_get_msi_desc(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		port = msi_desc_to_pci_sysdata(msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		clear_bit(hwirq, msi_irq_in_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * xilinx_pcie_assign_msi - Allocate MSI number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  * Return: A valid IRQ on success and error value on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int xilinx_pcie_assign_msi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (pos < XILINX_NUM_MSI_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		set_bit(pos, msi_irq_in_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  * xilinx_msi_teardown_irq - Destroy the MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  * @chip: MSI Chip descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  * @irq: MSI IRQ to destroy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void xilinx_msi_teardown_irq(struct msi_controller *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 				    unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	xilinx_pcie_destroy_msi(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	irq_dispose_mapping(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  * xilinx_pcie_msi_setup_irq - Setup MSI request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  * @chip: MSI chip pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  * @pdev: PCIe device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  * @desc: MSI descriptor pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  * Return: '0' on success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				     struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 				     struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct xilinx_pcie_port *port = pdev->bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct msi_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	phys_addr_t msg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	hwirq = xilinx_pcie_assign_msi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (hwirq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	irq = irq_create_mapping(port->msi_domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	irq_set_msi_desc(irq, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	msg_addr = virt_to_phys((void *)port->msi_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	msg.address_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	msg.address_lo = msg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	msg.data = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	pci_write_msi_msg(irq, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* MSI Chip Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct msi_controller xilinx_pcie_msi_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.setup_irq = xilinx_pcie_msi_setup_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.teardown_irq = xilinx_msi_teardown_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* HW Interrupt Chip Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct irq_chip xilinx_msi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.name = "Xilinx PCIe MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.irq_enable = pci_msi_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.irq_disable = pci_msi_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.irq_mask = pci_msi_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.irq_unmask = pci_msi_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)  * xilinx_pcie_msi_map - Set the handler for the MSI and mark IRQ as valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)  * @domain: IRQ domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)  * @irq: Virtual IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)  * @hwirq: HW interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)  * Return: Always returns 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int xilinx_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			       irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	irq_set_chip_and_handler(irq, &xilinx_msi_irq_chip, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	irq_set_chip_data(irq, domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* IRQ Domain operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const struct irq_domain_ops msi_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.map = xilinx_pcie_msi_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)  * xilinx_pcie_enable_msi - Enable MSI support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)  * @port: PCIe port information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	phys_addr_t msg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	port->msi_pages = __get_free_pages(GFP_KERNEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	if (!port->msi_pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	msg_addr = virt_to_phys((void *)port->msi_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* INTx Functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)  * xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)  * @domain: IRQ domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)  * @irq: Virtual IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)  * @hwirq: HW interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)  * Return: Always returns 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int xilinx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 				irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	irq_set_chip_data(irq, domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* INTx IRQ Domain operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct irq_domain_ops intx_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.map = xilinx_pcie_intx_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.xlate = pci_irqd_intx_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* PCIe HW Functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)  * xilinx_pcie_intr_handler - Interrupt Service Handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)  * @irq: IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)  * @data: PCIe port information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)  * Return: IRQ_HANDLED on success and IRQ_NONE on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	struct device *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	u32 val, mask, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	/* Read interrupt decode and mask registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	val = pcie_read(port, XILINX_PCIE_REG_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	mask = pcie_read(port, XILINX_PCIE_REG_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	status = val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (status & XILINX_PCIE_INTR_LINK_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		dev_warn(dev, "Link Down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	if (status & XILINX_PCIE_INTR_ECRC_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		dev_warn(dev, "ECRC failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (status & XILINX_PCIE_INTR_STR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		dev_warn(dev, "Streaming error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	if (status & XILINX_PCIE_INTR_HOT_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		dev_info(dev, "Hot reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		dev_warn(dev, "ECAM access timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	if (status & XILINX_PCIE_INTR_CORRECTABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		dev_warn(dev, "Correctable error message\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		xilinx_pcie_clear_err_interrupts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	if (status & XILINX_PCIE_INTR_NONFATAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		dev_warn(dev, "Non fatal error message\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		xilinx_pcie_clear_err_interrupts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	if (status & XILINX_PCIE_INTR_FATAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		dev_warn(dev, "Fatal error message\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		xilinx_pcie_clear_err_interrupts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		/* Check whether interrupt valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 			dev_warn(dev, "RP Intr FIFO1 read error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 			goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		/* Decode the IRQ number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 			val = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 				XILINX_PCIE_RPIFR2_MSG_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 			val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 				XILINX_PCIE_RPIFR1_INTR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 			val = irq_find_mapping(port->leg_domain, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		/* Clear interrupt FIFO register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 			   XILINX_PCIE_REG_RPIFR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		/* Handle the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		if (IS_ENABLED(CONFIG_PCI_MSI) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		    !(val & XILINX_PCIE_RPIFR1_MSI_INTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 			generic_handle_irq(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		dev_warn(dev, "Slave unsupported request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	if (status & XILINX_PCIE_INTR_SLV_UNEXP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		dev_warn(dev, "Slave unexpected completion\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	if (status & XILINX_PCIE_INTR_SLV_COMPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		dev_warn(dev, "Slave completion timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	if (status & XILINX_PCIE_INTR_SLV_ERRP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		dev_warn(dev, "Slave Error Poison\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	if (status & XILINX_PCIE_INTR_SLV_CMPABT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		dev_warn(dev, "Slave Completer Abort\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	if (status & XILINX_PCIE_INTR_SLV_ILLBUR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		dev_warn(dev, "Slave Illegal Burst\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	if (status & XILINX_PCIE_INTR_MST_DECERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		dev_warn(dev, "Master decode error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	if (status & XILINX_PCIE_INTR_MST_SLVERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		dev_warn(dev, "Master slave error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	if (status & XILINX_PCIE_INTR_MST_ERRP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		dev_warn(dev, "Master error poison\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	/* Clear the Interrupt Decode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	pcie_write(port, status, XILINX_PCIE_REG_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)  * xilinx_pcie_init_irq_domain - Initialize IRQ domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)  * @port: PCIe port information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)  * Return: '0' on success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	struct device *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	struct device_node *pcie_intc_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	/* Setup INTx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	pcie_intc_node = of_get_next_child(node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	if (!pcie_intc_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		dev_err(dev, "No PCIe Intc node found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	port->leg_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 						 &intx_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 						 port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	of_node_put(pcie_intc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	if (!port->leg_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		dev_err(dev, "Failed to get a INTx IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	/* Setup MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		port->msi_domain = irq_domain_add_linear(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 							 XILINX_NUM_MSI_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 							 &msi_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 							 &xilinx_pcie_msi_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 		if (!port->msi_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 			dev_err(dev, "Failed to get a MSI IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 		ret = xilinx_pcie_enable_msi(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)  * xilinx_pcie_init_port - Initialize hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)  * @port: PCIe port information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	struct device *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	if (xilinx_pcie_link_up(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		dev_info(dev, "PCIe Link is UP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 		dev_info(dev, "PCIe Link is DOWN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	/* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 		   XILINX_PCIE_REG_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	/* Clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 			 XILINX_PCIE_IMR_ALL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 		   XILINX_PCIE_REG_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	/* Enable all interrupts we handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	pcie_write(port, XILINX_PCIE_IMR_ENABLE_MASK, XILINX_PCIE_REG_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	/* Enable the Bridge enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 			 XILINX_PCIE_REG_RPSC_BEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 		   XILINX_PCIE_REG_RPSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)  * xilinx_pcie_parse_dt - Parse Device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)  * @port: PCIe port information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)  * Return: '0' on success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	struct device *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	struct resource regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	err = of_address_to_resource(node, 0, &regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 		dev_err(dev, "missing \"reg\" property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	port->reg_base = devm_pci_remap_cfg_resource(dev, &regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	if (IS_ERR(port->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 		return PTR_ERR(port->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	port->irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	err = devm_request_irq(dev, port->irq, xilinx_pcie_intr_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 			       IRQF_SHARED | IRQF_NO_THREAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 			       "xilinx-pcie", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 		dev_err(dev, "unable to request irq %d\n", port->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)  * xilinx_pcie_probe - Probe function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)  * @pdev: Platform device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)  * Return: '0' on success and error value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int xilinx_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	struct xilinx_pcie_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	if (!dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	port = pci_host_bridge_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	port->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	err = xilinx_pcie_parse_dt(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 		dev_err(dev, "Parsing DT failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 	xilinx_pcie_init_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	err = xilinx_pcie_init_irq_domain(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 		dev_err(dev, "Failed creating IRQ Domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	bridge->sysdata = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 	bridge->ops = &xilinx_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 	xilinx_pcie_msi_chip.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 	bridge->msi = &xilinx_pcie_msi_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 	return pci_host_probe(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const struct of_device_id xilinx_pcie_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 	{ .compatible = "xlnx,axi-pcie-host-1.00.a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static struct platform_driver xilinx_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 		.name = "xilinx-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 		.of_match_table = xilinx_pcie_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 	.probe = xilinx_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) builtin_platform_driver(xilinx_pcie_driver);