^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe host controller driver for NWL PCIe Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Based on pcie-xilinx.c, pci-tegra.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) Copyright 2014 - 2015, Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Bridge core config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BRCFG_PCIE_RX0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BRCFG_INTERRUPT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Egress - Bridge translation registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define E_BREG_CAPABILITIES 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define E_BREG_CONTROL 0x00000208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define E_BREG_BASE_LO 0x00000210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define E_BREG_BASE_HI 0x00000214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define E_ECAM_CAPABILITIES 0x00000220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define E_ECAM_CONTROL 0x00000228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define E_ECAM_BASE_LO 0x00000230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define E_ECAM_BASE_HI 0x00000234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Ingress - address translations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I_MSII_CAPABILITIES 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I_MSII_CONTROL 0x00000308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I_MSII_BASE_LO 0x00000310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I_MSII_BASE_HI 0x00000314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I_ISUB_CONTROL 0x000003E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SET_ISUB_CONTROL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Rxed msg fifo - Interrupt status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MSGF_MISC_STATUS 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MSGF_MISC_MASK 0x00000404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MSGF_LEG_STATUS 0x00000420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MSGF_LEG_MASK 0x00000424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MSGF_MSI_STATUS_LO 0x00000440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MSGF_MSI_STATUS_HI 0x00000444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MSGF_MSI_MASK_LO 0x00000448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MSGF_MSI_MASK_HI 0x0000044C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Msg filter mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CFG_ENABLE_PM_MSG_FWD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CFG_ENABLE_INT_MSG_FWD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CFG_ENABLE_ERR_MSG_FWD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CFG_ENABLE_INT_MSG_FWD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) CFG_ENABLE_ERR_MSG_FWD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Misc interrupt status mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MSGF_MISC_SR_RXMSG_OVER BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MSGF_MISC_SR_SLAVE_ERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MSGF_MISC_SR_MASTER_ERR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MSGF_MISC_SR_FATAL_AER BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MSGF_MISC_SR_CORR_AER BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MSGF_MISC_SR_UR_DETECT BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MSGF_MISC_SR_FATAL_DEV BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MSGF_MISC_SR_LINK_DOWN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MSGF_MISC_SR_RXMSG_OVER | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MSGF_MISC_SR_SLAVE_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MSGF_MISC_SR_MASTER_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MSGF_MISC_SR_I_ADDR_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MSGF_MISC_SR_E_ADDR_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MSGF_MISC_SR_FATAL_AER | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MSGF_MISC_SR_NON_FATAL_AER | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MSGF_MISC_SR_CORR_AER | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MSGF_MISC_SR_UR_DETECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MSGF_MISC_SR_NON_FATAL_DEV | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MSGF_MISC_SR_FATAL_DEV | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MSGF_MISC_SR_LINK_DOWN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MSGF_MSIC_SR_LINK_BWIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Legacy interrupt status mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MSGF_LEG_SR_INTA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MSGF_LEG_SR_INTB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MSGF_LEG_SR_INTC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MSGF_LEG_SR_INTD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* MSI interrupt status mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MSII_PRESENT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MSII_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MSII_STATUS_ENABLE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Bridge config interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BRCFG_INTERRUPT_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BREG_PRESENT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BREG_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BREG_ENABLE_FORCE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* E_ECAM status mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define E_ECAM_PRESENT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define E_ECAM_CR_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define E_ECAM_SIZE_LOC GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define E_ECAM_SIZE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ECAM_BUS_LOC_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ECAM_DEV_LOC_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define NWL_ECAM_VALUE_DEFAULT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CFG_DMA_REG_BAR GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define INT_PCI_MSI_NR (2 * 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Readin the PS_LINKUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PS_LINKUP_OFFSET 0x00000238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PCIE_PHY_LINKUP_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PHY_RDY_LINKUP_BIT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Parameters for the waiting for link up routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LINK_WAIT_MAX_RETRIES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LINK_WAIT_USLEEP_MIN 90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LINK_WAIT_USLEEP_MAX 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct nwl_msi { /* MSI information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct irq_domain *msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long *bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct irq_domain *dev_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct mutex lock; /* protect bitmap variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int irq_msi0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int irq_msi1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct nwl_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void __iomem *breg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void __iomem *pcireg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void __iomem *ecam_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) phys_addr_t phys_ecam_base; /* Physical Configuration Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 breg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 pcie_reg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 ecam_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int irq_intx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int irq_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 ecam_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 last_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct nwl_msi msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct irq_domain *legacy_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) raw_spinlock_t leg_mask_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return readl(pcie->breg_base + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writel(val, pcie->breg_base + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static bool nwl_phy_link_up(struct nwl_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int nwl_wait_for_link(struct nwl_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* check if the link is up or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (nwl_phy_link_up(pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(dev, "PHY link never came up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct nwl_pcie *pcie = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Check link before accessing downstream ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!pci_is_root_bus(bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!nwl_pcie_link_up(pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) } else if (devfn > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Only one device down on each root port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * nwl_pcie_map_bus - Get configuration base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @bus: Bus structure of current bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @devfn: Device/function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @where: Offset from base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Return: Base address of the configuration space needed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * accessed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct nwl_pcie *pcie = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int relbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!nwl_pcie_valid_device(bus, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) relbus = (bus->number << ECAM_BUS_LOC_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) (devfn << ECAM_DEV_LOC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return pcie->ecam_base + relbus + where;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* PCIe operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct pci_ops nwl_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .map_bus = nwl_pcie_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .read = pci_generic_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .write = pci_generic_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct nwl_pcie *pcie = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 misc_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Checking for misc interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MSGF_MISC_SR_MASKALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (!misc_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(dev, "Received Message FIFO Overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_err(dev, "Slave error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev_err(dev, "Master error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_err(dev, "In Misc Ingress address translation error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_err(dev, "In Misc Egress address translation error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (misc_stat & MSGF_MISC_SR_FATAL_AER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_err(dev, "Fatal Error in AER Capability\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(dev, "Non-Fatal Error in AER Capability\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (misc_stat & MSGF_MISC_SR_CORR_AER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(dev, "Correctable Error in AER Capability\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (misc_stat & MSGF_MISC_SR_UR_DETECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_err(dev, "Unsupported request Detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_err(dev, "Non-Fatal Error Detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_err(dev, "Fatal Error Detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_info(dev, "Link Bandwidth Management Status bit set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Clear misc interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void nwl_pcie_leg_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct nwl_pcie *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pcie = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MSGF_LEG_SR_MASKALL) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) for_each_set_bit(bit, &status, PCI_NUM_INTX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) virq = irq_find_mapping(pcie->legacy_irq_domain, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct nwl_msi *msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) msi = &pcie->msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) for_each_set_bit(bit, &status, 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) nwl_bridge_writel(pcie, 1 << bit, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) virq = irq_find_mapping(msi->dev_domain, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static void nwl_mask_leg_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct irq_desc *desc = irq_to_desc(data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct nwl_pcie *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) pcie = irq_desc_get_chip_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mask = 1 << (data->hwirq - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static void nwl_unmask_leg_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct irq_desc *desc = irq_to_desc(data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct nwl_pcie *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pcie = irq_desc_get_chip_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mask = 1 << (data->hwirq - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct irq_chip nwl_leg_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .name = "nwl_pcie:legacy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .irq_enable = nwl_unmask_leg_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .irq_disable = nwl_mask_leg_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .irq_mask = nwl_mask_leg_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .irq_unmask = nwl_unmask_leg_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) irq_set_chip_data(irq, domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) irq_set_status_flags(irq, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct irq_domain_ops legacy_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .map = nwl_legacy_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .xlate = pci_irqd_intx_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static struct irq_chip nwl_msi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .name = "nwl_pcie:msi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .irq_enable = pci_msi_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .irq_disable = pci_msi_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .irq_mask = pci_msi_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .irq_unmask = pci_msi_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static struct msi_domain_info nwl_msi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MSI_FLAG_MULTI_PCI_MSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .chip = &nwl_msi_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) msg->address_lo = lower_32_bits(msi_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) msg->address_hi = upper_32_bits(msi_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) msg->data = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int nwl_msi_set_affinity(struct irq_data *irq_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) const struct cpumask *mask, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static struct irq_chip nwl_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .name = "Xilinx MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .irq_compose_msi_msg = nwl_compose_msi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .irq_set_affinity = nwl_msi_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) unsigned int nr_irqs, void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct nwl_pcie *pcie = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct nwl_msi *msi = &pcie->msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) mutex_lock(&msi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) get_count_order(nr_irqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (bit < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mutex_unlock(&msi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) domain->host_data, handle_simple_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) mutex_unlock(&msi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct irq_data *data = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct nwl_msi *msi = &pcie->msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) mutex_lock(&msi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) bitmap_release_region(msi->bitmap, data->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) get_count_order(nr_irqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) mutex_unlock(&msi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const struct irq_domain_ops dev_msi_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .alloc = nwl_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .free = nwl_irq_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct nwl_msi *msi = &pcie->msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) &dev_msi_domain_ops, pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!msi->dev_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_err(dev, "failed to create dev IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) msi->msi_domain = pci_msi_create_irq_domain(fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) &nwl_msi_domain_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) msi->dev_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!msi->msi_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dev_err(dev, "failed to create msi IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) irq_domain_remove(msi->dev_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct device_node *legacy_intc_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) legacy_intc_node = of_get_next_child(node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (!legacy_intc_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_err(dev, "No legacy intc node found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PCI_NUM_INTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) &legacy_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) of_node_put(legacy_intc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!pcie->legacy_irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_err(dev, "failed to create IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) raw_spin_lock_init(&pcie->leg_mask_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) nwl_pcie_init_msi_irq_domain(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct nwl_msi *msi = &pcie->msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mutex_init(&msi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) msi->bitmap = kzalloc(size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (!msi->bitmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Get msi_1 IRQ number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (msi->irq_msi1 < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) irq_set_chained_handler_and_data(msi->irq_msi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) nwl_pcie_msi_handler_high, pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Get msi_0 IRQ number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (msi->irq_msi0 < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) irq_set_chained_handler_and_data(msi->irq_msi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) nwl_pcie_msi_handler_low, pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Check for msii_present bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_err(dev, "MSI not present\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Enable MSII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MSII_ENABLE, I_MSII_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Enable MSII status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) MSII_STATUS_ENABLE, I_MSII_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* setup AFI/FPCI range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) base = pcie->phys_pcie_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * For high range MSI interrupts: disable, clear any pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * and enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * For low range MSI interrupts: disable, clear any pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * and enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) kfree(msi->bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) msi->bitmap = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u32 breg_val, ecam_val, first_busno = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (!breg_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dev_err(dev, "BREG is not present\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return breg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Write bridge_off to breg base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) E_BREG_BASE_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) E_BREG_BASE_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Enable BREG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) E_BREG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Disable DMA channel registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Enable Ingress subtractive decode translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Enable msg filtering details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) BRCFG_PCIE_RX_MSG_FILTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) err = nwl_wait_for_link(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (!ecam_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_err(dev, "ECAM is not present\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return ecam_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Enable ECAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) E_ECAM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) E_ECAM_BASE_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) E_ECAM_BASE_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* Get bus range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Write primary, secondary and subordinate bus numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ecam_val = first_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ecam_val |= (first_busno + 1) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (nwl_pcie_link_up(pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_info(dev, "Link is UP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_info(dev, "Link is DOWN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* Get misc IRQ number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (pcie->irq_misc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) err = devm_request_irq(dev, pcie->irq_misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) nwl_pcie_misc_handler, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "nwl_pcie:misc", pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_err(dev, "fail to register misc IRQ#%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) pcie->irq_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* Disable all misc interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Clear pending misc interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Enable all misc interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* Disable all legacy interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Clear pending legacy interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* Enable all legacy interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Enable the bridge config interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) pcie->breg_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (IS_ERR(pcie->breg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return PTR_ERR(pcie->breg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) pcie->phys_breg_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) pcie->pcireg_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (IS_ERR(pcie->pcireg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return PTR_ERR(pcie->pcireg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) pcie->phys_pcie_reg_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (IS_ERR(pcie->ecam_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return PTR_ERR(pcie->ecam_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) pcie->phys_ecam_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Get intx IRQ number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (pcie->irq_intx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return pcie->irq_intx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) irq_set_chained_handler_and_data(pcie->irq_intx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) nwl_pcie_leg_handler, pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static const struct of_device_id nwl_pcie_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) { .compatible = "xlnx,nwl-pcie-2.11", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static int nwl_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct nwl_pcie *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) pcie = pci_host_bridge_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pcie->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) err = nwl_pcie_parse_dt(pcie, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_err(dev, "Parsing DT failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) pcie->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (IS_ERR(pcie->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return PTR_ERR(pcie->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) err = clk_prepare_enable(pcie->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_err(dev, "can't enable PCIe ref clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) err = nwl_pcie_bridge_init(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dev_err(dev, "HW Initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) err = nwl_pcie_init_irq_domain(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_err(dev, "Failed creating IRQ Domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) bridge->sysdata = pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) bridge->ops = &nwl_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (IS_ENABLED(CONFIG_PCI_MSI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) err = nwl_pcie_enable_msi(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_err(dev, "failed to enable MSI support: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return pci_host_probe(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static struct platform_driver nwl_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .name = "nwl-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .of_match_table = nwl_pcie_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .probe = nwl_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) builtin_platform_driver(nwl_pcie_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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