^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe driver for Renesas R-Car SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Phil Edworthy <phil.edworthy@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _PCIE_RCAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _PCIE_RCAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PCIECAR 0x000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PCIECCTLR 0x000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CONFIG_SEND_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TYPE0 (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TYPE1 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCIECDR 0x000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCIEMSR 0x000028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCIEINTXR 0x000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ASTINTX BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCIEPHYSR 0x0007f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PHYRDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCIEMSITXR 0x000840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Transfer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCIETCTLR 0x02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DL_DOWN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CFINIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCIETSTR 0x02004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DATA_LINK_ACTIVE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCIEERRFR 0x02020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UNSUPPORTED_REQUEST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCIEMSIFR 0x02044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCIEMSIALR 0x02048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MSIFE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCIEMSIAUR 0x0204c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCIEMSIIER 0x02050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* root port address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* local address reg & mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCIELAR(x) (0x02200 + ((x) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LAM_PREFETCH BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LAM_64BIT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LAR_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* PCIe address reg & mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PAR_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IO_SPACE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCICONF(x) (0x010000 + ((x) * 0x4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define INTDIS BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PMCAP(x) (0x010040 + ((x) * 0x4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MSICAP(x) (0x010050 + ((x) * 0x4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MSICAP0_MSIE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MSICAP0_MMESCAP_OFFSET 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MSICAP0_MMESE_OFFSET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MSICAP0_MMESE_MASK GENMASK(22, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EXPCAP(x) (0x010070 + ((x) * 0x4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VCCAP(x) (0x010100 + ((x) * 0x4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* link layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IDSETR0 0x011000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IDSETR1 0x011004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SUBIDSETR 0x011024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TLCTLR 0x011048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MACSR 0x011054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SPCHGFIN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPCHGFAIL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPCHGSUC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LINK_SPEED (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LINK_SPEED_2_5GTS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LINK_SPEED_5_0GTS (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MACCTLR 0x011058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MACCTLR_NFTS_MASK GENMASK(23, 16) /* The name is from SH7786 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SPEED_CHANGE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SCRAMBLE_DISABLE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LTSMDIS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_NFTS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PMSR 0x01105c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MACS2R 0x011078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MACCGSPSETR 0x011084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPCNGRSN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* R-Car H1 PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define H1_PCIEPHYADRR 0x04000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define WRITE_CMD BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PHY_ACK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RATE_POS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LANE_POS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ADR_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define H1_PCIEPHYDOUTR 0x040014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* R-Car Gen2 PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GEN2_PCIEPHYADDR 0x780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GEN2_PCIEPHYDATA 0x784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GEN2_PCIEPHYCTRL 0x78c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define INT_PCI_MSI_NR 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RCONF(x) (PCICONF(0) + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RPMCAP(x) (PMCAP(0) + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define REXPCAP(x) (EXPCAP(0) + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RVCCAP(x) (VCCAP(0) + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RCAR_PCI_MAX_RESOURCES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MAX_NR_INBOUND_MAPS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct rcar_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) RCAR_PCI_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) RCAR_PCI_ACCESS_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct resource_entry *window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u64 pci_addr, u64 flags, int idx, bool host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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