^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe driver for Renesas R-Car SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Phil Edworthy <phil.edworthy@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "pcie-rcar.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) writel(val, pcie->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) return readl(pcie->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned int shift = BITS_PER_BYTE * (where & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 val = rcar_pci_read_reg(pcie, where & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) val &= ~(mask << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) val |= data << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) rcar_pci_write_reg(pcie, val, where & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) while (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int timeout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) while (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct resource_entry *window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Setup PCIe address space mappings for each resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct resource *res = window->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) resource_size_t res_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * The PAMR mask is calculated in units of 128Bytes, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * keeps things pretty simple.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (size > 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mask = (roundup_pow_of_two(size) / SZ_128) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mask = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (res->flags & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) res_start = pci_pio_to_address(res->start) - window->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) res_start = res->start - window->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PCIEPALR(win));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* First resource is for IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mask = PAR_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (res->flags & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mask |= IO_SPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u64 pci_addr, u64 flags, int idx, bool host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Set up 64-bit inbound regions as the range parser doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * distinguish between 32 and 64-bit types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PCIEPRAR(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) rcar_pci_write_reg(pcie, flags, PCIELAMR(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PCIEPRAR(idx + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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