^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pcie-iproc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IPROC_MSI_INTR_EN_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IPROC_MSI_INTR_EN BIT(IPROC_MSI_INTR_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IPROC_MSI_INT_N_EVENT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IPROC_MSI_INT_N_EVENT BIT(IPROC_MSI_INT_N_EVENT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IPROC_MSI_EQ_EN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IPROC_MSI_EQ_EN BIT(IPROC_MSI_EQ_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IPROC_MSI_EQ_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Max number of GIC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NR_HW_IRQS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Number of entries in each event queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EQ_LEN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Size of each event queue memory region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EQ_MEM_REGION_SIZE SZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Size of each MSI address region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MSI_MEM_REGION_SIZE SZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum iproc_msi_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) IPROC_MSI_EQ_PAGE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) IPROC_MSI_EQ_PAGE_UPPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) IPROC_MSI_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) IPROC_MSI_PAGE_UPPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) IPROC_MSI_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) IPROC_MSI_EQ_HEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) IPROC_MSI_EQ_TAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) IPROC_MSI_INTS_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) IPROC_MSI_REG_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct iproc_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * iProc MSI group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * event queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @msi: pointer to iProc MSI data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @gic_irq: GIC interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @eq: Event queue number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct iproc_msi_grp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct iproc_msi *msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int gic_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int eq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * iProc event queue based MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Only meant to be used on platforms without MSI support integrated into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * GIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @pcie: pointer to iProc PCIe data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @reg_offsets: MSI register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @grps: MSI groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @nr_irqs: number of total interrupts connected to GIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @nr_cpus: number of toal CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @has_inten_reg: indicates the MSI interrupt enable register needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * set explicitly (required for some legacy platforms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @bitmap: MSI vector bitmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @bitmap_lock: lock to protect access to the MSI bitmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @nr_msi_vecs: total number of MSI vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @inner_domain: inner IRQ domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @msi_domain: MSI IRQ domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @nr_eq_region: required number of 4K aligned memory region for MSI event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @nr_msi_region: required number of 4K aligned address region for MSI posted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @eq_cpu: pointer to allocated memory region for MSI event queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @eq_dma: DMA address of MSI event queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @msi_addr: MSI address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct iproc_msi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct iproc_pcie *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct iproc_msi_grp *grps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int nr_cpus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) bool has_inten_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long *bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct mutex bitmap_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int nr_msi_vecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct irq_domain *inner_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct irq_domain *msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int nr_eq_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int nr_msi_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void *eq_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dma_addr_t eq_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) phys_addr_t msi_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const u16 iproc_msi_reg_paxb[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { 0x200, 0x2c0, 0x204, 0x2c4, 0x210, 0x250, 0x254, 0x208 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { 0x200, 0x2c0, 0x204, 0x2c4, 0x214, 0x258, 0x25c, 0x208 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { 0x200, 0x2c0, 0x204, 0x2c4, 0x218, 0x260, 0x264, 0x208 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { 0x200, 0x2c0, 0x204, 0x2c4, 0x21c, 0x268, 0x26c, 0x208 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { 0x200, 0x2c0, 0x204, 0x2c4, 0x220, 0x270, 0x274, 0x208 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 0x200, 0x2c0, 0x204, 0x2c4, 0x224, 0x278, 0x27c, 0x208 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const u16 iproc_msi_reg_paxc[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0xc00, 0xc04, 0xc08, 0xc0c, 0xc40, 0xc50, 0xc60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0xc10, 0xc14, 0xc18, 0xc1c, 0xc44, 0xc54, 0xc64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 0xc20, 0xc24, 0xc28, 0xc2c, 0xc48, 0xc58, 0xc68 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 0xc30, 0xc34, 0xc38, 0xc3c, 0xc4c, 0xc5c, 0xc6c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline u32 iproc_msi_read_reg(struct iproc_msi *msi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum iproc_msi_reg reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int eq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct iproc_pcie *pcie = msi->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline void iproc_msi_write_reg(struct iproc_msi *msi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) enum iproc_msi_reg reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int eq, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct iproc_pcie *pcie = msi->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return (hwirq % msi->nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline unsigned int iproc_msi_addr_offset(struct iproc_msi *msi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (msi->nr_msi_region > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return hwirq_to_group(msi, hwirq) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (msi->nr_eq_region > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return eq * EQ_MEM_REGION_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return eq * EQ_LEN * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct irq_chip iproc_msi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "iProc-MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct msi_domain_info iproc_msi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MSI_FLAG_PCI_MSIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .chip = &iproc_msi_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * In iProc PCIe core, each MSI group is serviced by a GIC interrupt and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * dedicated event queue. Each MSI group can support up to 64 MSI vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * The number of MSI groups varies between different iProc SoCs. The total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * number of CPU cores also varies. To support MSI IRQ affinity, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * distribute GIC interrupts across all available CPUs. MSI vector is moved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * from one GIC interrupt to another to steer to the target CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Assuming:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * - the number of MSI groups is M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * - the number of CPU cores is N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * - M is always a multiple of N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Total number of raw MSI vectors = M * 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * Total number of supported MSI vectors = (M * 64) / N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return (hwirq % msi->nr_cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static inline unsigned long hwirq_to_canonical_hwirq(struct iproc_msi *msi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return (hwirq - hwirq_to_cpu(msi, hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int iproc_msi_irq_set_affinity(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) const struct cpumask *mask, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int target_cpu = cpumask_first(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int curr_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) curr_cpu = hwirq_to_cpu(msi, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (curr_cpu == target_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = IRQ_SET_MASK_OK_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* steer MSI to the target CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = IRQ_SET_MASK_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) irq_data_update_effective_affinity(data, cpumask_of(target_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void iproc_msi_irq_compose_msi_msg(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) addr = msi->msi_addr + iproc_msi_addr_offset(msi, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) msg->address_lo = lower_32_bits(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) msg->address_hi = upper_32_bits(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) msg->data = data->hwirq << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct irq_chip iproc_msi_bottom_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .irq_set_affinity = iproc_msi_irq_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .irq_compose_msi_msg = iproc_msi_irq_compose_msi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int iproc_msi_irq_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned int virq, unsigned int nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct iproc_msi *msi = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int hwirq, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (msi->nr_cpus > 1 && nr_irqs > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) mutex_lock(&msi->bitmap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * Allocate 'nr_irqs' multiplied by 'nr_cpus' number of MSI vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * each time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) hwirq = bitmap_find_free_region(msi->bitmap, msi->nr_msi_vecs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) order_base_2(msi->nr_cpus * nr_irqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mutex_unlock(&msi->bitmap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (hwirq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) irq_domain_set_info(domain, virq + i, hwirq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) &iproc_msi_bottom_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) domain->host_data, handle_simple_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void iproc_msi_irq_domain_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned int virq, unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct irq_data *data = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mutex_lock(&msi->bitmap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) bitmap_release_region(msi->bitmap, hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) order_base_2(msi->nr_cpus * nr_irqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mutex_unlock(&msi->bitmap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) irq_domain_free_irqs_parent(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct irq_domain_ops msi_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .alloc = iproc_msi_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .free = iproc_msi_irq_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 __iomem *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned int offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) msg = (u32 __iomem *)(msi->eq_cpu + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) hwirq = readl(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) hwirq = (hwirq >> 5) + (hwirq & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * Since we have multiple hwirq mapped to a single MSI vector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * now we need to derive the hwirq at CPU0. It can then be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * mapped back to virq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return hwirq_to_canonical_hwirq(msi, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void iproc_msi_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct iproc_msi_grp *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct iproc_msi *msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 eq, head, tail, nr_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned long hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) grp = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) msi = grp->msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) eq = grp->eq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * iProc MSI event queue is tracked by head and tail pointers. Head
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * pointer indicates the next entry (MSI data) to be consumed by SW in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * the queue and needs to be updated by SW. iProc MSI core uses the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * tail pointer as the next data insertion point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * Entries between head and tail pointers contain valid MSI data. MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * data is guaranteed to be in the event queue memory before the tail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * pointer is updated by the iProc MSI core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) head = iproc_msi_read_reg(msi, IPROC_MSI_EQ_HEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) eq) & IPROC_MSI_EQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) tail = iproc_msi_read_reg(msi, IPROC_MSI_EQ_TAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) eq) & IPROC_MSI_EQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Figure out total number of events (MSI data) to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) nr_events = (tail < head) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) (EQ_LEN - (head - tail)) : (tail - head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!nr_events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* process all outstanding events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) while (nr_events--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) hwirq = decode_msi_hwirq(msi, eq, head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) virq = irq_find_mapping(msi->inner_domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) head++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) head %= EQ_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Now all outstanding events have been processed. Update the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * head pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) iproc_msi_write_reg(msi, IPROC_MSI_EQ_HEAD, eq, head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Now go read the tail pointer again to see if there are new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * outstanding events that came in during the above window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } while (true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void iproc_msi_enable(struct iproc_msi *msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int i, eq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Program memory region for each event queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) for (i = 0; i < msi->nr_eq_region; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dma_addr_t addr = msi->eq_dma + (i * EQ_MEM_REGION_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) lower_32_bits(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE_UPPER, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) upper_32_bits(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Program address region for MSI posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) for (i = 0; i < msi->nr_msi_region; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) phys_addr_t addr = msi->msi_addr + (i * MSI_MEM_REGION_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) iproc_msi_write_reg(msi, IPROC_MSI_PAGE, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) lower_32_bits(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) iproc_msi_write_reg(msi, IPROC_MSI_PAGE_UPPER, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) upper_32_bits(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) for (eq = 0; eq < msi->nr_irqs; eq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Enable MSI event queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) val = IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) IPROC_MSI_EQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * Some legacy platforms require the MSI interrupt enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * register to be set explicitly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (msi->has_inten_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) val |= BIT(eq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void iproc_msi_disable(struct iproc_msi *msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 eq, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) for (eq = 0; eq < msi->nr_irqs; eq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (msi->has_inten_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) val &= ~BIT(eq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) val = iproc_msi_read_reg(msi, IPROC_MSI_CTRL, eq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) val &= ~(IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) IPROC_MSI_EQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int iproc_msi_alloc_domains(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct iproc_msi *msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_msi_vecs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) &msi_domain_ops, msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!msi->inner_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) &iproc_msi_domain_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) msi->inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!msi->msi_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) irq_domain_remove(msi->inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static void iproc_msi_free_domains(struct iproc_msi *msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (msi->msi_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) irq_domain_remove(msi->msi_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (msi->inner_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) irq_domain_remove(msi->inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void iproc_msi_irq_free(struct iproc_msi *msi, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int iproc_msi_irq_setup(struct iproc_msi *msi, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) cpumask_var_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct iproc_pcie *pcie = msi->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) iproc_msi_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) &msi->grps[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Dedicate GIC interrupt to each CPU core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cpumask_clear(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) cpumask_set_cpu(cpu, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = irq_set_affinity(msi->grps[i].gic_irq, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_err(pcie->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "failed to set affinity for IRQ%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) msi->grps[i].gic_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) free_cpumask_var(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(pcie->dev, "failed to alloc CPU mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Free all configured/unconfigured IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) iproc_msi_irq_free(msi, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct iproc_msi *msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!of_device_is_compatible(node, "brcm,iproc-msi"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (!of_find_property(node, "msi-controller", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (pcie->msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) msi = devm_kzalloc(pcie->dev, sizeof(*msi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) msi->pcie = pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pcie->msi = msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) msi->msi_addr = pcie->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mutex_init(&msi->bitmap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) msi->nr_cpus = num_possible_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (msi->nr_cpus == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) iproc_msi_domain_info.flags |= MSI_FLAG_MULTI_PCI_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) msi->nr_irqs = of_irq_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (!msi->nr_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_err(pcie->dev, "found no MSI GIC interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (msi->nr_irqs > NR_HW_IRQS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_warn(pcie->dev, "too many MSI GIC interrupts defined %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) msi->nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) msi->nr_irqs = NR_HW_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (msi->nr_irqs < msi->nr_cpus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev_err(pcie->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "not enough GIC interrupts for MSI affinity\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (msi->nr_irqs % msi->nr_cpus != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) msi->nr_irqs -= msi->nr_irqs % msi->nr_cpus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev_warn(pcie->dev, "Reducing number of interrupts to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) msi->nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) switch (pcie->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case IPROC_PCIE_PAXB_BCMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case IPROC_PCIE_PAXB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) msi->reg_offsets = iproc_msi_reg_paxb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) msi->nr_eq_region = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) msi->nr_msi_region = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case IPROC_PCIE_PAXC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) msi->reg_offsets = iproc_msi_reg_paxc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) msi->nr_eq_region = msi->nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) msi->nr_msi_region = msi->nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (of_find_property(node, "brcm,pcie-msi-inten", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) msi->has_inten_reg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) msi->nr_msi_vecs = msi->nr_irqs * EQ_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) msi->bitmap = devm_kcalloc(pcie->dev, BITS_TO_LONGS(msi->nr_msi_vecs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) sizeof(*msi->bitmap), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!msi->bitmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) msi->grps = devm_kcalloc(pcie->dev, msi->nr_irqs, sizeof(*msi->grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (!msi->grps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) for (i = 0; i < msi->nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned int irq = irq_of_parse_and_map(node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_err(pcie->dev, "unable to parse/map interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) goto free_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) msi->grps[i].gic_irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) msi->grps[i].msi = msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) msi->grps[i].eq = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Reserve memory for event queue and make sure memories are zeroed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) msi->eq_cpu = dma_alloc_coherent(pcie->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) msi->nr_eq_region * EQ_MEM_REGION_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) &msi->eq_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (!msi->eq_cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) goto free_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = iproc_msi_alloc_domains(node, msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_err(pcie->dev, "failed to create MSI domains\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) goto free_eq_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = iproc_msi_irq_setup(msi, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) goto free_msi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) iproc_msi_enable(msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) free_msi_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) for_each_online_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) iproc_msi_irq_free(msi, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) iproc_msi_free_domains(msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) free_eq_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) msi->eq_cpu, msi->eq_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) free_irqs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) for (i = 0; i < msi->nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (msi->grps[i].gic_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) irq_dispose_mapping(msi->grps[i].gic_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) pcie->msi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) EXPORT_SYMBOL(iproc_msi_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) void iproc_msi_exit(struct iproc_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct iproc_msi *msi = pcie->msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) unsigned int i, cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (!msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) iproc_msi_disable(msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) for_each_online_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) iproc_msi_irq_free(msi, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) iproc_msi_free_domains(msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) msi->eq_cpu, msi->eq_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) for (i = 0; i < msi->nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (msi->grps[i].gic_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) irq_dispose_mapping(msi->grps[i].gic_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) EXPORT_SYMBOL(iproc_msi_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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