Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Altera PCIe MSI support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Ley Foon Tan <lftan@altera.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright Altera Corporation (C) 2013-2015. All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MSI_STATUS		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MSI_ERROR		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MSI_INTMASK		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MAX_MSI_VECTORS		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) struct altera_msi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	DECLARE_BITMAP(used, MAX_MSI_VECTORS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct mutex		lock;	/* protect "used" bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct platform_device	*pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct irq_domain	*msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct irq_domain	*inner_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	void __iomem		*csr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	void __iomem		*vector_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	phys_addr_t		vector_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u32			num_of_vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	int			irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static inline void msi_writel(struct altera_msi *msi, const u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			      const u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	writel_relaxed(value, msi->csr_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static inline u32 msi_readl(struct altera_msi *msi, const u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return readl_relaxed(msi->csr_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void altera_msi_isr(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct altera_msi *msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u32 virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	msi = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	while ((status = msi_readl(msi, MSI_STATUS)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		for_each_set_bit(bit, &status, msi->num_of_vectors) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			/* Dummy read from vector to clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			readl_relaxed(msi->vector_base + (bit * sizeof(u32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			virq = irq_find_mapping(msi->inner_domain, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			if (virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 				generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 				dev_err(&msi->pdev->dev, "unexpected MSI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static struct irq_chip altera_msi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.name = "Altera PCIe MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.irq_mask = pci_msi_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.irq_unmask = pci_msi_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static struct msi_domain_info altera_msi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		     MSI_FLAG_PCI_MSIX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.chip	= &altera_msi_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void altera_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct altera_msi *msi = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	phys_addr_t addr = msi->vector_phy + (data->hwirq * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	msg->address_lo = lower_32_bits(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	msg->address_hi = upper_32_bits(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	msg->data = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	dev_dbg(&msi->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		(int)data->hwirq, msg->address_hi, msg->address_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int altera_msi_set_affinity(struct irq_data *irq_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				   const struct cpumask *mask, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct irq_chip altera_msi_bottom_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.name			= "Altera MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.irq_compose_msi_msg	= altera_compose_msi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.irq_set_affinity	= altera_msi_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int altera_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				   unsigned int nr_irqs, void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct altera_msi *msi = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	unsigned long bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	WARN_ON(nr_irqs != 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	mutex_lock(&msi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	bit = find_first_zero_bit(msi->used, msi->num_of_vectors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (bit >= msi->num_of_vectors) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		mutex_unlock(&msi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	set_bit(bit, msi->used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	mutex_unlock(&msi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	irq_domain_set_info(domain, virq, bit, &altera_msi_bottom_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			    domain->host_data, handle_simple_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			    NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	mask = msi_readl(msi, MSI_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	mask |= 1 << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	msi_writel(msi, mask, MSI_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void altera_irq_domain_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				   unsigned int virq, unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct altera_msi *msi = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	mutex_lock(&msi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (!test_bit(d->hwirq, msi->used)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		dev_err(&msi->pdev->dev, "trying to free unused MSI#%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		__clear_bit(d->hwirq, msi->used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		mask = msi_readl(msi, MSI_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		mask &= ~(1 << d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		msi_writel(msi, mask, MSI_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	mutex_unlock(&msi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct irq_domain_ops msi_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.alloc	= altera_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.free	= altera_irq_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int altera_allocate_domains(struct altera_msi *msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct fwnode_handle *fwnode = of_node_to_fwnode(msi->pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	msi->inner_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 					     &msi_domain_ops, msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (!msi->inner_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		dev_err(&msi->pdev->dev, "failed to create IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	msi->msi_domain = pci_msi_create_irq_domain(fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				&altera_msi_domain_info, msi->inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (!msi->msi_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		dev_err(&msi->pdev->dev, "failed to create MSI domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		irq_domain_remove(msi->inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void altera_free_domains(struct altera_msi *msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	irq_domain_remove(msi->msi_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	irq_domain_remove(msi->inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int altera_msi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct altera_msi *msi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	msi_writel(msi, 0, MSI_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	irq_set_chained_handler(msi->irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	irq_set_handler_data(msi->irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	altera_free_domains(msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	platform_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int altera_msi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct altera_msi *msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	msi = devm_kzalloc(&pdev->dev, sizeof(struct altera_msi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			   GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (!msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	mutex_init(&msi->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	msi->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	msi->csr_base = devm_platform_ioremap_resource_byname(pdev, "csr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (IS_ERR(msi->csr_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		dev_err(&pdev->dev, "failed to map csr memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		return PTR_ERR(msi->csr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 					   "vector_slave");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	msi->vector_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (IS_ERR(msi->vector_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		dev_err(&pdev->dev, "failed to map vector_slave memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return PTR_ERR(msi->vector_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	msi->vector_phy = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (of_property_read_u32(np, "num-vectors", &msi->num_of_vectors)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		dev_err(&pdev->dev, "failed to parse the number of vectors\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	ret = altera_allocate_domains(msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	msi->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (msi->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		ret = msi->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	irq_set_chained_handler_and_data(msi->irq, altera_msi_isr, msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	platform_set_drvdata(pdev, msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	altera_msi_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct of_device_id altera_msi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	{ .compatible = "altr,msi-1.0", NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct platform_driver altera_msi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.name = "altera-msi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		.of_match_table = altera_msi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.probe = altera_msi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.remove = altera_msi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int __init altera_msi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return platform_driver_register(&altera_msi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static void __exit altera_msi_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	platform_driver_unregister(&altera_msi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) subsys_initcall(altera_msi_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MODULE_DEVICE_TABLE(of, altera_msi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) module_exit(altera_msi_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_LICENSE("GPL v2");