^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * APM X-Gene MSI Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014, Applied Micro Circuits Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Tanmay Inamdar <tinamdar@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Duc Dang <dhdang@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MSI_IR0 0x000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MSI_INT0 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IDX_PER_GROUP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IRQS_PER_IDX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define NR_HW_IRQS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NR_MSI_VEC (IDX_PER_GROUP * IRQS_PER_IDX * NR_HW_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct xgene_msi_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct xgene_msi *msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int gic_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 msi_grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct xgene_msi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct irq_domain *inner_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct irq_domain *msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u64 msi_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *msi_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long *bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct mutex bitmap_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct xgene_msi_group *msi_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int num_cpus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Global data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct xgene_msi xgene_msi_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static struct irq_chip xgene_msi_top_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .name = "X-Gene1 MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .irq_enable = pci_msi_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .irq_disable = pci_msi_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .irq_mask = pci_msi_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .irq_unmask = pci_msi_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct msi_domain_info xgene_msi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MSI_FLAG_PCI_MSIX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .chip = &xgene_msi_top_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * n is group number (0..F), x is index of registers in each group (0..7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * The register layout is as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * MSI0IR0 base_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * MSI0IR1 base_addr + 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * ... ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * MSI0IR6 base_addr + 0x60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * MSI0IR7 base_addr + 0x70000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * MSI1IR0 base_addr + 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * MSI1IR1 base_addr + 0x90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * ... ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * MSI1IR7 base_addr + 0xF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * MSI2IR0 base_addr + 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * ... ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * MSIFIR0 base_addr + 0x780000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * MSIFIR1 base_addr + 0x790000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * ... ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * MSIFIR7 base_addr + 0x7F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * MSIINT0 base_addr + 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * MSIINT1 base_addr + 0x810000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * ... ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * MSIINTF base_addr + 0x8F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Each index register supports 16 MSI vectors (0..15) to generate interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * There are total 16 GIC IRQs assigned for these 16 groups of MSI termination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * the MSI pending status caused by 1 of its 8 index registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* MSInIRx read helper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static u32 xgene_msi_ir_read(struct xgene_msi *msi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 msi_grp, u32 msir_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return readl_relaxed(msi->msi_regs + MSI_IR0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (msi_grp << 19) + (msir_idx << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* MSIINTn read helper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static u32 xgene_msi_int_read(struct xgene_msi *msi, u32 msi_grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return readl_relaxed(msi->msi_regs + MSI_INT0 + (msi_grp << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * With 2048 MSI vectors supported, the MSI message can be constructed using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * following scheme:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * - Divide into 8 256-vector groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Group 0: 0-255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Group 1: 256-511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Group 2: 512-767
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Group 7: 1792-2047
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * - Each 256-vector group is divided into 16 16-vector groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * As an example: 16 16-vector groups for 256-vector group 0-255 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Group 0: 0-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Group 1: 16-32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Group 15: 240-255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * - The termination address of MSI vector in 256-vector group n and 16-vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * group x is the address of MSIxIRn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * - The data for MSI vector in 16-vector group x is x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static u32 hwirq_to_reg_set(unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return (hwirq / (NR_HW_IRQS * IRQS_PER_IDX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static u32 hwirq_to_group(unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return (hwirq % NR_HW_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static u32 hwirq_to_msi_data(unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return ((hwirq / NR_HW_IRQS) % IRQS_PER_IDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void xgene_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct xgene_msi *msi = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 reg_set = hwirq_to_reg_set(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 group = hwirq_to_group(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u64 target_addr = msi->msi_addr + (((8 * group) + reg_set) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) msg->address_hi = upper_32_bits(target_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) msg->address_lo = lower_32_bits(target_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) msg->data = hwirq_to_msi_data(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * X-Gene v1 only has 16 MSI GIC IRQs for 2048 MSI vectors. To maintain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * the expected behaviour of .set_affinity for each MSI interrupt, the 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * MSI GIC IRQs are statically allocated to 8 X-Gene v1 cores (2 GIC IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * for each core). The MSI vector is moved fom 1 MSI GIC IRQ to another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * MSI GIC IRQ to steer its MSI interrupt to correct X-Gene v1 core. As a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * consequence, the total MSI vectors that X-Gene v1 supports will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * reduced to 256 (2048/8) vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int hwirq_to_cpu(unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return (hwirq % xgene_msi_ctrl.num_cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static unsigned long hwirq_to_canonical_hwirq(unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return (hwirq - hwirq_to_cpu(hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int xgene_msi_set_affinity(struct irq_data *irqdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) const struct cpumask *mask, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int target_cpu = cpumask_first(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int curr_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) curr_cpu = hwirq_to_cpu(irqdata->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (curr_cpu == target_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return IRQ_SET_MASK_OK_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Update MSI number to target the new CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) irqdata->hwirq = hwirq_to_canonical_hwirq(irqdata->hwirq) + target_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return IRQ_SET_MASK_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct irq_chip xgene_msi_bottom_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .name = "MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .irq_set_affinity = xgene_msi_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .irq_compose_msi_msg = xgene_compose_msi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int xgene_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int nr_irqs, void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct xgene_msi *msi = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int msi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mutex_lock(&msi->bitmap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) msi_irq = bitmap_find_next_zero_area(msi->bitmap, NR_MSI_VEC, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) msi->num_cpus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (msi_irq < NR_MSI_VEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bitmap_set(msi->bitmap, msi_irq, msi->num_cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) msi_irq = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mutex_unlock(&msi->bitmap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (msi_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return msi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) irq_domain_set_info(domain, virq, msi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) &xgene_msi_bottom_irq_chip, domain->host_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) handle_simple_irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void xgene_irq_domain_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int virq, unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct irq_data *d = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct xgene_msi *msi = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mutex_lock(&msi->bitmap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) hwirq = hwirq_to_canonical_hwirq(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) bitmap_clear(msi->bitmap, hwirq, msi->num_cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mutex_unlock(&msi->bitmap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) irq_domain_free_irqs_parent(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct irq_domain_ops msi_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .alloc = xgene_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .free = xgene_irq_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int xgene_allocate_domains(struct xgene_msi *msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) msi->inner_domain = irq_domain_add_linear(NULL, NR_MSI_VEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) &msi_domain_ops, msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!msi->inner_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(msi->node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) &xgene_msi_domain_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) msi->inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!msi->msi_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) irq_domain_remove(msi->inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void xgene_free_domains(struct xgene_msi *msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (msi->msi_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) irq_domain_remove(msi->msi_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (msi->inner_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) irq_domain_remove(msi->inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int xgene_msi_init_allocator(struct xgene_msi *xgene_msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int size = BITS_TO_LONGS(NR_MSI_VEC) * sizeof(long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) xgene_msi->bitmap = kzalloc(size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!xgene_msi->bitmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mutex_init(&xgene_msi->bitmap_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) xgene_msi->msi_groups = kcalloc(NR_HW_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) sizeof(struct xgene_msi_group),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!xgene_msi->msi_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void xgene_msi_isr(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct xgene_msi_group *msi_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct xgene_msi *xgene_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int msir_index, msir_val, hw_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 intr_index, grp_select, msi_grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) msi_groups = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) xgene_msi = msi_groups->msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) msi_grp = msi_groups->msi_grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * If bit x of this register is set (x is 0..7), one or more interupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * corresponding to MSInIRx is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) grp_select = xgene_msi_int_read(xgene_msi, msi_grp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) while (grp_select) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) msir_index = ffs(grp_select) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Calculate MSInIRx address to read to check for interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * (refer to termination address and data assignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * described in xgene_compose_msi_msg() )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) msir_val = xgene_msi_ir_read(xgene_msi, msi_grp, msir_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) while (msir_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) intr_index = ffs(msir_val) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * Calculate MSI vector number (refer to the termination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * address and data assignment described in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * xgene_compose_msi_msg function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) hw_irq = (((msir_index * IRQS_PER_IDX) + intr_index) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) NR_HW_IRQS) + msi_grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * As we have multiple hw_irq that maps to single MSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * always look up the virq using the hw_irq as seen from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * CPU0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) hw_irq = hwirq_to_canonical_hwirq(hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) virq = irq_find_mapping(xgene_msi->inner_domain, hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) WARN_ON(!virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (virq != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) msir_val &= ~(1 << intr_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) grp_select &= ~(1 << msir_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!grp_select) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * We handled all interrupts happened in this group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * resample this group MSI_INTx register in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * something else has been made pending in the meantime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) grp_select = xgene_msi_int_read(xgene_msi, msi_grp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static enum cpuhp_state pci_xgene_online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int xgene_msi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct xgene_msi *msi = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (pci_xgene_online)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) cpuhp_remove_state(pci_xgene_online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) cpuhp_remove_state(CPUHP_PCI_XGENE_DEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) kfree(msi->msi_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) kfree(msi->bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) msi->bitmap = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) xgene_free_domains(msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int xgene_msi_hwirq_alloc(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct xgene_msi *msi = &xgene_msi_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct xgene_msi_group *msi_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) cpumask_var_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) msi_group = &msi->msi_groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!msi_group->gic_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) irq_set_chained_handler_and_data(msi_group->gic_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) xgene_msi_isr, msi_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * Statically allocate MSI GIC IRQs to each CPU core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * to each core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) cpumask_clear(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) cpumask_set_cpu(cpu, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) err = irq_set_affinity(msi_group->gic_irq, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pr_err("failed to set affinity for GIC IRQ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) free_cpumask_var(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pr_err("failed to alloc CPU mask for affinity\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) irq_set_chained_handler_and_data(msi_group->gic_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int xgene_msi_hwirq_free(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct xgene_msi *msi = &xgene_msi_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct xgene_msi_group *msi_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) msi_group = &msi->msi_groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!msi_group->gic_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) irq_set_chained_handler_and_data(msi_group->gic_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const struct of_device_id xgene_msi_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {.compatible = "apm,xgene1-msi"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int xgene_msi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int rc, irq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct xgene_msi *xgene_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int virt_msir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 msi_val, msi_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) xgene_msi = &xgene_msi_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) platform_set_drvdata(pdev, xgene_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) xgene_msi->msi_regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (IS_ERR(xgene_msi->msi_regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_err(&pdev->dev, "no reg space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) rc = PTR_ERR(xgene_msi->msi_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) xgene_msi->msi_addr = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) xgene_msi->node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) xgene_msi->num_cpus = num_possible_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) rc = xgene_msi_init_allocator(xgene_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_err(&pdev->dev, "Error allocating MSI bitmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) rc = xgene_allocate_domains(xgene_msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_err(&pdev->dev, "Failed to allocate MSI domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) virt_msir = platform_get_irq(pdev, irq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (virt_msir < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) rc = virt_msir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) xgene_msi->msi_groups[irq_index].gic_irq = virt_msir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) xgene_msi->msi_groups[irq_index].msi_grp = irq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) xgene_msi->msi_groups[irq_index].msi = xgene_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * MSInIRx registers are read-to-clear; before registering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * interrupt handlers, read all of them to clear spurious
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * interrupts that may occur before the driver is probed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) for (msi_idx = 0; msi_idx < IDX_PER_GROUP; msi_idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) xgene_msi_ir_read(xgene_msi, irq_index, msi_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Read MSIINTn to confirm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) msi_val = xgene_msi_int_read(xgene_msi, irq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (msi_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_err(&pdev->dev, "Failed to clear spurious IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "pci/xgene:online",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) xgene_msi_hwirq_alloc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) goto err_cpuhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pci_xgene_online = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) rc = cpuhp_setup_state(CPUHP_PCI_XGENE_DEAD, "pci/xgene:dead", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) xgene_msi_hwirq_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto err_cpuhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dev_info(&pdev->dev, "APM X-Gene PCIe MSI driver loaded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) err_cpuhp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_err(&pdev->dev, "failed to add CPU MSI notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) xgene_msi_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static struct platform_driver xgene_msi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .name = "xgene-msi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .of_match_table = xgene_msi_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .probe = xgene_msi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .remove = xgene_msi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static int __init xgene_pcie_msi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return platform_driver_register(&xgene_msi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) subsys_initcall(xgene_pcie_msi_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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